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AgeCommit message (Expand)AuthorFilesLines
2022-11-04sim: build: remove various obsolete generation dep variablesMike Frysinger1-14/+0
2022-11-02sim: common: change sim_{fetch,store}_register helpers to use void* buffersMike Frysinger1-2/+2
2022-10-31sim: reg: constify store helperMike Frysinger1-1/+1
2022-05-13sim: remove use of PTRAlan Modra1-2/+2
2022-01-01sim: tweak copyright lines for gnulib update-copyrightMike Frysinger1-1/+1
2022-01-01Automatic Copyright Year update after running gdb/copyright.pyJoel Brobecker35-35/+35
2021-12-09sim: use ## for automake commentsMike Frysinger1-19/+19
2021-11-28sim: frv: resolve syscalls dynamicallyMike Frysinger1-2/+1
2021-11-19sim: install various doc filesMike Frysinger1-0/+3
2021-11-16sim: callback: expose argv & environMike Frysinger1-1/+8
2021-11-16sim: keep track of program environment stringsMike Frysinger1-1/+7
2021-11-15sim: split program path out of argv vectorMike Frysinger1-5/+1
2021-11-10sim: frv: flip trapdump default back to offMike Frysinger1-1/+1
2021-11-02sim: hoist cgen mloop rules up to common buildsMike Frysinger2-12/+38
2021-11-01sim: frv: reduce -Wno-error scopeMike Frysinger1-2/+2
2021-10-31sim: tighten up stamp rulesMike Frysinger1-1/+2
2021-10-31sim: silence stamp touch rulesMike Frysinger1-3/+3
2021-10-31sim: standardize move-if-change rulesMike Frysinger1-2/+2
2021-08-17sim: rename ChangeLog files to ChangeLog-2021Mike Frysinger1-0/+0
2021-06-30sim: cris/frv/iq2000/lm32: merge with common configure scriptMike Frysinger5-2944/+41
2021-06-30sim: unify scache settingsMike Frysinger4-29/+7
2021-06-30sim: frv: scope the unique configure flagMike Frysinger4-29/+41
2021-06-30sim: move default model to the runtime sim stateMike Frysinger5-24/+9
2021-06-30sim: namespace sim_machsMike Frysinger3-1/+11
2021-06-29sim: model: constify sim_machs storageMike Frysinger2-1/+5
2021-06-28sim: cgen: delete unused record_trace_results functionsMike Frysinger2-8/+4
2021-06-27sim: frv: add missing const typeMike Frysinger2-1/+5
2021-06-27sim: frv: fix engine hookMike Frysinger2-1/+5
2021-06-27sim: frv: fix up various missing prototype warningsMike Frysinger6-1/+22
2021-06-27sim: frv: fix some printf type mismatch warningsMike Frysinger3-2/+7
2021-06-27sim: frv: fix uninitialized variable warningMike Frysinger2-2/+6
2021-06-27sim: frv: fix return type for post_wait_for funcsMike Frysinger3-19/+31
2021-06-27sim: frv: fix ambiguous else compiler warningsMike Frysinger4-25/+43
2021-06-22sim: drop configure scripts for simple portsMike Frysinger2-0/+11
2021-06-21sim: unify hardware settingsMike Frysinger3-49/+5
2021-06-21sim: hw: rework configure option & device selectionMike Frysinger2-37/+29
2021-06-20sim: delete SIM_AC_COMMON macroMike Frysinger4-5/+5
2021-06-20sim: unify general maintainer settingsMike Frysinger3-124/+5
2021-06-20sim: unify cgen maintainer settingsMike Frysinger5-45/+6
2021-06-20sim: move sim-inline to the common codeMike Frysinger3-36/+5
2021-06-19sim: unify gettext/intl probing logicMike Frysinger2-85/+0
2021-06-19sim: unify toolchain dependency logicMike Frysinger2-1109/+1
2021-06-19sim: unify toolchain probing logicMike Frysinger2-1360/+26
2021-06-19sim: unify bfd library dependency testing logicMike Frysinger3-7691/+6
2021-06-19sim: unify various library testing logicMike Frysinger2-141/+6
2021-06-18sim: unify -Werror build settingsMike Frysinger3-112/+6
2021-06-18sim: move -Werror disabling to MakefileMike Frysinger4-59/+69
2021-06-18sim: split sim-signal.h include outMike Frysinger3-0/+7
2021-06-17sim: overhaul & unify endian settings managementMike Frysinger5-56/+9
2021-06-17sim: split sim/callback.h include outMike Frysinger2-0/+5
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