riscv-gnu-toolchain/gdb.git - Unnamed repository; edit this file 'description' to name the repository.

Age	Commit message (Expand)	Author	Files	Lines
2016-01-03	sim: drop host endian configure option	Mike Frysinger	1	-1/+1
2016-01-01	GDB copyright headers update after running GDB's copyright.py script.	Joel Brobecker	1	-1/+1
2015-05-17	sim: erc32: restore attribution	Mike Frysinger	1	-1/+4
2015-05-08	Switch erc32 simulator copyright headers to FSF.	Joel Brobecker	1	-20/+14
2015-04-24	Fix typos in sim sources exposed by static analysis.	Nick Clifton	1	-1/+1
2015-04-19	sim/erc32: Switched emulated memory to host endian order.	Jiri Gaisler	1	-9/+49
2015-03-28	sim: erc32: strip paren from return statements	Mike Frysinger	1	-15/+15
2015-03-16	sim/erc32: use SIM_AC_OPTION_HOSTENDIAN to probe for host endianess	Jiri Gaisler	1	-4/+3
2015-02-21	sim/erc32: Corrected wrong CPU implementation and version ID in psr	Jiri Gaisler	1	-1/+1
2014-01-07	remove PARAMS from sim	Tom Tromey	1	-8/+8
2012-12-19	[sim] Update old contact info in GPL license notices	Joel Brobecker	1	-2/+1
2012-12-19	Update sim copyright headers from GPLv2-or-later to GPLv3-or-later.	Joel Brobecker	1	-1/+1
2012-08-16	* end.c: Include config.h before system header files.	Nick Clifton	1	-0/+1
2008-11-11	2008-11-10 Joel Sherrill <joel.sherrill@oarcorp.com>	Joel Sherrill	1	-2/+2
2005-03-07	2005-03-07 Jerome Guitton <guitton@gnat.com>	Jerome Guitton	1	-0/+2
1999-04-16	Initial creation of sourceware repositorygdb-4_18-branchpoint	Stan Shebs	1	-0/+2041
1999-04-16	Initial creation of sourceware repository	Stan Shebs	1	-1597/+0
1996-05-20	New sparc simulator from the ESA.	Rob Savoye	1	-0/+1597