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path: root/sim/d10v/simops.c
AgeCommit message (Expand)AuthorFilesLines
2022-01-06sim: d10v: migrate to standard uintXX_t typesMike Frysinger1-198/+198
2021-11-28sim: d10v: switch to new target-newlib-syscallMike Frysinger1-32/+22
2021-06-18sim: split sim-signal.h include outMike Frysinger1-0/+1
2021-05-16sim: switch config.h usage to defs.hMike Frysinger1-1/+2
2021-01-11sim: clean up C11 header includesMike Frysinger1-2/+0
2015-11-15sim: d10v: drop global callback stateMike Frysinger1-73/+72
2015-11-15sim: d10v: convert to common sim engine logicMike Frysinger1-98/+45
2015-11-15sim: d10v: push down sd/cpu varsMike Frysinger1-401/+400
2015-03-30sim: d10v: convert to nrunMike Frysinger1-4/+11
2015-03-30sim: d10v: clean up misc warningsMike Frysinger1-175/+169
2014-01-07remove PARAMS from simTom Tromey1-4/+4
2003-10-31Index: sim/frv/ChangeLogAndrew Cagney1-1/+1
2002-11-14Index: common/ChangeLogAndrew Cagney1-0/+3
2002-05-282002-05-28 Elena Zannoni <ezannoni@redhat.com>Elena Zannoni1-4/+4
2000-02-09Report SIGBUS and halt simulation when ld/st detect a misaligned address.Andrew Cagney1-32/+44
2000-01-06import gdb-2000-01-05 snapshotJason Molenda1-26/+183
1999-12-07import gdb-1999-12-06 snapshotJason Molenda1-0/+22
1999-11-17import gdb-1999-11-16 snapshotJason Molenda1-8/+20
1999-11-02import gdb-1999-11-01 snapshotJason Molenda1-2/+2
1999-09-22import gdb-1999-09-21Jason Molenda1-7/+1
1999-09-13import gdb-1999-09-13 snapshotJason Molenda1-0/+175
1999-09-09import gdb-1999-09-08 snapshotStan Shebs1-2/+2
1999-04-26import gdb-19990422 snapshotStan Shebs1-2/+6
1999-04-16Initial creation of sourceware repositorygdb-4_18-branchpointStan Shebs1-0/+3252
1999-04-16Initial creation of sourceware repositoryStan Shebs1-3252/+0
1999-01-271999-01-26 Jason Molenda (jsm@bugshack.cygnus.com)Jason Molenda1-868/+1032
1998-02-13Implement separate user (SPU) and interrupt (SPI) stack pointers.Andrew Cagney1-0/+2
1998-02-11Don't abort() when system call is unknown.Andrew Cagney1-1/+1
1998-02-11Ensure zero-hardwired bits in DPSW remain zero.Andrew Cagney1-3/+35
1998-01-23First round of d10v ABI changesMichael Meissner1-68/+68
1997-12-08For "trap", IBT and RIE exceptions, mask all PSW.SM. NB: SteppingAndrew Cagney1-77/+79
1997-12-04Add DM (bit 4) to PSW. See 7-1 for more info.Andrew Cagney1-0/+2
1997-12-03* d10v_sim.h (SEXT56): Define.Andrew Cagney1-6/+10
1997-12-02For "msbu", subtract unsigned product from ACC,Andrew Cagney1-4/+8
1997-12-02For "mulxu", store unsigned product in ACC.Andrew Cagney1-3/+6
1997-12-02For MACU add unsigned multiply to accumulator.Andrew Cagney1-4/+8
1997-12-02For sub2w, compute carry according to negated addition rules.Andrew Cagney1-2/+3
1997-12-01Rework sim/common/sim-alu.h to differentiate between direcctAndrew Cagney1-11/+16
1997-10-13 * simops.c (OP_6A01): Change OP_POSTDEC to OP_POSTINC and moveFred Fish1-8/+8
1997-10-11 * simops.c (OP_6401): postdecrement on r15 is OK, remove exception.Fred Fish1-15/+3
1997-04-17Cleanups to compile under FreeBSDAndrew Cagney1-40/+24
1997-03-13Fix problems in setting the carry bitMichael Meissner1-31/+22
1997-03-13Fix os_printf_filtered; Flush stdout after calling printf_filteredMichael Meissner1-24/+58
1996-10-30Fix -t option to work with memory mapping; Print PC in some error messagesMichael Meissner1-22/+1
1996-10-29Tue Oct 29 12:13:52 1996 Martin M. Hunt <hunt@pizza.cygnus.com>Martin Hunt1-16/+54
1996-10-16Fix tracing of accumulatorsMichael Meissner1-2/+2
1996-10-15Better error messages when a program stops due to signal; support d10v getpid...Michael Meissner1-0/+145
1996-10-13Fix ld2w r2,@r2 so that r3 loads the proper valueMichael Meissner1-13/+93
1996-09-25Fix tracing for st2wMichael Meissner1-12/+41
1996-09-20Make sure cmp{,eq,u}i use correct castsMichael Meissner1-5/+5