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AgeCommit message (Expand)AuthorFilesLines
2016-01-04sim: parse_args: polish getopt error messageMike Frysinger2-1/+5
2016-01-04sim: punt x86-specific bswap logicMike Frysinger5-55/+12
2016-01-03sim: parse_args: display getopt error ourselvesMike Frysinger2-1/+33
2016-01-03sim: clean up some more device detritusMike Frysinger3-4/+5
2016-01-03sim: use libiberty countargv in more placesMike Frysinger2-2/+6
2016-01-03sim: nrun: use lbasenameMike Frysinger2-5/+9
2016-01-03sim: drop host endian configure optionMike Frysinger10-87/+295
2016-01-03sim: convert to bfd_endianMike Frysinger12-244/+125
2016-01-02sim: delete dead current_state globalsMike Frysinger4-32/+6
2016-01-01GDB copyright headers update after running GDB's copyright.py script.Joel Brobecker113-113/+113
2015-12-30sim: simplify STATE_MY_NAME setupMike Frysinger2-3/+6
2015-12-27sim: unify sim-hloadMike Frysinger2-0/+5
2015-12-26sim: punt WITH_DEVICES & tconfig.h supportMike Frysinger9-108/+22
2015-12-26sim: sim-core: pass down cpu to hw accesses when availableMike Frysinger2-10/+41
2015-12-25sim: hw-properties: delete trace callsMike Frysinger2-4/+8
2015-12-25sim: drop WITH_ENGINE defineMike Frysinger3-15/+5
2015-12-25sim: sim-model: build for everyoneMike Frysinger10-20/+42
2015-12-25sim: move MACH/MODEL types into SIM_xxx namespaceMike Frysinger4-27/+34
2015-12-25sim: device_error: puntMike Frysinger4-29/+16
2015-12-25sim: always enable callback memoryMike Frysinger4-13/+13
2015-12-25sim: dv-pal: always use CPU_INDEXMike Frysinger2-5/+7
2015-12-24sim: make LMA loading the default for all targetsMike Frysinger2-9/+7
2015-12-24sim: cris: move option install to sim_openMike Frysinger2-4/+4
2015-12-24sim: h8300: move h8300-specific options out of common codeMike Frysinger2-29/+7
2015-12-24sim: enable watchpoint module everywhereMike Frysinger2-2/+5
2015-12-24sim: delete SIM_HAVE_FLATMEM supportMike Frysinger4-51/+9
2015-12-24sim: delete SIM_HAVE_SIMCACHEMike Frysinger2-6/+4
2015-11-22sim: common: set up CPPFLAGS/CXXFLAGS/LDFLAGS from configure [PR sim/18762]Mike Frysinger2-0/+8
2015-11-22sim: sim_do_commandf: fix call to va_end [PR sim/19273]Mike Frysinger2-2/+13
2015-11-22sim: common: add PRI printf definesMike Frysinger2-0/+28
2015-11-17sim: always enable modulo memoryMike Frysinger4-29/+14
2015-11-17sim: sim-close: use XCONCAT2 helperMike Frysinger2-3/+6
2015-11-16sim: sim-stop/sim-reason/sim-reg: move to common obj listMike Frysinger2-0/+8
2015-11-15sim: sim-close: unify sim_close logicMike Frysinger3-0/+63
2015-09-25[PATCH] Add micromips support to the MIPS simulatorAndrew Bennett2-0/+10
2015-07-24Remove leading/trailing white spaces in ChangeLogH.J. Lu1-160/+160
2015-06-24sim: trace: drop unused trace_one_insnMike Frysinger3-98/+5
2015-06-24sim: trace: rename debug_printf fullyMike Frysinger3-5/+10
2015-06-24sim: trace: add a basic cpu register classMike Frysinger3-12/+44
2015-06-24sim: trace: add set of system helpersMike Frysinger2-0/+28
2015-06-24sim: trace: document alu/fpu/vpu trace options betterMike Frysinger3-7/+14
2015-06-23sim: common: replace SIM_FILTER_PATH with lbasenameMike Frysinger3-26/+16
2015-06-23sim: use AS_HELP_STRING everywhereMike Frysinger3-31/+81
2015-06-23sim: trace: do not enable internal debug by defaultMike Frysinger2-2/+6
2015-06-23sim: assume recentish compiler/systemsMike Frysinger3-26/+5
2015-06-21sim: common: add basic model assertMike Frysinger2-0/+5
2015-06-21sim: common: use standard intXX_t types for signedXXMike Frysinger2-82/+27
2015-06-21sim: common: standardize multiple include definesMike Frysinger6-13/+26
2015-06-18sim: syscall: simplify unknown syscall traceMike Frysinger2-5/+7
2015-06-18sim: callback: fix sentinel testing when walking mapsMike Frysinger2-2/+7
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