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AgeCommit message (Expand)AuthorFilesLines
2016-01-04sim: punt x86-specific bswap logicMike Frysinger2-21/+6
2016-01-03sim: parse_args: display getopt error ourselvesMike Frysinger2-3/+5
2016-01-03sim: TODO: move to wikiMike Frysinger2-54/+4
2016-01-03sim: use libiberty countargv in more placesMike Frysinger2-19/+11
2016-01-03sim: drop host endian configure optionMike Frysinger3-261/+232
2016-01-03sim: convert to bfd_endianMike Frysinger3-19/+25
2016-01-01GDB copyright headers update after running GDB's copyright.py script.Joel Brobecker75-75/+75
2015-12-27sim: unify sim-hloadMike Frysinger2-1/+4
2015-12-26sim: punt WITH_DEVICES & tconfig.h supportMike Frysinger3-6/+6
2015-12-26sim: bfin: push down mmr address/size checksMike Frysinger33-229/+549
2015-12-26sim: bfin: avoid stack error under asanMike Frysinger2-1/+5
2015-12-26sim: standardize sim_create_inferior handling of argv a bit moreMike Frysinger2-4/+9
2015-12-25sim: sim-model: build for everyoneMike Frysinger3-4/+5
2015-12-25sim: move MACH/MODEL types into SIM_xxx namespaceMike Frysinger2-7/+12
2015-12-25sim: device_error: puntMike Frysinger2-8/+4
2015-12-24sim: make LMA loading the default for all targetsMike Frysinger2-3/+4
2015-11-17sim: always enable modulo memoryMike Frysinger2-4/+4
2015-11-16sim: sim-stop/sim-reason/sim-reg: move to common obj listMike Frysinger2-4/+6
2015-11-15sim: sim-close: unify sim_close logicMike Frysinger2-6/+4
2015-10-11sim: bfin: handle negative left saturated shifts as ashifts [BZ #18407]Mike Frysinger2-1/+11
2015-06-24sim: trace: add a basic cpu register classMike Frysinger3-28/+5
2015-06-23sim: use AS_HELP_STRING everywhereMike Frysinger2-14/+30
2015-06-17sim: syscall: unify memory helpersMike Frysinger2-28/+10
2015-06-17sim: callback: add human readable strings for debugging to mapsMike Frysinger2-496/+503
2015-06-12sim: bfin: expand CB_SYS_xxx commentMike Frysinger2-1/+7
2015-06-12sim: update configure.in->configure.ac docsMike Frysinger2-1/+5
2015-06-12sim: drop -DTRACE from configureMike Frysinger2-3/+7
2015-06-12sim: trace: add common macros for logging infoMike Frysinger6-37/+46
2015-04-24Fix typos in sim sources exposed by static analysis.Nick Clifton2-1/+8
2015-04-18sim: unify SIM_CPU definitionMike Frysinger2-0/+6
2015-04-18sim: unify sim_cia definitionMike Frysinger2-2/+4
2015-04-17sim: replace CIA_{GET,SET} with CPU_PC_{GET,SET}Mike Frysinger2-3/+4
2015-04-15sim: unify sim-cpu usageMike Frysinger3-6/+6
2015-04-13sim: fix the PKGVERSION defineMike Frysinger2-2/+6
2015-04-06sim: move sim-engine.o/sim-hrw.o to the common listMike Frysinger2-2/+4
2015-04-02Regenerate configure in simH.J. Lu1-2/+2
2015-04-02sim: clean up SIM_EXTRA_OBJS referencesMike Frysinger2-2/+5
2015-04-01Regenerate configure in simH.J. Lu1-4/+6
2015-04-01sim: update zlib handlingMike Frysinger3-84/+17
2015-03-24sim: fix sim-hardware configure optionMike Frysinger2-6/+6
2015-03-23sim: drop support for requiring hw supportMike Frysinger2-10/+9
2015-03-23sim: dv-sockser: move build to common dirMike Frysinger4-15/+12
2015-03-23sim: dv-sockser: add stub funcs when not availableMike Frysinger2-6/+5
2015-03-23sim: bfin/msp430: drop run-sim.h includeMike Frysinger2-1/+4
2015-03-16sim: rename tconfig.in to tconfig.hMike Frysinger5-21/+22
2015-03-15sim: dv-sockser: push module init prototype downMike Frysinger2-12/+5
2015-03-14sim: bfin: fix signed warningMike Frysinger2-1/+5
2015-03-14sim: make nrun the default run programMike Frysinger2-3/+4
2015-03-10sim: bfin: fix up linux-fixed-code.h generation more [PR sim/13160]Mike Frysinger2-1/+7
2015-03-09sim: bfin: fix bug referenceMike Frysinger1-1/+1
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