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AgeCommit message (Expand)AuthorFilesLines
2011-06-04sim: bfin: add support for glued SIC interrupt linesMike Frysinger2-25/+71
2011-06-04sim: bfin: push SIC mappings to device treeMike Frysinger3-589/+723
2011-06-03sim: bfin: dma: fix indentationMike Frysinger2-1/+5
2011-05-26sim: bfin: switch to new syscall trace levelMike Frysinger2-1/+5
2011-05-25sim: bfin: move model data into machs.hMike Frysinger31-109/+80
2011-05-25sim: bfin: add a performance monitor stubMike Frysinger7-0/+196
2011-05-25sim: bfin: add bf526-0.2/bf54x-0.4 rom regionsMike Frysinger6-0/+27
2011-05-14sim: bfin: allow pushing of SPMike Frysinger2-2/+6
2011-05-14sim: bfin: implement loop back support in the UARTsMike Frysinger4-23/+62
2011-05-09sim: bfin: fix UART LSR read-only bit saturationMike Frysinger2-0/+6
2011-04-27sim: bfin: constify dmac pmap arraysMike Frysinger2-13/+22
2011-04-26sim: gpio: add output supportMike Frysinger2-16/+53
2011-04-26sim: gpio: update mask a/b signals betterMike Frysinger2-12/+49
2011-04-16sim: bfin: use store buffer with more 32bit insnsMike Frysinger2-23/+37
2011-04-15sim: bfin: handle implicit DISALGNEXCPT with video insnsMike Frysinger2-0/+30
2011-04-11sim: bfin: respect the port level on signals to the SICMike Frysinger2-16/+32
2011-04-11sim: bfin: add missing GPIO pin 15Mike Frysinger2-0/+5
2011-04-01sim: bfin: add OTP output portMike Frysinger2-0/+12
2011-03-29sim: bfin: regen configure to include new cfi deviceMike Frysinger2-1/+5
2011-03-29sim: bfin: fix sign extension with 16bit acc add insnsMike Frysinger2-9/+9
2011-03-27sim: bfin: handle saturation with RND12 sub insnsMike Frysinger2-1/+11
2011-03-26sim: bfin: add missing VS set with add/sub insnsMike Frysinger2-0/+7
2011-03-25sim: bfin: add hw tracing to gpio/sic port eventsMike Frysinger3-10/+64
2011-03-25sim: bfin: fix GPIO logic bugs when processing eventsMike Frysinger2-4/+16
2011-03-25sim: bfin: fix clear/set/toggle GPIO handlingMike Frysinger2-0/+11
2011-03-24sim: bfin: document SIC limitationMike Frysinger2-1/+27
2011-03-24sim: bfin: fix inverted W1C logicMike Frysinger14-17/+34
2011-03-24sim: bfin: define more UART LSR bitsMike Frysinger2-7/+16
2011-03-24sim: bfin: fix typo in TWI stat regMike Frysinger2-1/+5
2011-03-24sim: bfin: update VIT_MAX behavior to match hardware when Acc.X bits are setMike Frysinger2-2/+7
2011-03-24sim: bfin: always do 16bit sign extension with the SEARCH insnMike Frysinger2-0/+10
2011-03-24sim: bfin: update AV and AC ASTAT bits with acc negationMike Frysinger2-6/+14
2011-03-24sim: bfin: fix thinko in SIC pin encodingMike Frysinger2-511/+516
2011-03-24sim: bfin: allow byteop[123]p src regs to be the sameMike Frysinger2-9/+5
2011-03-24sim: bfin: fix thinko in bfin_gpio bus addressesMike Frysinger2-30/+38
2011-03-17sim: bfin: check for kill/preadMike Frysinger5-2/+25
2011-03-15sim: bfin: add GPIO device simulationMike Frysinger7-28/+369
2011-03-15sim: bfin: fix brace styleMike Frysinger27-27/+54
2011-03-15sim: bfin: fix brace styleMike Frysinger58-161/+342
2011-03-15sim: bfin: handle AZ updates with 16bit adds/subsMike Frysinger2-1/+6
2011-03-15sim: bfin: skip acc/ASTAT updates for movesMike Frysinger2-6/+10
2011-03-15sim: bfin: handle AN (negative overflows) in dsp mult insnsMike Frysinger2-8/+40
2011-03-15sim: bfin: handle V overflows in dsp mult insnsMike Frysinger2-7/+15
2011-03-15sim: bfin: decode ASTAT on failureMike Frysinger2-34/+79
2011-03-15sim: bfin: handle saturation with fract multiplicationsMike Frysinger2-0/+6
2011-03-14sim: bfin: forgot to cvs add the changelogMike Frysinger1-0/+29
2011-03-06sim: bfin: new portMike Frysinger101-0/+30214
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