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AgeCommit message (Expand)AuthorFilesLines
2012-11-20Fix sim build when configured with --enable-pluginsH.J. Lu1-1/+8960
2012-08-01sim: bfin: set bfrom alias field to correct sizeMike Frysinger2-10/+17
2012-08-01sim: bfin: update return value in bfin_reg_{fetch,store}Mike Frysinger2-4/+10
2012-06-15Define PACKAGE macro in all sims' config.h.Joel Brobecker3-0/+19
2012-04-09sim: bfin: new PINT modelMike Frysinger7-1/+386
2012-04-09sim: bfin: new GPIO modelMike Frysinger7-1/+352
2012-04-09sim: bfin: fix ASTAT issues in immediate shiftsMike Frysinger2-17/+64
2012-04-09sim: bfin: fix ASTAT/correctness issues with arithmetic shiftsMike Frysinger2-10/+67
2012-04-09sim: bfin: more parallel insn checksMike Frysinger2-18/+84
2012-04-09sim: bfin: keep track of the exact position of parallel insnsMike Frysinger3-44/+75
2012-04-08sim: bfin: drop excess space in negation insnMike Frysinger2-1/+5
2012-04-01sim: bfin: throw VEC_ILGAL_I with 32bit insn in group1/group2 slotsMike Frysinger2-0/+8
2012-04-01sim: bfin: simplify field width processing and fix build warningsMike Frysinger2-10/+6
2012-04-01sim: bfin: fix unused bfrom handling for BF535Mike Frysinger2-1/+5
2012-04-01sim: bfin: fix build warning/style with auxvt_sizeMike Frysinger2-2/+7
2012-03-31sim: bfin: fix typo in BF54x SIC initMike Frysinger2-1/+5
2012-03-31sim: bfin: include devices.h to fix build warningsMike Frysinger2-0/+5
2012-03-24[PATCH] sim: make sure to include strsignal prototypeMike Frysinger4-150/+267
2012-03-19sim: bfin: fix corner case Logical shift issuesMike Frysinger2-45/+64
2012-03-19sim: bfin: ebiu_amc: push down hardcoded base addressesMike Frysinger2-2/+12
2012-03-19sim: bfin: use ARRAY_SIZEMike Frysinger2-1/+6
2012-03-04sim: bfin: drop old linux/mii.h workaroundsMike Frysinger5-23/+35
2012-01-04Copyright year update in most files of the GDB Project.Joel Brobecker71-71/+71
2011-12-03sim: bfin: lookup target strings when tracing system callsMike Frysinger2-10/+41
2011-12-03sim: generate build dependencies on the flyMike Frysinger4-34/+306
2011-10-19sim: dv-cfi: check for log2 support in libm when enabledMike Frysinger2-0/+52
2011-10-18sim: rename common/aclocal.m4 to common/acinclude.m4Mike Frysinger4-8/+18
2011-10-18sim: move from common.m4 to SIM_AC_COMMONMike Frysinger3-364/+353
2011-09-29sim: bfin: use store buffer for VIT_MAX insnsMike Frysinger2-2/+6
2011-07-05sim: start a unified sim_do_commandMike Frysinger2-7/+4
2011-07-01sim: bfin: implement stat_map for virtual environments (libgloss)Mike Frysinger2-4/+30
2011-06-22sim: bfin: pass up result2/errcode with libgloss syscallsMike Frysinger2-2/+7
2011-06-18sim: bfin: set ASTAT AV/AVS when shifting accumulators overflowMike Frysinger2-0/+12
2011-06-18sim: bfin: do not touch ASTAT[V] when shifting accumulatorsMike Frysinger2-3/+9
2011-06-18sim: bfin: do not extend accumulator in LSHIFT insnsMike Frysinger2-1/+6
2011-06-18sim: bfin: tweak saturation handling with TFU/FU modes and MM bitMike Frysinger2-14/+35
2011-06-18sim: bfin: handle large shift values with accumulator shift insnsMike Frysinger2-2/+14
2011-06-18sim: bfin: handle odd shift values with shift insnsMike Frysinger2-7/+36
2011-06-18sim: bfin: fix M_IH saturation sizeMike Frysinger2-17/+6
2011-06-18sim: bfin: handle V/VS saturation in dsp mac insnsMike Frysinger2-25/+58
2011-06-18sim: bfin: handle the MM flag in M_IU/M_TFU modes with dsp insnsMike Frysinger2-0/+10
2011-06-18sim: bfin: fix sign extension in dsp insns with MM flagMike Frysinger2-8/+10
2011-06-18sim: bfin: fix dsp insns IH saturation/rounding behaviorMike Frysinger2-1/+16
2011-06-18sim: bfin: fix inverted changelog entryMike Frysinger1-1/+1
2011-06-18sim: bfin: fix accumulator edge case saturationMike Frysinger2-2/+7
2011-06-18sim: bfin: use freeargv for freeing argvsMike Frysinger2-1/+5
2011-06-04sim: bfin: add support for glued SIC interrupt linesMike Frysinger2-25/+71
2011-06-04sim: bfin: push SIC mappings to device treeMike Frysinger3-589/+723
2011-06-03sim: bfin: dma: fix indentationMike Frysinger2-1/+5
2011-05-26sim: bfin: switch to new syscall trace levelMike Frysinger2-1/+5
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