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AgeCommit message (Expand)AuthorFilesLines
2011-03-24sim: bfin: fix inverted W1C logicMike Frysinger14-17/+34
2011-03-24sim: bfin: define more UART LSR bitsMike Frysinger2-7/+16
2011-03-24sim: bfin: fix typo in TWI stat regMike Frysinger2-1/+5
2011-03-24sim: bfin: update VIT_MAX behavior to match hardware when Acc.X bits are setMike Frysinger2-2/+7
2011-03-24sim: bfin: always do 16bit sign extension with the SEARCH insnMike Frysinger2-0/+10
2011-03-24sim: bfin: update AV and AC ASTAT bits with acc negationMike Frysinger2-6/+14
2011-03-24sim: bfin: fix thinko in SIC pin encodingMike Frysinger2-511/+516
2011-03-24sim: bfin: allow byteop[123]p src regs to be the sameMike Frysinger2-9/+5
2011-03-24sim: bfin: fix thinko in bfin_gpio bus addressesMike Frysinger2-30/+38
2011-03-17sim: bfin: check for kill/preadMike Frysinger5-2/+25
2011-03-15sim: bfin: add GPIO device simulationMike Frysinger7-28/+369
2011-03-15sim: bfin: fix brace styleMike Frysinger27-27/+54
2011-03-15sim: bfin: fix brace styleMike Frysinger58-161/+342
2011-03-15sim: bfin: handle AZ updates with 16bit adds/subsMike Frysinger2-1/+6
2011-03-15sim: bfin: skip acc/ASTAT updates for movesMike Frysinger2-6/+10
2011-03-15sim: bfin: handle AN (negative overflows) in dsp mult insnsMike Frysinger2-8/+40
2011-03-15sim: bfin: handle V overflows in dsp mult insnsMike Frysinger2-7/+15
2011-03-15sim: bfin: decode ASTAT on failureMike Frysinger2-34/+79
2011-03-15sim: bfin: handle saturation with fract multiplicationsMike Frysinger2-0/+6
2011-03-14sim: bfin: forgot to cvs add the changelogMike Frysinger1-0/+29
2011-03-06sim: bfin: new portMike Frysinger101-0/+30214
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