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path: root/sim/bfin/bfin-sim.c
AgeCommit message (Expand)AuthorFilesLines
2011-09-29sim: bfin: use store buffer for VIT_MAX insnsMike Frysinger1-2/+2
2011-06-18sim: bfin: set ASTAT AV/AVS when shifting accumulators overflowMike Frysinger1-0/+6
2011-06-18sim: bfin: do not touch ASTAT[V] when shifting accumulatorsMike Frysinger1-3/+4
2011-06-18sim: bfin: do not extend accumulator in LSHIFT insnsMike Frysinger1-1/+1
2011-06-18sim: bfin: tweak saturation handling with TFU/FU modes and MM bitMike Frysinger1-14/+30
2011-06-18sim: bfin: handle large shift values with accumulator shift insnsMike Frysinger1-2/+8
2011-06-18sim: bfin: handle odd shift values with shift insnsMike Frysinger1-7/+29
2011-06-18sim: bfin: fix M_IH saturation sizeMike Frysinger1-12/+1
2011-06-18sim: bfin: handle V/VS saturation in dsp mac insnsMike Frysinger1-25/+48
2011-06-18sim: bfin: handle the MM flag in M_IU/M_TFU modes with dsp insnsMike Frysinger1-0/+4
2011-06-18sim: bfin: fix sign extension in dsp insns with MM flagMike Frysinger1-8/+3
2011-06-18sim: bfin: fix dsp insns IH saturation/rounding behaviorMike Frysinger1-1/+11
2011-06-18sim: bfin: fix accumulator edge case saturationMike Frysinger1-2/+2
2011-05-14sim: bfin: allow pushing of SPMike Frysinger1-2/+1
2011-04-16sim: bfin: use store buffer with more 32bit insnsMike Frysinger1-23/+29
2011-04-15sim: bfin: handle implicit DISALGNEXCPT with video insnsMike Frysinger1-0/+24
2011-03-29sim: bfin: fix sign extension with 16bit acc add insnsMike Frysinger1-9/+2
2011-03-27sim: bfin: handle saturation with RND12 sub insnsMike Frysinger1-1/+6
2011-03-26sim: bfin: add missing VS set with add/sub insnsMike Frysinger1-0/+3
2011-03-24sim: bfin: update VIT_MAX behavior to match hardware when Acc.X bits are setMike Frysinger1-2/+2
2011-03-24sim: bfin: always do 16bit sign extension with the SEARCH insnMike Frysinger1-0/+5
2011-03-24sim: bfin: update AV and AC ASTAT bits with acc negationMike Frysinger1-6/+8
2011-03-24sim: bfin: allow byteop[123]p src regs to be the sameMike Frysinger1-9/+0
2011-03-15sim: bfin: handle AZ updates with 16bit adds/subsMike Frysinger1-1/+1
2011-03-15sim: bfin: skip acc/ASTAT updates for movesMike Frysinger1-6/+6
2011-03-15sim: bfin: handle AN (negative overflows) in dsp mult insnsMike Frysinger1-8/+33
2011-03-15sim: bfin: handle V overflows in dsp mult insnsMike Frysinger1-7/+9
2011-03-15sim: bfin: decode ASTAT on failureMike Frysinger1-34/+72
2011-03-15sim: bfin: handle saturation with fract multiplicationsMike Frysinger1-0/+2
2011-03-06sim: bfin: new portMike Frysinger1-0/+6099
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