| Age | Commit message (Expand) | Author | Files | Lines |
|---|
| 2011-09-29 | sim: bfin: use store buffer for VIT_MAX insns | Mike Frysinger | 1 | -2/+2 |
| 2011-06-18 | sim: bfin: set ASTAT AV/AVS when shifting accumulators overflow | Mike Frysinger | 1 | -0/+6 |
| 2011-06-18 | sim: bfin: do not touch ASTAT[V] when shifting accumulators | Mike Frysinger | 1 | -3/+4 |
| 2011-06-18 | sim: bfin: do not extend accumulator in LSHIFT insns | Mike Frysinger | 1 | -1/+1 |
| 2011-06-18 | sim: bfin: tweak saturation handling with TFU/FU modes and MM bit | Mike Frysinger | 1 | -14/+30 |
| 2011-06-18 | sim: bfin: handle large shift values with accumulator shift insns | Mike Frysinger | 1 | -2/+8 |
| 2011-06-18 | sim: bfin: handle odd shift values with shift insns | Mike Frysinger | 1 | -7/+29 |
| 2011-06-18 | sim: bfin: fix M_IH saturation size | Mike Frysinger | 1 | -12/+1 |
| 2011-06-18 | sim: bfin: handle V/VS saturation in dsp mac insns | Mike Frysinger | 1 | -25/+48 |
| 2011-06-18 | sim: bfin: handle the MM flag in M_IU/M_TFU modes with dsp insns | Mike Frysinger | 1 | -0/+4 |
| 2011-06-18 | sim: bfin: fix sign extension in dsp insns with MM flag | Mike Frysinger | 1 | -8/+3 |
| 2011-06-18 | sim: bfin: fix dsp insns IH saturation/rounding behavior | Mike Frysinger | 1 | -1/+11 |
| 2011-06-18 | sim: bfin: fix accumulator edge case saturation | Mike Frysinger | 1 | -2/+2 |
| 2011-05-14 | sim: bfin: allow pushing of SP | Mike Frysinger | 1 | -2/+1 |
| 2011-04-16 | sim: bfin: use store buffer with more 32bit insns | Mike Frysinger | 1 | -23/+29 |
| 2011-04-15 | sim: bfin: handle implicit DISALGNEXCPT with video insns | Mike Frysinger | 1 | -0/+24 |
| 2011-03-29 | sim: bfin: fix sign extension with 16bit acc add insns | Mike Frysinger | 1 | -9/+2 |
| 2011-03-27 | sim: bfin: handle saturation with RND12 sub insns | Mike Frysinger | 1 | -1/+6 |
| 2011-03-26 | sim: bfin: add missing VS set with add/sub insns | Mike Frysinger | 1 | -0/+3 |
| 2011-03-24 | sim: bfin: update VIT_MAX behavior to match hardware when Acc.X bits are set | Mike Frysinger | 1 | -2/+2 |
| 2011-03-24 | sim: bfin: always do 16bit sign extension with the SEARCH insn | Mike Frysinger | 1 | -0/+5 |
| 2011-03-24 | sim: bfin: update AV and AC ASTAT bits with acc negation | Mike Frysinger | 1 | -6/+8 |
| 2011-03-24 | sim: bfin: allow byteop[123]p src regs to be the same | Mike Frysinger | 1 | -9/+0 |
| 2011-03-15 | sim: bfin: handle AZ updates with 16bit adds/subs | Mike Frysinger | 1 | -1/+1 |
| 2011-03-15 | sim: bfin: skip acc/ASTAT updates for moves | Mike Frysinger | 1 | -6/+6 |
| 2011-03-15 | sim: bfin: handle AN (negative overflows) in dsp mult insns | Mike Frysinger | 1 | -8/+33 |
| 2011-03-15 | sim: bfin: handle V overflows in dsp mult insns | Mike Frysinger | 1 | -7/+9 |
| 2011-03-15 | sim: bfin: decode ASTAT on failure | Mike Frysinger | 1 | -34/+72 |
| 2011-03-15 | sim: bfin: handle saturation with fract multiplications | Mike Frysinger | 1 | -0/+2 |
| 2011-03-06 | sim: bfin: new port | Mike Frysinger | 1 | -0/+6099 |
