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AgeCommit message (Expand)AuthorFilesLines
2012-04-09sim: bfin: new PINT modelMike Frysinger1-0/+11
2012-04-09sim: bfin: new GPIO modelMike Frysinger1-0/+10
2012-04-09sim: bfin: fix ASTAT issues in immediate shiftsMike Frysinger1-0/+6
2012-04-09sim: bfin: fix ASTAT/correctness issues with arithmetic shiftsMike Frysinger1-0/+7
2012-04-09sim: bfin: more parallel insn checksMike Frysinger1-0/+18
2012-04-09sim: bfin: keep track of the exact position of parallel insnsMike Frysinger1-0/+14
2012-04-08sim: bfin: drop excess space in negation insnMike Frysinger1-0/+4
2012-04-01sim: bfin: throw VEC_ILGAL_I with 32bit insn in group1/group2 slotsMike Frysinger1-0/+5
2012-04-01sim: bfin: simplify field width processing and fix build warningsMike Frysinger1-0/+5
2012-04-01sim: bfin: fix unused bfrom handling for BF535Mike Frysinger1-0/+4
2012-04-01sim: bfin: fix build warning/style with auxvt_sizeMike Frysinger1-0/+5
2012-03-31sim: bfin: fix typo in BF54x SIC initMike Frysinger1-0/+4
2012-03-31sim: bfin: include devices.h to fix build warningsMike Frysinger1-0/+4
2012-03-24[PATCH] sim: make sure to include strsignal prototypeMike Frysinger1-0/+4
2012-03-19sim: bfin: fix corner case Logical shift issuesMike Frysinger1-0/+11
2012-03-19sim: bfin: ebiu_amc: push down hardcoded base addressesMike Frysinger1-0/+7
2012-03-19sim: bfin: use ARRAY_SIZEMike Frysinger1-0/+5
2012-03-04sim: bfin: drop old linux/mii.h workaroundsMike Frysinger1-0/+8
2011-12-03sim: bfin: lookup target strings when tracing system callsMike Frysinger1-0/+8
2011-12-03sim: generate build dependencies on the flyMike Frysinger1-0/+5
2011-10-19sim: dv-cfi: check for log2 support in libm when enabledMike Frysinger1-0/+4
2011-10-18sim: rename common/aclocal.m4 to common/acinclude.m4Mike Frysinger1-0/+5
2011-10-18sim: move from common.m4 to SIM_AC_COMMONMike Frysinger1-0/+6
2011-09-29sim: bfin: use store buffer for VIT_MAX insnsMike Frysinger1-0/+4
2011-07-05sim: start a unified sim_do_commandMike Frysinger1-0/+4
2011-07-01sim: bfin: implement stat_map for virtual environments (libgloss)Mike Frysinger1-0/+11
2011-06-22sim: bfin: pass up result2/errcode with libgloss syscallsMike Frysinger1-0/+5
2011-06-18sim: bfin: set ASTAT AV/AVS when shifting accumulators overflowMike Frysinger1-0/+6
2011-06-18sim: bfin: do not touch ASTAT[V] when shifting accumulatorsMike Frysinger1-0/+5
2011-06-18sim: bfin: do not extend accumulator in LSHIFT insnsMike Frysinger1-0/+5
2011-06-18sim: bfin: tweak saturation handling with TFU/FU modes and MM bitMike Frysinger1-0/+5
2011-06-18sim: bfin: handle large shift values with accumulator shift insnsMike Frysinger1-0/+6
2011-06-18sim: bfin: handle odd shift values with shift insnsMike Frysinger1-0/+7
2011-06-18sim: bfin: fix M_IH saturation sizeMike Frysinger1-5/+5
2011-06-18sim: bfin: handle V/VS saturation in dsp mac insnsMike Frysinger1-0/+10
2011-06-18sim: bfin: handle the MM flag in M_IU/M_TFU modes with dsp insnsMike Frysinger1-0/+6
2011-06-18sim: bfin: fix sign extension in dsp insns with MM flagMike Frysinger1-0/+7
2011-06-18sim: bfin: fix dsp insns IH saturation/rounding behaviorMike Frysinger1-0/+5
2011-06-18sim: bfin: fix inverted changelog entryMike Frysinger1-1/+1
2011-06-18sim: bfin: fix accumulator edge case saturationMike Frysinger1-0/+5
2011-06-18sim: bfin: use freeargv for freeing argvsMike Frysinger1-0/+4
2011-06-04sim: bfin: add support for glued SIC interrupt linesMike Frysinger1-0/+9
2011-06-04sim: bfin: push SIC mappings to device treeMike Frysinger1-0/+33
2011-06-03sim: bfin: dma: fix indentationMike Frysinger1-0/+4
2011-05-26sim: bfin: switch to new syscall trace levelMike Frysinger1-0/+4
2011-05-25sim: bfin: move model data into machs.hMike Frysinger1-0/+33
2011-05-25sim: bfin: add a performance monitor stubMike Frysinger1-0/+9
2011-05-25sim: bfin: add bf526-0.2/bf54x-0.4 rom regionsMike Frysinger1-0/+9
2011-05-14sim: bfin: allow pushing of SPMike Frysinger1-0/+5
2011-05-14sim: bfin: implement loop back support in the UARTsMike Frysinger1-0/+15
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