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AgeCommit message (Expand)AuthorFilesLines
2011-04-15sim: bfin: handle implicit DISALGNEXCPT with video insnsMike Frysinger1-0/+6
2011-04-11sim: bfin: respect the port level on signals to the SICMike Frysinger1-0/+7
2011-04-11sim: bfin: add missing GPIO pin 15Mike Frysinger1-0/+4
2011-04-01sim: bfin: add OTP output portMike Frysinger1-0/+5
2011-03-29sim: bfin: regen configure to include new cfi deviceMike Frysinger1-0/+4
2011-03-29sim: bfin: fix sign extension with 16bit acc add insnsMike Frysinger1-0/+7
2011-03-27sim: bfin: handle saturation with RND12 sub insnsMike Frysinger1-0/+5
2011-03-26sim: bfin: add missing VS set with add/sub insnsMike Frysinger1-0/+4
2011-03-25sim: bfin: add hw tracing to gpio/sic port eventsMike Frysinger1-0/+10
2011-03-25sim: bfin: fix GPIO logic bugs when processing eventsMike Frysinger1-0/+6
2011-03-25sim: bfin: fix clear/set/toggle GPIO handlingMike Frysinger1-0/+5
2011-03-24sim: bfin: document SIC limitationMike Frysinger1-0/+4
2011-03-24sim: bfin: fix inverted W1C logicMike Frysinger1-0/+17
2011-03-24sim: bfin: define more UART LSR bitsMike Frysinger1-0/+4
2011-03-24sim: bfin: fix typo in TWI stat regMike Frysinger1-0/+4
2011-03-24sim: bfin: update VIT_MAX behavior to match hardware when Acc.X bits are setMike Frysinger1-0/+5
2011-03-24sim: bfin: always do 16bit sign extension with the SEARCH insnMike Frysinger1-0/+5
2011-03-24sim: bfin: update AV and AC ASTAT bits with acc negationMike Frysinger1-0/+6
2011-03-24sim: bfin: fix thinko in SIC pin encodingMike Frysinger1-0/+14
2011-03-24sim: bfin: allow byteop[123]p src regs to be the sameMike Frysinger1-0/+5
2011-03-24sim: bfin: fix thinko in bfin_gpio bus addressesMike Frysinger1-0/+7
2011-03-17sim: bfin: check for kill/preadMike Frysinger1-0/+8
2011-03-15sim: bfin: add GPIO device simulationMike Frysinger1-0/+15
2011-03-15sim: bfin: fix brace styleMike Frysinger1-0/+20
2011-03-15sim: bfin: handle AZ updates with 16bit adds/subsMike Frysinger1-0/+5
2011-03-15sim: bfin: skip acc/ASTAT updates for movesMike Frysinger1-0/+4
2011-03-15sim: bfin: handle AN (negative overflows) in dsp mult insnsMike Frysinger1-0/+7
2011-03-15sim: bfin: handle V overflows in dsp mult insnsMike Frysinger1-0/+6
2011-03-15sim: bfin: decode ASTAT on failureMike Frysinger1-0/+7
2011-03-15sim: bfin: handle saturation with fract multiplicationsMike Frysinger1-0/+4
2011-03-14sim: bfin: forgot to cvs add the changelogMike Frysinger1-0/+29
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