riscv-gnu-toolchain/gdb.git - Unnamed repository; edit this file 'description' to name the repository.

Age	Commit message (Collapse)	Author	Files	Lines
2012-12-19	[sim] Update old contact info in GPL license notices	Joel Brobecker	1	-2/+1
	sim/ChangeLog: Update old contact info in GPL license notices.
2012-12-19	Update sim copyright headers from GPLv2-or-later to GPLv3-or-later.	Joel Brobecker	1	-1/+1
	gdb/sim/ChangeLog: Update the non-FSF-copyrighted files in sim to GPLv3 or later.
2008-11-26	2008-11-24 Joel Sherrill <joel.sherrill@oarcorp.com>	Joel Sherrill	1	-0/+2
	* arminit.c, iwmmxt.c: Include <string.h> to eliminate warning.
2005-05-12	Update the address of the FSF organization	Nick Clifton	1	-1/+1

2005-04-25	* armemu.c (handle_v6_insn): New function - emulate a few of the v6 ↵	Nick Clifton	1	-0/+2
	instructions - the ones now generated by GCC. (ARMulEmulate32): Call handle_v6_insn when a possible v6 insn is found. * armdefs.h (struct ARMul_State): Add new field: is_v6.# (ARM_v6_Prop): Define. * arminit.c (ARMul_NewState): Initialise the v6 flag. (ARMul_SelectProcessor): Determine if the v6 flag should be set. * wrapper.c (sim_create_inferior): For unknown architectures, default to allowing the v6 instructions.
2003-03-27	Add iWMMXt support to ARM simulator	Nick Clifton	1	-0/+23

2003-03-20	Add Cirrus Maverick support to arm simulator	Nick Clifton	1	-0/+5

2002-01-10	Fix parameters passed to CPRead[13] and CPRead[14].	Nick Clifton	1	-4/+6

2001-04-18	* XScale coprocessor support.	Matthew Green	1	-2/+9
	2001-04-18 matthew green <mrg@redhat.com> * armcopro.c (write_cp15_reg): Set CHANGEMODE if endianness changes. (read_cp15_reg): Make non-static. (XScale_cp15_LDC): Update for write_cp15_reg() change. (XScale_cp15_MCR): Likewise. (XScale_cp15_write_reg): Likewise. (XScale_check_memacc): New function. Check for breakpoints being activated by memory accesses. Does not support the Branch Target Buffer. (XScale_set_fsr_far): New function. Set FSR and FAR for XScale. (XScale_debug_moe): New function. Set the debug Method Of Entry, if configured. (write_cp14_reg): Reset count counter if requested. * armdefs.h (struct ARMul_State): New members `LastTime' and `CP14R0_CCD' used for the timer/counters. (ARMul_CP13_R0_FIQ, ARMul_CP13_R0_IRQ, ARMul_CP13_R8_PMUS, ARMul_CP14_R0_ENABLE, ARMul_CP14_R0_CLKRST, ARMul_CP14_R0_CCD, ARMul_CP14_R0_INTEN0, ARMul_CP14_R0_INTEN1, ARMul_CP14_R0_INTEN2, ARMul_CP14_R0_FLAG0, ARMul_CP14_R0_FLAG1, ARMul_CP14_R0_FLAG2, ARMul_CP14_R10_MOE_IB, ARMul_CP14_R10_MOE_DB, ARMul_CP14_R10_MOE_BT, ARMul_CP15_R1_ENDIAN, ARMul_CP15_R1_ALIGN, ARMul_CP15_R5_X, ARMul_CP15_R5_ST_ALIGN, ARMul_CP15_R5_IMPRE, ARMul_CP15_R5_MMU_EXCPT, ARMul_CP15_DBCON_M, ARMul_CP15_DBCON_E1, ARMul_CP15_DBCON_E0): New defines for XScale registers. (XScale_check_memacc, XScale_set_fsr_far, XScale_debug_moe): Prototype. (ARMul_Emulate32, ARMul_Emulate26): Clean up function definition. (ARMul_Emulate32): Handle the clock counter and hardware instruction breakpoints. Call XScale_set_fsr_far() for software breakpoints and software interrupts. (LoadMult): Call XScale_set_fsr_far() for data aborts. (LoadSMult): Likewise. (StoreMult): Likewise. (StoreSMult): Likewise. * armemu.h (write_cp15_reg): Update prototype. * arminit.c (ARMul_NewState): Initialise CP14R0_CCD and LastTime. (ARMul_Abort): If XScale, check for FIQ and IRQ being enabled in CP13 register 0. * armvirt.c (GetWord): Call XScale_check_memacc(). (PutWord): Likewise.
2000-11-30	Add support for ARM's v5TE architecture and Intel's XScale extenstions	Nick Clifton	1	-10/+12

2000-09-15	Replace StrongARM property with v4 and v5 properties.	Nick Clifton	1	-7/+10

2000-07-04	* armdefs.h (struct ARMul_State): Add is_StrongARM.	Alexandre Oliva	1	-0/+4
	(ARM_Strong_Prop, STRONGARM): Define. * arminit.c (ARMul_NewState): Reset is_StrongARM. (ARMul_SelectProcessor): Set is_StrongARM. * wrapper.c (sim_create_inferior): Use bfd machine type to determine processor type to emulate. * armemu.h (BUSUSEDINCPCS, BUSUSEDINCPCN): Don't increment PC when emulating StrongARM.
2000-07-04	* armemu.h (INSN_SIZE): New macro.	Alexandre Oliva	1	-32/+9
	(SET_ABORT): Save CPSR in SPSR and set LR. * armemu.c (ARMul_Emulate, isize): Set to INSN_SIZE. (WriteR15, WriteSR15): Do not discard bit 1 in Thumb mode. * arminit.c (ARMul_Abort): Use new SETABORT and INSN_SIZE.
2000-05-30	Add support for v4 SystemMode.	Nick Clifton	1	-1/+7

2000-02-05	import gdb-2000-02-04 snapshot	Jason Molenda	1	-202/+228

1999-04-16	Initial creation of sourceware repositorygdb-4_18-branchpoint	Stan Shebs	1	-0/+294