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AgeCommit message (Expand)AuthorFilesLines
2003-04-13Only call XScale_check_memacc if in XScale mode.Nick Clifton1-0/+6
2003-03-30Remove use of __IWMMXT__.Nick Clifton1-1/+15
2003-03-27Add iWMMXt support to ARM simulatorNick Clifton1-0/+25
2003-03-20fix date on latest ChangeLog entry.Nick Clifton1-1/+1
2003-03-20Add Cirrus Maverick support to arm simulatorNick Clifton1-0/+24
2003-03-02(SWIWrite0): Catch big-endian bug when printing charactersNick Clifton1-0/+5
2003-02-27Index: arm/ChangeLogAndrew Cagney1-0/+4
2003-01-102003-01-10 Ben Elliston <bje@redhat.com>Ben Elliston1-0/+5
2003-01-10* remove duplicated entry from 2002-05-17 on 2002-05-20.Ben Elliston1-23/+1
2002-09-27Add support for -m option. Fix PR gdb/433.Andrew Cagney1-0/+6
2002-08-15Catch and ignore SWIs of -1, they can be caused by an interrupted systemNick Clifton1-0/+5
2002-07-05Add checks to catch invaliud XScale MIA, MIAPH and MIAxy instructions.Nick Clifton1-0/+5
2002-06-21Set correct value for ADP_Stopped_RunTimeErrorNick Clifton1-0/+4
2002-06-16Import current --enable-gdb-build-warnings.Andrew Cagney1-0/+4
2002-06-12Add the file include/gdb/sim-arm.h defining an enum that specifies theAndrew Cagney1-0/+8
2002-06-09Move include/callback.h and include/remote-sim.h to include/gdb/.Andrew Cagney1-0/+5
2002-05-29Set the FSR and FAR registers if a Data Abort is detected.Nick Clifton1-0/+5
2002-05-27Only perform access checks if 'check' is set.Nick Clifton1-0/+5
2002-05-27Thumb BL instruction: Do not set LR to pc + 2, it has already been advanced.Nick Clifton1-0/+5
2002-05-23When decoding a BLX(1) instruction do not add in the second bit of the baseNick Clifton1-0/+6
2002-05-21Simulate XScale BCUMOD registerNick Clifton1-0/+6
2002-05-20Add support for target specific command line switches to old-style simualtors.Nick Clifton1-0/+43
2002-05-09Support the RedBoot SWI in ARM mode and some of its system calls.Nick Clifton1-0/+5
2002-03-18Increase default memory size to 8MB.Anthony Green1-0/+4
2002-02-21 * armos.c (SWIWrite0): Use generic host_callback mechanismKeith Seitz1-0/+10
2002-02-05Modify previous patch so that it is only triggered for COFF format executables.Nick Clifton1-3/+8
2002-02-04If a v5 architecture is detected, assume it might be an XScale binary, sinceNick Clifton1-0/+6
2002-01-10Fix parameters passed to CPRead[13] and CPRead[14].Nick Clifton1-0/+8
2002-01-09General format tidy upsNick Clifton1-0/+1
2002-01-09Fix bug detected by GDB testsuite - when fetching registers more than 4Nick Clifton1-0/+5
2001-11-162001-11-16 Ben Harris <bjh21@netbsd.org>Ben Harris1-0/+6
2001-10-18Add support for XScale's coprocessor access check register.Nick Clifton1-0/+19
2001-05-11Fix handling of XScale LDRD and STRD instructions with post indexed addressin...Nick Clifton1-0/+5
2001-05-08Check Mode not Bank in order to determine rocesor mode.Nick Clifton1-0/+5
2001-04-18* XScale coprocessor support.Matthew Green1-0/+41
2001-03-20Do not enable alignment checking when loading unaligned thumb instructions.Nick Clifton1-0/+5
2001-03-06Fix BLX(1) for ThumbNick Clifton1-0/+6
2001-02-28Add support for disabling alignment checks when performing GDB interfaceNick Clifton1-0/+30
2001-02-16Remove Prefetch abort for breakpoints. Instead set the state to RESUME.Nick Clifton1-0/+5
2001-02-15Add code to preserve processor mode when a prefetchNick Clifton1-0/+3
2001-02-14Reset processor into ARM mode for any machine type except the early ARMs.Nick Clifton1-0/+5
2001-02-14Prevent Aborts from happening whilst emulating a SWINick Clifton1-0/+7
2001-02-12Fix definition of NEGBRANCHNick Clifton1-0/+4
2001-02-01Update base address register after restoring register bank.Nick Clifton1-0/+7
2001-02-01Detect installation of SWI vector by running program as well as loading program.Nick Clifton1-0/+9
2000-12-19Fix test for StoreDouble Instruction.Nick Clifton1-0/+5
2000-12-11Add 0x91 as an FPE SWI.Nick Clifton1-0/+4
2000-12-08Add emulation of double word load and store instructions.Nick Clifton1-0/+8
2000-12-03Suppress support of DEMON swi's in XScale mode.Nick Clifton1-0/+6
2000-11-30Add support for ARM's v5TE architecture and Intel's XScale extenstionsNick Clifton1-1/+27
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