| Age | Commit message (Expand) | Author | Files | Lines |
|---|
| 2023-08-22 | aarch64: Improve naming conventions for A and R-profile architecture | Victor Do Nascimento | 3 | -219/+219 |
| 2023-08-22 | kvx_dis_init | Alan Modra | 1 | -20/+3 |
| 2023-08-21 | bpf: correct neg and neg32 instruction encoding | David Faust | 1 | -4/+0 |
| 2023-08-19 | sim --enable-cgen-maint | Alan Modra | 2 | -2/+8 |
| 2023-08-16 | kvx: New port. | Paul Iannetta | 10 | -0/+112808 |
| 2023-08-15 | RISC-V: Make "fli.h" available to 'Zvfh' + 'Zfa' | Tsukasa OI | 1 | -1/+1 |
| 2023-08-15 | RISC-V: Add support for the 'Zihintntl' extension | Tsukasa OI | 1 | -0/+12 |
| 2023-08-15 | RISC-V: remove indirection from register tables | Jan Beulich | 2 | -12/+12 |
| 2023-08-12 | regen config | Alan Modra | 1 | -21/+52 |
| 2023-08-11 | x86: pack CPU flags in opcode table | Jan Beulich | 4 | -31432/+4568 |
| 2023-08-11 | RISC-V: Fix opcode entries of "vmsge{,u}.vx" | Tsukasa OI | 1 | -4/+4 |
| 2023-08-09 | bpf: use w regs in 32-bit non-fetch atomic pseudo-c | David Faust | 1 | -4/+4 |
| 2023-08-07 | RISC-V: move comment describing rules for riscv_opcodes[] | Jan Beulich | 1 | -10/+10 |
| 2023-08-03 | cris: sprintf optimisation | Alan Modra | 1 | -19/+10 |
| 2023-08-03 | cris: sprintf sanitizer null destination pointer | Alan Modra | 1 | -6/+1 |
| 2023-08-03 | Fix Wlto-type-mismatch in opcodes/ft32-dis.c | Tom de Vries | 1 | -1/+1 |
| 2023-08-02 | Revert "2.41 Release sources" | Sam James | 26 | -10922/+13254 |
| 2023-08-02 | 2.41 Release sourcesbinutils-2_41-release | Nick Clifton | 26 | -13254/+10922 |
| 2023-07-31 | bpf: opcodes: fix regression in BPF disassembler | Jose E. Marchesi | 2 | -1/+7 |
| 2023-07-30 | bpf: include, bfd, opcodes: add EF_BPF_CPUVER ELF header flags | Jose E. Marchesi | 3 | -21/+36 |
| 2023-07-28 | Fix typo in riscv-dis.c comment | Tsukasa OI | 1 | -1/+1 |
| 2023-07-27 | Support Intel PBNDKB | Hu, Lin1 | 7 | -6040/+6090 |
| 2023-07-27 | Support Intel SM4 | Haochen Jiang | 7 | -6751/+6825 |
| 2023-07-27 | Support Intel SM3 | Haochen Jiang | 7 | -6974/+7105 |
| 2023-07-27 | Support Intel SHA512 | Haochen Jiang | 7 | -7051/+7206 |
| 2023-07-27 | Support Intel AVX-VNNI-INT16 | konglin1 | 7 | -5622/+9878 |
| 2023-07-26 | bpf: fix register NEG[32] instructions | Jose E. Marchesi | 2 | -2/+7 |
| 2023-07-26 | Regen bpf opcodes POTFILE | Alan Modra | 3 | -7/+2 |
| 2023-07-25 | bpf: Add atomic compare-and-exchange instructions | David Faust | 1 | -0/+12 |
| 2023-07-25 | bpf: Update atomic instruction pseudo-C syntax | David Faust | 1 | -16/+16 |
| 2023-07-24 | Updated translations for bfd, gold and opcodes | Nick Clifton | 1 | -372/+341 |
| 2023-07-24 | bpf: gas,include,opcode: add suppor for instructions BSWAP{16,32,64} | Jose E. Marchesi | 2 | -0/+13 |
| 2023-07-24 | bpf: gas,opcodes: fix pseudoc syntax for MOVS* and LDXS* insns | Jose E. Marchesi | 2 | -10/+15 |
| 2023-07-24 | bpf: add support for jal/gotol jump instruction with 32-bit target | Jose E. Marchesi | 2 | -0/+8 |
| 2023-07-21 | bpf: disasemble offsets of value 0 as "+0" | David Faust | 1 | -2/+2 |
| 2023-07-21 | bpf: opcodes, gas: support for signed load V4 instructions | Jose E. Marchesi | 2 | -0/+15 |
| 2023-07-21 | bpf: opcodes, gas: support for signed register move V4 instructions | Jose E. Marchesi | 2 | -0/+17 |
| 2023-07-21 | bpf: add missing bpf-dis.c to opcodes/Makefile.am | Jose E. Marchesi | 3 | -0/+8 |
| 2023-07-21 | DesCGENization of the BPF binutils port | Jose E. Marchesi | 12 | -6380/+680 |
| 2023-07-21 | x86: adjust disassembly of insns operating on selector values | Jan Beulich | 1 | -6/+6 |
| 2023-07-21 | x86: simplify disassembly of LAR/LSL | Jan Beulich | 1 | -14/+2 |
| 2023-07-19 | Updated Romainian translation for the opcodes directory | Nick Clifton | 1 | -374/+344 |
| 2023-07-18 | RISC-V: Supports Zcb extension. | Jiawei | 2 | -0/+42 |
| 2023-07-14 | Fix loongarch build with gcc-4.5 | Alan Modra | 1 | -1/+1 |
| 2023-07-11 | x86: simplify table-referencing macros | Jan Beulich | 1 | -17/+15 |
| 2023-07-11 | x86: convert 0FXOP to just XOP in enumerator names | Jan Beulich | 1 | -304/+304 |
| 2023-07-11 | x86: misc further register-only insns don't need to go through mod_table[] | Jan Beulich | 4 | -163/+77 |
| 2023-07-11 | x86: various operations on mask registers can avoid going through mod_table[] | Jan Beulich | 4 | -296/+176 |
| 2023-07-11 | x86: slightly rework handling of some register-only insns | Jan Beulich | 2 | -62/+53 |
| 2023-07-11 | x86: SIMD shift-by-immediate don't need to go through mod_table[] | Jan Beulich | 1 | -54/+18 |
