| Age | Commit message (Expand) | Author | Files | Lines |
|---|
| 2018-10-23 | S/390: Support vector alignment hints | Andreas Krebbel | 1 | -0/+7 |
| 2018-10-22 | S12Z: Disassembly: Fallback to show the address if the symbol table is empty. | John Darrington | 2 | -0/+9 |
| 2018-10-19 | Arm: Fix disassembler crashing on -b binary when thumb file and thumb not for... | Tamar Christina | 2 | -3/+14 |
| 2018-10-16 | AArch64: Fix error checking for SIMD udot (by element) | Matthew Malcomson | 2 | -1/+7 |
| 2018-10-10 | x86: fold Size{16,32,64} template attributes | Jan Beulich | 5 | -15577/+11696 |
| 2018-10-09 | [PATCH, BINUTULS, AARCH64, 9/9] Add SSBS to MSR/MRS | Sudakshina Das | 2 | -0/+23 |
| 2018-10-09 | [PATCH, BINUTILS, AARCH64, 8/9] Add SCXTNUM_ELx and ID_PFR2_EL1 system registers | Sudakshina Das | 2 | -0/+26 |
| 2018-10-09 | [PATCH, BINUTILS, AARCH64, 7/9] Add BTI instruction | Sudakshina Das | 8 | -1136/+1182 |
| 2018-10-09 | [PATCH, BINUTILS, AARCH64, 6/9] Add Random number instructions | Sudakshina Das | 2 | -0/+16 |
| 2018-10-09 | [PATCH, BINUTILS, AARCH64, 5/9] Add DC CVADP instruction | Sudakshina Das | 2 | -0/+11 |
| 2018-10-09 | [PATCH, BINUTILS, AARCH64, 4/9] Add Execution and Data Restriction instructions | Sudakshina Das | 7 | -1089/+1147 |
| 2018-10-09 | [PATCH, BINUTILS, AARCH64, 3/9] Add instruction SB for ARMv8.5-A | Sudakshina Das | 5 | -1014/+1030 |
| 2018-10-09 | [PATCH, BINUTILS, AARCH64, 2/9] Add Data procoessing instructions for ARMv8.5-A | Sudakshina Das | 5 | -2644/+2766 |
| 2018-10-09 | [PATCH, BINUTILS, AARCH64, 1/9] Add -march=armv8.5-a and related internal fea... | Sudakshina Das | 2 | -0/+11 |
| 2018-10-08 | AArch64: Replace C initializers with memset | Tamar Christina | 2 | -1/+7 |
| 2018-10-05 | x86: Add Intel ENCLV to assembler and disassembler | H.J. Lu | 4 | -1/+22 |
| 2018-10-05 | [Arm, 2/3] Add instruction SB for AArch32 | Sudakshina Das | 2 | -0/+11 |
| 2018-10-05 | or1k: Add the l.muld, l.muldu, l.macu, l.msbu insns | Richard Henderson | 6 | -29/+163 |
| 2018-10-05 | or1k: Add the l.adrp insn and supporting relocations | Stafford Horne | 9 | -137/+320 |
| 2018-10-05 | or1k: Add relocations for high-signed and low-stores | Richard Henderson | 2 | -272/+172 |
| 2018-10-03 | AArch64: Constraint disassembler and assembler changes. | Tamar Christina | 4 | -11/+104 |
| 2018-10-03 | AArch64: Add SVE constraints verifier. | Tamar Christina | 3 | -1/+358 |
| 2018-10-03 | AArch64: Refactor verifiers to make more general. | Tamar Christina | 3 | -7/+16 |
| 2018-10-03 | AArch64: Refactor err_type. | Tamar Christina | 2 | -13/+13 |
| 2018-10-03 | AArch64: Wire through instr_sequence | Tamar Christina | 3 | -1/+10 |
| 2018-10-03 | AArch64: Mark sve instructions that require MOVPRFX constraints | Tamar Christina | 2 | -231/+254 |
| 2018-10-02 | RISC-V: Add fence.tso instruction | Palmer Dabbelt | 2 | -0/+5 |
| 2018-09-23 | Fix incorrect extraction of signed constants in nios2 disassembler. | Sandra Loosemore | 2 | -13/+21 |
| 2018-09-21 | csky-opc.h: Initialize fields of last array elements | Simon Marchi | 7 | -68/+14 |
| 2018-09-20 | ARC: Fix build errors with large constants and C89 | Maciej W. Rozycki | 2 | -26/+30 |
| 2018-09-20 | Andes Technology has good news for you, we plan to update the nds32 port of b... | Nick Clifton | 5 | -300/+944 |
| 2018-09-17 | RISC-V: bge[u] should get higher priority than ble[u]. | Jim Wilson | 2 | -2/+6 |
| 2018-09-17 | x86: Set EVex=2 on EVEX.128 only vmovd and vmovq | H.J. Lu | 5 | -13/+94 |
| 2018-09-17 | x86: Set Vex=1 on VEX.128 only vmovd and vmovq | H.J. Lu | 4 | -18/+24 |
| 2018-09-17 | x86: Update disassembler for VexWIG | H.J. Lu | 2 | -1563/+619 |
| 2018-09-17 | x86: Replace VexW=3 with VexWIG | H.J. Lu | 2 | -468/+475 |
| 2018-09-15 | x86: Set VexW=3 on AVX vrsqrtss | H.J. Lu | 3 | -2/+7 |
| 2018-09-15 | x86: Set Vex=1 on VEX.128 only vmovq | H.J. Lu | 4 | -6/+12 |
| 2018-09-14 | x86: Support VEX/EVEX WIG encoding | H.J. Lu | 4 | -932/+941 |
| 2018-09-14 | x86: Handle unsupported static rounding in vcvt[u]si2sd in 32-bit mode | H.J. Lu | 3 | -2/+22 |
| 2018-09-14 | x86: Properly decode EVEX.W in vcvt[u]si2s[sd] in 32-bit mode | H.J. Lu | 3 | -4/+23 |
| 2018-09-14 | i386: Reformat OP_E_memory | H.J. Lu | 2 | -2/+6 |
| 2018-09-14 | x86: fold CRC32 templates | Jan Beulich | 3 | -45/+12 |
| 2018-09-13 | x86: Remove VexW=1 from WIG VEX movq and vmovq | H.J. Lu | 2 | -8/+8 |
| 2018-09-13 | i386: Update VexW field for VEX instructions | H.J. Lu | 3 | -36/+44 |
| 2018-09-13 | x86: drop bogus IgnoreSize from a few further insns | Jan Beulich | 3 | -52/+61 |
| 2018-09-13 | x86: drop bogus IgnoreSize from AVX512_4* insns | Jan Beulich | 3 | -12/+18 |
| 2018-09-13 | x86: drop bogus IgnoreSize from AVX512DQ insns | Jan Beulich | 3 | -96/+102 |
| 2018-09-13 | x86: drop bogus IgnoreSize from AVX512BW insns | Jan Beulich | 3 | -78/+84 |
| 2018-09-13 | x86: drop bogus IgnoreSize from AVX512VL insns | Jan Beulich | 3 | -26/+32 |
