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2016-03-30opcodes/arc: Comment and whitespace fixes in opcode tableAndrew Burgess2-6/+13
2016-03-30[ARC] Cleanup AUX register names.Claudiu Zissulescu2-27/+13
2016-03-29[ARC] Fix typo in extension instruction name.Claudiu Zissulescu2-1/+5
2016-03-29[ARC] Add support for Quarkse opcodes.Claudiu Zissulescu5-6/+130
2016-03-24More -Wstack-usage warnings: opcodes/aarch64-*Jan Kratochvil3-7/+11
2016-03-24sparc: reorder wr instructions in sparc_opcodes to fix diagnosticsJose E. Marchesi2-6/+11
2016-03-22Add -Wstack-usage to the gcc warning flags list, but only if using a sufficie...Nick Clifton2-1/+23
2016-03-21arc/nps400: Add first nps400 instructionsAndrew Burgess3-0/+173
2016-03-21arc/opcodes: Use flag operand class to handle multiple flag matchesAndrew Burgess2-25/+31
2016-03-21arc: Add nps400 machine type, and assembler flag.Andrew Burgess2-0/+8
2016-03-21arc/gas: default mach is arc700, initialised in md_beginAndrew Burgess2-3/+4
2016-03-21Remove use of alloca.Nick Clifton2-2/+3
2016-03-18Fix the disassembly of the AArch64's OOR instruction as a MOV instruction.Nick Clifton2-1/+7
2016-03-16[ARM] Support ARMv8.2 FP16 simd instructionsJiong Wang2-23/+85
2016-03-07Add const qualifiers at various places.Trevor Saunders5-7/+15
2016-03-03Regenerate or1k opcodes fileAlan Modra2-3/+4
2016-03-02Regenerate rl78 opcodes fileAlan Modra2-2/+3
2016-03-02Fix shift left warning at sourceAlan Modra2-1/+5
2016-03-01Fix typo in print_insn_rl78_common function.Nick Clifton2-1/+7
2016-02-24[OPCODES][ARM][1/3]Add armv8.2 fp16 instruction dissembler support.Renlin Li2-4/+92
2016-02-24[OPCODES][ARM]Fix mask for a few coprocessor opcodes.Renlin Li2-8/+13
2016-02-24[OPCODE][ARM]Correct disassembler for cdp/cdp2, mcr/mcr2, mrc/mrc2, ldc/ldc2,...Renlin Li2-0/+28
2016-02-15Add parentheses to prevent truncated addressesH.J. Lu2-2/+8
2016-02-10Add support for ARC instruction relaxation in the assembler.Claudiu Zissulescu2-0/+132
2016-02-04Fix the encoding of the MSP430's RRUX instruction.Nick Clifton2-2/+14
2016-02-02opcodes/cgen: Rework calculation of shift when inserting fieldsAndrew Burgess15-42/+157
2016-02-02epiphany/disassembler: Improve alignment of output.Andrew Burgess2-2/+7
2016-02-01Fix undefined compilation behaviour shifting a value into the sign bit of a s...Michael McConville2-1/+7
2016-01-25[PATCH[ARM]Check mapping symbol while backward searching for IT block.Renlin Li2-3/+83
2016-01-20[AArch64] Reject invalid immediate operands to MSR UAOMatthew Wahab2-2/+9
2016-01-18MIPS: Remove remnants of 48-bit microMIPS instruction supportMaciej W. Rozycki2-35/+6
2016-01-17Regen configureAlan Modra2-1/+5
2016-01-14Fix display of RL78 MOVW instructions that use the stack pointer.Nick Clifton4-3/+23
2016-01-14[AArch64] Fix missing architecture checks for ARMv8.2 system registers.Matthew Wahab2-9/+13
2016-01-12[ARM] Support ARMv8.2 RAS extension.Matthew Wahab2-0/+13
2016-01-11Delete opcodes that have been removed from ISA 3.0.Peter Bergner2-5/+8
2016-01-08m68k: fix constraints of move.[bw] for ISA_B/CAndreas Schwab2-3/+9
2016-01-01Copyright update for binutilsAlan Modra270-273/+277
2016-01-01New 2016 binutils ChangeLog filesAlan Modra1-0/+14
2016-01-01binutils ChangeLog rotationAlan Modra1-0/+0
2015-12-31opcodes/arc: Support dmb instruction with no operandsAndrew Burgess2-0/+8
2015-12-30Fix assorted ChangeLog errorsAlan Modra1-9/+8
2015-12-24Add assembler support for ARMv8-M BaselineThomas Preud'homme2-13/+21
2015-12-24Add assembler support for ARMv8-M MainlineThomas Preud'homme2-12/+25
2015-12-22RXv2 support updateYoshinori Sato3-8/+17
2015-12-15Add support for RX V2 Instruction SetYoshinori Sato4-1280/+2862
2015-12-14[AArch64][PATCH 14/14] Support FP16 Adv.SIMD Scalar Shift By Immediate instru...Matthew Wahab5-1021/+1052
2015-12-14[AArch64][PATCH 13/14] Support FP16 Adv.SIMD Shift By Immediate instructions.Matthew Wahab5-1259/+1288
2015-12-14[AArch64][PATCH 12/14] Support FP16 Adv.SIMD Scalar Pairwise instructions.Matthew Wahab5-1101/+1181
2015-12-14[AArch64][PATCH 11/14] Add support for the 2H vector type.Matthew Wahab3-1/+15
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