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2022-11-04opcodes/arm: silence compiler warning about uninitialized variable useAndrew Burgess1-1/+3
After this commit: commit 6576bffe6cbbb53c5756b2fccd2593ba69b74cdf Date: Thu Jul 7 13:43:45 2022 +0100 opcodes/arm: add disassembler styling for arm Some people were seeing their builds failing with complaints about a possible uninitialized variable usage. I previously fixed an instance of this issue in this commit: commit 2df82cd4b459fbc32120e0ad1ce19e26349506fe Date: Tue Nov 1 10:36:59 2022 +0000 opcodes/arm: silence compiler warning about uninitialized variable use which did fix the build problems that the sourceware buildbot was hitting, however, an additional instance of the same problem was brought to my attention, and that is fixed in this commit. Where commit 2df82cd4b4 fixed the uninitialized variable problem in print_mve_unpredictable, this commit fixes the same problem in print_mve_undefined. As with the previous commit, I don't believe we could really ever get an uninitialized variable usage, based on the current usage of the function, so I have just initialized the reason variable to "??".
2022-11-04Support Intel AVX-NE-CONVERTkonglin16-4169/+4397
gas/ChangeLog: * NEWS: Support Intel AVX-NE-CONVERT. * config/tc-i386.c: Add avx_ne_convert. * doc/c-i386.texi: Document .avx_ne_convert. * testsuite/gas/i386/i386.exp: Run AVX NE CONVERT tests. * testsuite/gas/i386/avx-ne-convert-intel.d: New test. * testsuite/gas/i386/avx-ne-convert.d: Ditto. * testsuite/gas/i386/avx-ne-convert.s: Ditto. * testsuite/gas/i386/x86-64-avx-ne-convert-intel.d: Ditto. * testsuite/gas/i386/x86-64-avx-ne-convert.d: Ditto. * testsuite/gas/i386/x86-64-avx-ne-convert.s: Ditto. opcodes/ChangeLog: * i386-dis.c (Mw): New. (PREFIX_VEX_0F3872): Ditto. (PREFIX_VEX_0F38B0_W_0): Ditto. (PREFIX_VEX_0F38B1_W_0): Ditto. (VEX_W_0F3872_P_1): Ditto. (VEX_W_0F38B0): Ditto. (VEX_W_0F38B1): Ditto. (prefix_table): Add PREFIX_VEX_0F3872, PREFIX_VEX_0F38B0_W_0, PREFIX_VEX_0F38B1_W_0. (vex_w_table): Add VEX_W_0F3872_P_1, VEX_W_0F38B0, VEX_W_0F38B1. * i386-gen.c (cpu_flag_init): Add CPU_AVX_NE_CONVERT_FLGAS and CPU_ANY_AVX_NE_CONVERT_FLAGS. (cpu_flags): Add CpuAVX_NE_CONVERT. * i386-init.h: Regenerated. * i386-opc.h (CpuAVX_NE CONVERT): New. (i386_cpu_flags): Add cpuavx_ne_convert. * i386-opc.tbl: Add Intel AVX-NE-CONVERT instructions. * i386-tbl.h: Regenerated.
2022-11-04i386: Rename <xy> template.konglin11-17/+18
opcodes/ * i386-opc.tbl: Rename <xy> template for VEX insn with x/y suffix to <Vxy>. Rename <xy> for EVEX insn with x/y suffix to <Exy>.
2022-11-02x86: drop bogus TbyteJan Beulich2-4/+4
Prior to commit 1cb0ab18ad24 ("x86/Intel: restrict suffix derivation") the Tbyte modifier on the FLDT and FSTPT templates was pointless, as No_ldSuf would have prevented it being accepted. Due to the special nature of LONG_DOUBLE_MNEM_SUFFIX said commit, however, has led to these insns being accepted in Intel syntax mode even when "tbyte ptr" was present. Restore original behavior by dropping Tbyte there. (Note that these insns in principle should by marked AT&T syntax only, but since they haven't been so far we probably shouldn't change that.)
2022-11-02Support Intel MSRLISTHu, Lin16-4161/+4237
gas/ChangeLog: * NEWS: Support Intel MSRLIST. * config/tc-i386.c: Add msrlist. * doc/c-i386.texi: Document .msrlist. * testsuite/gas/i386/i386.exp: Add MSRLIST tests. * testsuite/gas/i386/msrlist-inval.l: New test. * testsuite/gas/i386/msrlist-inval.s: Ditto. * testsuite/gas/i386/x86-64-msrlist-intel.d: Ditto. * testsuite/gas/i386/x86-64-msrlist.d: Ditto. * testsuite/gas/i386/x86-64-msrlist.s: Ditto. opcodes/ChangeLog: * i386-dis.c (X86_64_0F01_REG_0_MOD_3_RM_6_P_1): New. (X86_64_0F01_REG_0_MOD_3_RM_6_P_3): Ditto. (prefix_table): New entry for msrlist. (x86_64_table): Add X86_64_0F01_REG_0_MOD_3_RM_6_P_1 and X86_64_0F01_REG_0_MOD_3_RM_6_P_3. * i386-gen.c (cpu_flag_init): Add CPU_MSRLIST_FLAGS and CPU_ANY_MSRLIST_FLAGS. * i386-init.h: Regenerated. * i386-opc.h (CpuMSRLIST): New. (i386_cpu_flags): Add cpumsrlist. * i386-opc.tbl: Add MSRLIST instructions. * i386-tbl.h: Regenerated.
2022-11-02Support Intel WRMSRNSHu, Lin16-4160/+4212
gas/ChangeLog: * NEWS: Support Intel WRMSRNS. * config/tc-i386.c: Add wrmsrns. * doc/c-i386.texi: Document .wrmsrns. * testsuite/gas/i386/i386.exp: Add WRMSRNS tests. * testsuite/gas/i386/wrmsrns-intel.d: New test. * testsuite/gas/i386/wrmsrns.d: Ditto. * testsuite/gas/i386/wrmsrns.s: Ditto. * testsuite/gas/i386/x86-64-wrmsrns-intel.d: Ditto. * testsuite/gas/i386/x86-64-wrmsrns.d: Ditto. opcodes/ChangeLog: * i386-dis.c (PREFIX_0F01_REG_0_MOD_3_RM_6): New. (prefix_table): Add PREFIX_0F01_REG_0_MOD_3_RM_6. (rm_table): New entry for wrmsrns. * i386-gen.c (cpu_flag_init): Add CPU_WRMSRNS_FLAGS and CPU_ANY_WRMSRNS_FLAGS. (cpu_flags): Add CpuWRMSRNS. * i386-init.h: Regenerated. * i386-opc.h (CpuWRMSRNS): New. (i386_cpu_flags): Add cpuwrmsrns. * i386-opc.tbl: Add WRMSRNS instructions. * i386-tbl.h: Regenerated.
2022-11-02Support Intel CMPccXADDHaochen Jiang6-4150/+4805
gas/ChangeLog: * NEWS: Support Intel CMPccXADD. * config/tc-i386.c: Add cmpccxadd. (build_modrm_byte): Add operations for Vex.VVVV reg on operand 0 while have memory operand. * doc/c-i386.texi: Document .cmpccxadd. * testsuite/gas/i386/i386.exp: Run CMPccXADD tests. * testsuite/gas/i386/cmpccxadd-inval.s: New test. * testsuite/gas/i386/cmpccxadd-inval.l: Ditto. * testsuite/gas/i386/x86-64-cmpccxadd-intel.d: Ditto. * testsuite/gas/i386/x86-64-cmpccxadd.s: Ditto. * testsuite/gas/i386/x86-64-cmpccxadd.d: Ditto. opcodes/ChangeLog: * i386-dis.c (Mdq): New. (X86_64_VEX_0F38E0): Ditto. (X86_64_VEX_0F38E1): Ditto. (X86_64_VEX_0F38E2): Ditto. (X86_64_VEX_0F38E3): Ditto. (X86_64_VEX_0F38E4): Ditto. (X86_64_VEX_0F38E5): Ditto. (X86_64_VEX_0F38E6): Ditto. (X86_64_VEX_0F38E7): Ditto. (X86_64_VEX_0F38E8): Ditto. (X86_64_VEX_0F38E9): Ditto. (X86_64_VEX_0F38EA): Ditto. (X86_64_VEX_0F38EB): Ditto. (X86_64_VEX_0F38EC): Ditto. (X86_64_VEX_0F38ED): Ditto. (X86_64_VEX_0F38EE): Ditto. (X86_64_VEX_0F38EF): Ditto. (x86_64_table): Add X86_64_VEX_0F38E0, X86_64_VEX_0F38E1, X86_64_VEX_0F38E2, X86_64_VEX_0F38E3, X86_64_VEX_0F38E4, X86_64_VEX_0F38E5, X86_64_VEX_0F38E6, X86_64_VEX_0F38E7, X86_64_VEX_0F38E8, X86_64_VEX_0F38E9, X86_64_VEX_0F38EA, X86_64_VEX_0F38EB, X86_64_VEX_0F38EC, X86_64_VEX_0F38ED, X86_64_VEX_0F38EE, X86_64_VEX_0F38EF. * i386-gen.c (cpu_flag_init): Add CPU_CMPCCXADD_FLAGS and CPU_ANY_CMPCCXADD_FLAGS. (cpu_flags): Add CpuCMPCCXADD. * i386-init.h: Regenerated. * i386-opc.h (CpuCMPCCXADD): New. (i386_cpu_flags): Add cpucmpccxadd. Comment unused for it is actually 0. * i386-opc.tbl: Add Intel CMPccXADD instructions. * i386-tbl.h: Regenerated.
2022-11-02Support Intel AVX-VNNI-INT8Cui,Lili6-456/+612
gas/ * NEWS: Support Intel AVX-VNNI-INT8. * config/tc-i386.c: Add avx_vnni_int8. * doc/c-i386.texi: Document avx_vnni_int8. * testsuite/gas/i386/avx-vnni-int8-intel.d: New file. * testsuite/gas/i386/avx-vnni-int8.d: Likewise. * testsuite/gas/i386/avx-vnni-int8.s: Likewise. * testsuite/gas/i386/x86-64-avx-vnni-int8-intel.d: Likewise. * testsuite/gas/i386/x86-64-avx-vnni-int8.d: Likewise. * testsuite/gas/i386/x86-64-avx-vnni-int8.s: Likewise. * testsuite/gas/i386/i386.exp: Run AVX VNNI INT8 tests. opcodes/ * i386-dis.c: (PREFIX_VEX_0F3850) New. (PREFIX_VEX_0F3851): Likewise. (VEX_W_0F3850_P_0): Likewise. (VEX_W_0F3850_P_1): Likewise. (VEX_W_0F3850_P_2): Likewise. (VEX_W_0F3850_P_3): Likewise. (VEX_W_0F3851_P_0): Likewise. (VEX_W_0F3851_P_1): Likewise. (VEX_W_0F3851_P_2): Likewise. (VEX_W_0F3851_P_3): Likewise. (VEX_W_0F3850): Delete. (VEX_W_0F3851): Likewise. (prefix_table): Add PREFIX_VEX_0F3850 and PREFIX_VEX_0F3851. (vex_table): Add PREFIX_VEX_0F3850 and PREFIX_VEX_0F3851, delete VEX_W_0F3850 and VEX_W_0F3851. (vex_w_table): Add VEX_W_0F3850_P_0, VEX_W_0F3850_P_1, VEX_W_0F3850_P_2 VEX_W_0F3850_P_3, VEX_W_0F3851_P_0, VEX_W_0F3851_P_1, VEX_W_0F3851_P_2 and VEX_W_0F3851_P_3, delete VEX_W_0F3850 and VEX_W_0F3851. * i386-gen.c: (cpu_flag_init): Add CPU_AVX_VNNI_INT8_FLAGS and CPU_ANY_AVX_VNNI_INT8_FLAGS. (cpu_flags): Add CpuAVX_VNNI_INT8. * i386-opc.h (CpuAVX_VNNI_INT8): New. * i386-opc.tbl: Add Intel AVX_VNNI_INT8 instructions. * i386-init.h: Regenerated. * i386-tbl.h: Likewise.
2022-11-02Support Intel AVX-IFMAHongyu Wang7-4145/+4224
x86: Support Intel AVX-IFMA Intel AVX IFMA instructions are marked with CpuVEX_PREFIX, which is cleared by default. Without {vex} pseudo prefix, Intel IFMA instructions are encoded with EVEX prefix. {vex} pseudo prefix will turn on VEX encoding for Intel IFMA instructions. gas/ * NEWS: Support Intel AVX-IFMA. * config/tc-i386.c (cpu_arch): Add avx_ifma. * doc/c-i386.texi: Document .avx_ifma. * testsuite/gas/i386/avx-ifma.d: New file. * testsuite/gas/i386/avx-ifma-intel.d: Likewise. * testsuite/gas/i386/avx-ifma.s: Likewise. * testsuite/gas/i386/x86-64-avx-ifma.d: Likewise. * testsuite/gas/i386/x86-64-avx-ifma-intel.d: Likewise. * testsuite/gas/i386/x86-64-avx-ifma.s: Likewise. * testsuite/gas/i386/i386.exp: Run AVX IFMA tests. opcodes/ * i386-dis.c (PREFIX_VEX_0F38B4): New. (PREFIX_VEX_0F38B5): Likewise. (VEX_W_0F38B4_P_2): Likewise. (VEX_W_0F38B5_P_2): Likewise. (prefix_table): Add PREFIX_VEX_0F38B4 and PREFIX_VEX_0F38B5. (vex_table): Add VEX_W_0F38B4_P_2 and VEX_W_0F38B5_P_2. * i386-dis-evex.h: Fold AVX512IFMA entries to AVX-IFMA. * i386-gen.c (cpu_flag_init): Clear the CpuAVX_IFMA bit in CPU_UNKNOWN_FLAGS. Add CPU_AVX_IFMA_FLGAS and CPU_ANY_AVX_IFMA_FLAGS. Add CpuAVX_IFMA to CPU_AVX2_FLAGS. (cpu_flags): Add CpuAVX_IFMA. * i386-opc.h (CpuAVX_IFMA): New. (i386_cpu_flags): Add cpuavx_ifma. * i386-opc.tbl: Add Intel AVX IFMA instructions. * i386-init.h: Regenerated. * i386-tbl.h: Likewise. Co-authored-by: Haochen Jiang <haochen.jiang@intel.com>
2022-11-01opcodes/arm: don't pass non-string literal to printf like functionAndrew Burgess1-2/+3
The earlier commit: commit 6576bffe6cbbb53c5756b2fccd2593ba69b74cdf Date: Thu Jul 7 13:43:45 2022 +0100 opcodes/arm: add disassembler styling for arm introduced two places where a register name was passed as the format string to the disassembler's fprintf_styled_func callback. This will cause a warning from some compilers, like this: ../../binutils-gdb/opcodes/arm-dis.c: In function ‘print_mve_vld_str_addr’: ../../binutils-gdb/opcodes/arm-dis.c:6005:3: error: format not a string literal and no format arguments [-Werror=format-security] 6005 | func (stream, dis_style_register, arm_regnames[gpr]); | ^~~~ This commit fixes these by using "%s" as the format string.
2022-11-01opcodes/arm: silence compiler warning about uninitialized variable useAndrew Burgess1-1/+3
The earlier commit: commit 6576bffe6cbbb53c5756b2fccd2593ba69b74cdf Date: Thu Jul 7 13:43:45 2022 +0100 opcodes/arm: add disassembler styling for arm was causing a compiler warning about a possible uninitialized variable usage within opcodes/arm-dis.c. The problem is in print_mve_unpredictable, and relates to the reason variable, which is set by a switch table. Currently the switch table does cover every valid value, though there is no default case. The variable switched on is passed in as an argument to the print_mve_unpredictable function. Looking at how print_mve_unpredictable is used, there is only one use, the second argument is the one that is used for the switch table, looking at how this argument is set, I don't believe it is possible for this argument to take an invalid value. So, I think the compiler warning is a false positive. As such, my proposed solution is to initialize the reason variable to the string "??", this will silence the warning, and the "??" string should never end up being printed.
2022-11-01opcodes/arm: add disassembler styling for armAndrew Burgess2-1002/+1631
This commit adds disassembler styling for the ARM architecture. The ARM disassembler is driven by several instruction tables, e.g. cde_opcodes, coprocessor_opcodes, neon_opcodes, etc The type for elements in each table can vary, but they all have one thing in common, a 'const char *assembler' field. This field contains a string that describes the assembler syntax of the instruction. Embedded within that assembler syntax are various escape characters, prefixed with a '%'. Here's an example of a very simple instruction from the arm_opcodes table: "pld\t%a" The '%a' indicates a particular type of operand, the function print_insn_arm processes the arm_opcodes table, and includes a switch statement that handles the '%a' operand, and takes care of printing the correct value for that instruction operand. It is worth noting that there are many print_* functions, each function handles a single *_opcodes table, and includes its own switch statement for operand handling. As a result, every *_opcodes table uses a different mapping for the operand escape sequences. This means that '%a' might print an address for one *_opcodes table, but in a different *_opcodes table '%a' might print a register operand. Notice as well that in our example above, the instruction mnemonic 'pld' is embedded within the assembler string. Some instructions also include comments within the assembler string, for example, also from the arm_opcodes table: "nop\t\t\t@ (mov r0, r0)" here, everything after the '@' is a comment that is displayed at the end of the instruction disassembly. The next complexity is that the meaning of some escape sequences is not necessarily fixed. Consider these two examples from arm_opcodes: "ldrex%c\tr%12-15d, [%16-19R]" "setpan\t#%9-9d" Here, the '%d' escape is used with a bitfield modifier, '%12-15d' in the first instruction, and '%9-9d' in the second instruction, but, both of these are the '%d' escape. However, in the first instruction, the '%d' is used to print a register number, notice the 'r' immediately before the '%d'. In the second instruction the '%d' is used to print an immediate, notice the '#' just before the '%d'. We have two problems here, first, the '%d' needs to know if it should use register style or immediate style, and secondly, the 'r' and '#' characters also need to be styled appropriately. The final thing we must consider is that some escape codes result in more than just a single operand being printed, for example, the '%q' operand as used in arm_opcodes ends up calling arm_decode_shift, which can print a register name, a shift type, and a shift amount, this could end up using register, sub-mnemonic, and immediate styles, as well as the text style for things like ',' between the different parts. I propose a three layer approach to adding styling: (1) Basic state machine: When we start printing an instruction we should maintain the idea of a 'base_style'. Every character from the assembler string will be printed using the base_style. The base_style will start as mnemonic, as each instruction starts with an instruction mnemonic. When we encounter the first '\t' character, the base_style will change to text. When we encounter the first '@' the base_style will change to comment_start. This simple state machine ensures that for simple instructions the basic parts, except for the operands themselves, will be printed in the correct style. (2) Simple operand styling: For operands that only have a single meaning, or which expand to multiple parts, all of which have a consistent meaning, then I will simply update the operand printing code to print the operand with the correct style. This will cover a large number of the operands, and is the most consistent with how styling has been added to previous architectures. (3) New styling syntax in assembler strings: For cases like the '%d' that I describe above, I propose adding a new extension to the assembler syntax. This extension will allow me to temporarily change the base_style. Operands like '%d', will then print using the base_style rather than using a fixed style. Here are the two examples from above that use '%d', updated with the new syntax extension: "ldrex%c\t%{R:r%12-15d%}, [%16-19R]" "setpan\t%{I:#%9-9d%}" The syntax has the general form '%{X:....%}' where the 'X' character changes to indicate a different style. In the first instruction I use '%{R:...%}' to change base_style to the register style, and in the second '%{I:...%}' changes base_style to immediate style. Notice that the 'r' and '#' characters are included within the new style group, this ensures that these characters are printed with the correct style rather than as text. The function decode_base_style maps from character to style. I've included a character for each style for completeness, though only a small number of styles are currently used. I have updated arm-dis.c to the above scheme, and checked all of the tests in gas/testsuite/gas/arm/, and the styling looks reasonable. There are no regressions on the ARM gas/binutils/ld tests that I can see, so I don't believe I've changed the output layout at all. There were two binutils tests for which I needed to force the disassembler styling off. I can't guarantee that I've not missed some untested corners of the disassembler, or that I might have just missed some incorrectly styled output when reviewing the test results, but I don't believe I've introduced any changes that could break the disassembler - the worst should be some aspect is not styled correctly.
2022-11-01opcodes/arm: use '@' consistently for the comment characterAndrew Burgess1-48/+48
Looking at the ARM disassembler output, every comment seems to start with a ';' character, so I assumed this was the correct character to start an assembler comment. I then spotted a couple of places where there was no ';', but instead, just a '@' character. I thought that this was a case of a missing ';', and proposed a patch to add the missing ';' characters. Turns out I was wrong, '@' is actually the ARM assembler comment character, while ';' is the statement separator. Thus this: nop ;@ comment is two statements, the first is the 'nop' instruction, while the second contains no instructions, just the '@ comment' comment text. This: nop @ comment is a single 'nop' instruction followed by a comment. And finally, this: nop ; comment is two statements, the first contains the 'nop' instruction, while the second contains the instruction 'comment', which obviously isn't actually an instruction at all. Why this matters is that, in the next commit, I would like to add libopcodes syntax styling support for ARM. The question then is how should the disassembler style the three cases above? As '@' is the actual comment start character then clearly the '@' and anything after it can be styled as a comment. But what about ';' in the second example? Style as text? Style as a comment? And the third example is even harder, what about the 'comment' text? Style as an instruction mnemonic? Style as text? Style as a comment? I think the only sensible answer is to move the disassembler to use '@' consistently as its comment character, and remove all the uses of ';'. Then, in the next commit, it's obvious what to do. There's obviously a *lot* of tests that get updated by this commit, the only actual code changes are in opcodes/arm-dis.c.
2022-10-31x86: minor improvements to optimize_imm() (part III)Jan Beulich2-6/+0
Earlier tidying still missed an opportunity: There's no need for the "anyimm" static variable. Instead of using it in the loop to mask "allowed" (which is necessary to satisfy operand_type_or()'s assertions) simply use "mask", requiring it to be calculated first. That way the post-loop masking by "mask" ahead of the operand_type_all_zero() can be dropped.
2022-10-31Updated Romainain translation for the binutils sub-directory and Swedish ↵Nick Clifton1-399/+475
translations for the ld and opcodes sub-directories.
2022-10-31Support Intel PREFETCHICui, Lili6-4141/+4263
gas/ChangeLog: * NEWS: Add support for Intel PREFETCHI instruction. * config/tc-i386.c (load_insn_p): Use prefetch* to fold all prefetches. (md_assemble): Add warning for illegal input of PREFETCHI. * doc/c-i386.texi: Document .prefetchi. * testsuite/gas/i386/i386.exp: Run PREFETCHI tests. * testsuite/gas/i386/x86-64-lfence-load.d: Add PREFETCHI. * testsuite/gas/i386/x86-64-lfence-load.s: Likewise. * testsuite/gas/i386/x86-64-prefetch.d: New test. * testsuite/gas/i386/x86-64-prefetchi-intel.d: Likewise. * testsuite/gas/i386/x86-64-prefetchi-inval-register.d: Likewise.. * testsuite/gas/i386/x86-64-prefetchi-inval-register.s: Likewise. * testsuite/gas/i386/x86-64-prefetchi-warn.l: Likewise. * testsuite/gas/i386/x86-64-prefetchi-warn.s: Likewise. * testsuite/gas/i386/x86-64-prefetchi.d: Likewise. * testsuite/gas/i386/x86-64-prefetchi.s: Likewise. opcodes/ChangeLog: * i386-dis.c (reg_table): Add MOD_0F18_REG_6 and MOD_0F18_REG_7 (x86_64_table): Add X86_64_0F18_REG_6_MOD_0 and X86_64_0F18_REG_7_MOD_0. (mod_table): Add MOD_0F18_REG_6 and MOD_0F18_REG_7. (prefix_table): Add PREFIX_0F18_REG_6_MOD_0_X86_64 and PREFIX_0F18_REG_7_MOD_0_X86_64. (PREFETCHI_Fixup): New. * i386-gen.c (cpu_flag_init): Add CPU_PREFETCHI_FLAGS. (cpu_flags): Add CpuPREFETCHI. * i386-opc.h (CpuPREFETCHI): New. (i386_cpu_flags): Add cpuprefetchi. * i386-opc.tbl: Add Intel PREFETCHI instructions. * i386-init.h: Regenerated. * i386-tbl.h: Likewise.
2022-10-31RX assembler: switch arguments of thw MVTACGU insn.Yoshinori Sato3-8/+13
2022-10-28RISC-V: Output mapping symbols with ISA string.Nelson Chu1-0/+9
RISC-V Psabi pr196, https://github.com/riscv-non-isa/riscv-elf-psabi-doc/pull/196 bfd/ * elfxx-riscv.c (riscv_release_subset_list): Free arch_str if needed. (riscv_copy_subset_list): Copy arch_str as well. * elfxx-riscv.h (riscv_subset_list_t): Store arch_str for each subset list. gas/ * config/tc-riscv.c (riscv_reset_subsets_list_arch_str): Update the architecture string in the subset_list. (riscv_set_arch): Call riscv_reset_subsets_list_arch_str after parsing new architecture string. (s_riscv_option): Likewise. (need_arch_map_symbol): New boolean, used to indicate if .option directives do affect instructions. (make_mapping_symbol): New boolean parameter reset_seg_arch_str. Need to generate $x+arch for MAP_INSN, and then store it into tc_segment_info_data if reset_seg_arch_str is true. (riscv_mapping_state): Decide if we need to add $x+arch for MAP_INSN. For now, only add $x+arch if the architecture strings in subset list and segment are different. Besides, always add $x+arch at the start of section, and do not add $x+arch for code alignment, since rvc for alignment can be judged from addend of R_RISCV_ALIGN. (riscv_remove_mapping_symbol): If current and previous mapping symbol have same value, then remove the current $x only if the previous is $x+arch; Otherwise, always remove previous. (riscv_add_odd_padding_symbol): Updated. (riscv_check_mapping_symbols): Don't need to add any $x+arch if need_arch_map_symbol is false, so changed them to $x. (riscv_frag_align_code): Updated since riscv_mapping_state is changed. (riscv_init_frag): Likewise. (s_riscv_insn): Likewise. (riscv_elf_final_processing): Call riscv_release_subset_list to release subset_list of riscv_rps_as, rather than only release arch_str in the riscv_write_out_attrs. (riscv_write_out_attrs): No need to call riscv_arch_str, just get arch_str from subset_list of riscv_rps_as. * config/tc-riscv.h (riscv_segment_info_type): Record current $x+arch mapping symbol of each segment. * testsuite/gas/riscv/mapping-0*: Merged and replaced by mapping.s. * testsuite/gas/riscv/mapping.s: New testcase, to test most of the cases in one file. * testsuite/gas/riscv/mapping-symbols.d: Likewise. * testsuite/gas/riscv/mapping-dis.d: Likewise. * testsuite/gas/riscv/mapping-non-arch.s: New testcase for the case that does need any $x+arch. * testsuite/gas/riscv/mapping-non-arch.d: Likewise. * testsuite/gas/riscv/option-arch-01a.d: Updated. opcodes/ * riscv-dis.c (riscv_disassemble_insn): Set riscv_fpr_names back to riscv_fpr_names_abi or riscv_fpr_names_numeric when zfinx is disabled for some specfic code region. (riscv_get_map_state): Recognized mapping symbols $x+arch, and then reset the architecture string once the ISA is different.
2022-10-27PowerPC: Add support for RFC02658 - MMA+ Outer-Product InstructionsPeter Bergner1-1/+38
gas/ * config/tc-ppc.c (md_assemble): Only check for prefix opcodes. * testsuite/gas/ppc/rfc02658.s: New test. * testsuite/gas/ppc/rfc02658.d: Likewise. * testsuite/gas/ppc/ppc.exp: Run it. opcodes/ * ppc-opc.c (XMSK8, P_GERX4_MASK, P_GERX2_MASK, XX3GERX_MASK): New. (powerpc_opcodes): Add dmxvi8gerx4pp, dmxvi8gerx4, dmxvf16gerx2pp, dmxvf16gerx2, dmxvbf16gerx2pp, dmxvf16gerx2np, dmxvbf16gerx2, dmxvi8gerx4spp, dmxvbf16gerx2np, dmxvf16gerx2pn, dmxvbf16gerx2pn, dmxvf16gerx2nn, dmxvbf16gerx2nn, pmdmxvi8gerx4pp, pmdmxvi8gerx4, pmdmxvf16gerx2pp, pmdmxvf16gerx2, pmdmxvbf16gerx2pp, pmdmxvf16gerx2np, pmdmxvbf16gerx2, pmdmxvi8gerx4spp, pmdmxvbf16gerx2np, pmdmxvf16gerx2pn, pmdmxvbf16gerx2pn, pmdmxvf16gerx2nn, pmdmxvbf16gerx2nn.
2022-10-27PowerPC: Add support for RFC02653 - Dense Math FacilityPeter Bergner2-26/+191
gas/ * config/tc-ppc.c (pre_defined_registers): Add dense math registers. (md_assemble): Check dmr specified in correct operand. * testsuite/gas/ppc/outerprod.s <dmsetaccz, dmxvbf16ger2, dmxvbf16ger2nn, dmxvbf16ger2np, dmxvbf16ger2pn, dmxvbf16ger2pp, dmxvf16ger2, dmxvf16ger2nn, dmxvf16ger2np, dmxvf16ger2pn, dmxvf16ger2pp, dmxvf32ger, dmxvf32gernn, dmxvf32gernp, dmxvf32gerpn, dmxvf32gerpp, dmxvf64ger, dmxvf64gernn, dmxvf64gernp, dmxvf64gerpn, dmxvf64gerpp, dmxvi16ger2, dmxvi16ger2pp, dmxvi16ger2s, dmxvi16ger2spp, dmxvi4ger8, dmxvi4ger8pp, dmxvi8ger4, dmxvi8ger4pp, dmxvi8ger4spp, dmxxmfacc, dmxxmtacc, pmdmxvbf16ger2, pmdmxvbf16ger2nn, pmdmxvbf16ger2np, pmdmxvbf16ger2pn, pmdmxvbf16ger2pp, pmdmxvf16ger2, pmdmxvf16ger2nn, pmdmxvf16ger2np, pmdmxvf16ger2pn, pmdmxvf16ger2pp, pmdmxvf32ger, pmdmxvf32gernn, pmdmxvf32gernp, pmdmxvf32gerpn, pmdmxvf32gerpp, pmdmxvf64ger, pmdmxvf64gernn, pmdmxvf64gernp, pmdmxvf64gerpn, pmdmxvf64gerpp, pmdmxvi16ger2, pmdmxvi16ger2pp, pmdmxvi16ger2s, pmdmxvi16ger2spp, pmdmxvi4ger8, pmdmxvi4ger8pp, pmdmxvi8ger4, pmdmxvi8ger4pp, pmdmxvi8ger4spp>: Add new tests. * testsuite/gas/ppc/outerprod.d: Likewise. * testsuite/gas/ppc/rfc02653.s: New test. * testsuite/gas/ppc/rfc02653.d: Likewise. * testsuite/gas/ppc/ppc.exp: Run it. include/ * opcode/ppc.h (PPC_OPERAND_DMR): Define. Renumber following PPC_OPERAND defines. opcodes/ * ppc-dis.c (print_insn_powerpc): Prepend 'dm' when printing DMR regs. * ppc-opc.c (insert_p2, (extract_p2, (insert_xa5, (extract_xa5, insert_xb5, (extract_xb5): New functions. (insert_xa6a, extract_xa6a, insert_xb6a, extract_xb6a): Disallow operand overlap only on Power10. (DMR, DMRAB, P1, P2, XA5p, XB5p, XDMR_MASK, XDMRDMR_MASK, XX2ACC_MASK, XX2DMR_MASK, XX3DMR_MASK): New defines. (powerpc_opcodes): Add dmmr, dmsetaccz, dmsetdmrz, dmxor, dmxvbf16ger2, dmxvbf16ger2nn, dmxvbf16ger2np, dmxvbf16ger2pn, dmxvbf16ger2pp, dmxvf16ger2, dmxvf16ger2nn, dmxvf16ger2np, dmxvf16ger2pn, dmxvf16ger2pp, dmxvf32ger, dmxvf32gernn, dmxvf32gernp, dmxvf32gerpn, dmxvf32gerpp, dmxvf64ger, dmxvf64gernn, dmxvf64gernp, dmxvf64gerpn, dmxvf64gerpp, dmxvi16ger2, dmxvi16ger2pp, dmxvi16ger2s, dmxvi16ger2spp, dmxvi4ger8, dmxvi4ger8pp, dmxvi8ger4, dmxvi8ger4pp, dmxvi8ger4spp, dmxxextfdmr256, dmxxextfdmr512, dmxxinstdmr256, dmxxinstdmr512, dmxxmfacc, dmxxmtacc, pmdmxvbf16ger2, pmdmxvbf16ger2nn, pmdmxvbf16ger2np, pmdmxvbf16ger2pn, pmdmxvbf16ger2pp, pmdmxvf16ger2, pmdmxvf16ger2nn, pmdmxvf16ger2np, pmdmxvf16ger2pn, pmdmxvf16ger2pp, pmdmxvf32ger, pmdmxvf32gernn, pmdmxvf32gernp, pmdmxvf32gerpn, pmdmxvf32gerpp, pmdmxvf64ger, pmdmxvf64gernn, pmdmxvf64gernp, pmdmxvf64gerpn, pmdmxvf64gerpp, pmdmxvi16ger2, pmdmxvi16ger2pp, pmdmxvi16ger2s, pmdmxvi16ger2spp, pmdmxvi4ger8, pmdmxvi4ger8pp, pmdmxvi8ger4, pmdmxvi8ger4pp, pmdmxvi8ger4spp.
2022-10-24x86: emit {evex} prefix when disassembling ambiguous AVX512VL insnsJan Beulich6-235/+271
When no AVX512-specific functionality is in use, the disassembly of AVX512VL insns is indistinguishable from their AVX counterparts (if such exist). Emit the {evex} pseudo-prefix in such cases. Where applicable drop stray uses of PREFIX_OPCODE from table entries.
2022-10-21Support Intel AMX-FP16Cui,Lili6-4088/+4139
gas/ * NEWS: Add support for Intel AMX-FP16 instruction. * config/tc-i386.c: Add amx_fp16. * doc/c-i386.texi: Document .amx_fp16. * testsuite/gas/i386/i386.exp: Add AMX-FP16 tests. * testsuite/gas/i386/x86-64-amx-fp16-intel.d: New test. * testsuite/gas/i386/x86-64-amx-fp16.d: Likewise. * testsuite/gas/i386/x86-64-amx-fp16.s: Likewise. * testsuite/gas/i386/x86-64-amx-fp16-bad.d: Likewise. * testsuite/gas/i386/x86-64-amx-fp16-bad.s: Likewise. opcodes/ * i386-dis.c (MOD_VEX_0F385C_X86_64_P_3_W_0): New. (VEX_LEN_0F385C_X86_64_P_3_W_0_M_0): Likewise. (VEX_W_0F385C_X86_64_P_3): Likewise. (prefix_table): Add VEX_W_0F385C_X86_64_P_3. (vex_len_table): Add VEX_LEN_0F385C_X86_64_P_3_W_0_M_0. (vex_w_table): Add VEX_W_0F385C_X86_64_P_3. (mod_table): Add MOD_VEX_0F385C_X86_64_P_3_W_0. * i386-gen.c (cpu_flag_init): Add AMX-FP16_FLAGS. (CPU_ANY_AMX_TILE_FLAGS): Add CpuAMX_FP16. (cpu_flags): Add CpuAMX-FP16. * i386-opc.h (enum): Add CpuAMX-FP16. (i386_cpu_flags): Add cpuamx_fp16. * i386-opc.tbl: Add Intel AMX-FP16 instruction. * i386-init.h: Regenerate. * i386-tbl.h: Likewise.
2022-10-20x86: re-work AVX-VNNI supportJan Beulich4-7025/+7021
By putting the templates after their AVX512 counterparts, the AVX512 flavors will be picked by default. That way the need to always use {vex} ceases to exist once respective CPU features (AVX512-VNNI or AVX512VL as a whole) have been disabled. This way the need for the PseudoVexPrefix attribute also disappears.
2022-10-18x86: Disable AVX-VNNI when disabling AVX2H.J. Lu2-3/+3
Since AVX-VNNI requires AVX2, disable AVX-VNNI when disabling AVX2. * i386-gen.c (cpu_flag_init): Add CpuAVX_VNNI to CPU_ANY_AVX2_FLAGS. * i386-init.h: Regenerate.
2022-10-18x86: correct CPU_AMX_{BF16,INT8}_FLAGSJan Beulich2-4/+4
AMX-TILE is a prereq to these, as already correctly expressed by CPU_ANY_AMX_TILE_FLAGS. Express the dependency also in the reverse ("positive") direction.
2022-10-17Allow explicit size specifier for predicate operand of {sq, uq, }{incp, decp}CaiJingtao2-7/+17
Omitting predicate size specifier in vector form of {sq, uq, }{decp, incp} is deprecated and will be prohibited in a future release of the aarch64, see https://developer.arm.com/documentation/ddi0602/2021-09/SVE-Instructions/DECP--vector---Decrement-vector-by-count-of-true-predicate-elements-. This allows explicit size specifier, e.g. `decp z0.h, p0.h`, for predicate operand of these SVE instructions. The existing behaviour of not requiring the specifier is preserved. And the disasembly is with the specifier with this patch. The GAS tests passed under our local tests. opcodes/ * aarch64-asm.c: Modify `sve_size_hsd` encoding. * aarch64-tbl.h (aarch64_opcode_table): Add QUALS's type OP_SVE_Vv_HSD for decp, incp, sqdecp, sqincp, uqdecp and uqincp. gas/ * testsuite/gas/aarch64/sve-movprfx_23.s: Update movprfx_23 testcase's test_sametwo macro, where take the predicate size specifier. * testsuite/gas/aarch64/sve-movprfx_23.d: Update movprfx_23 testcase's expected disassembly. * testsuite/gas/aarch64/sve-movprfx_23.l: Update movprfx_23 testcase's expected assembler messages. * testsuite/gas/aarch64/sve.s: Add sve testcase's instructions for decp, incp, sqdecp, sqincp, uqdecp and uqincp, which take the predicate size specifier. * testsuite/gas/aarch64/sve.d: Update sve testcase's expected disassembly. Signed-off-by: CaiJingtao <caijingtao@huawei.com>
2022-10-17aarch64: Tweak handling of F_STRICTRichard Sandiford1-17/+8
Current F_STRICT qualifier checking is enforced after the fact rather than as part of the match. This makes it impossible to have, e.g.: QLF2(S_D, S_D) QLF2(S_D, NIL) in the same list. opcodes/ * aarch64-opc.c (aarch64_find_best_match): Handle F_STRICT here rather than... (match_operands_qualifier): ...here.
2022-10-17x86: properly decode EVEX.W for AVX512_4{FMAPS,VNNIW} insnsJan Beulich1-6/+6
These require EVEX.W=0. Use %XS to facilitate the checking, even if for the AVX512_4VNNIW ones this is kind of an abuse (as 's' there stands for "signed", not "single"). While there also correct the 3rd operand for the AVX512_4VNNIW entries: Only the memory form is allowed (just like for AVX512_4FMAPS, where the correct type is already in use).
2022-10-17x86: fold AVX512-VNNI disassembler entries with AVX-VNNI onesJan Beulich3-15/+22
Make %XV also print the separating blank in the VEX case, while making it do nothing for EVEX-encoded insns. This way the AVX-VNNI entries can be re-used for AVX512-VNNI, at the same time fixing the lack of EVEX.W decoding. For the AVX-VNNI ones further make sure only VEX.66 forms are actually decoded.
2022-10-16PowerPC se_rfmci and VLE, SPE2 and LSP insns with -manyAlan Modra2-1/+9
I noticed recently that se_rfmci, a VLE mode instruction, was being accepted by non-VLE cpus, and also that se_rfmci by itself in a section did not cause SHF_PPC_VLE to be set. ie. both testcases added by this patch fail without the changes to tc-ppc.c here. Also, VLE, SPE2 and LSP insns were not accepted by the assembler with -many nor were SPE2 and LSP being disassembled with -Many. gas/ * config/tc-ppc.c (ppc_setup_opcodes): Wrap long lines. Add vle_opcodes when PPC_OPCODE_VLE or PPC_OPCODE_ANY. Simplify disassembler index segment checks. Add LSP and SPE2 opcodes when PPC_OPCODE_ANY too. (md_assemble): Correct logic adding PPC_APUINFO_VLE and SHF_PPC_VLE. * testsuite/gas/ppc/se_rfmci.s * testsuite/gas/ppc/se_rfmci.d, * testsuite/gas/ppc/se_rfmci_bad.d: New tests. * testsuite/gas/ppc/ppc.exp: Run them. opcodes/ * ppc-dis.c (print_insn_powerpc): Disassemble SPE2 and LSP insn when -Many. * ppc-opc.c (vle_opcodes <se_rfmci>): Comment.
2022-10-14PowerPC SPE disassembly and testsAlan Modra1-2/+2
Where sub and subf forms of an instruction exist we generally disassemble to the extended insn sub form rather than the underlying machine subf instruction. Do so for SPE evsubw and evsubiw too. spe_ambiguous.d always was a bit too optimistic. There is no sensible way to disassemble identical bytes back to different and original source. Instead change the test to check -Mraw results. gas/ * testsuite/gas/ppc/ppc.exp: Run spe_ambiguous test. * testsuite/gas/ppc/spe.d: Expect evsubw and evsubiw rather than evsubfw and evsubifw. * testsuite/gas/ppc/spe_ambiguous.s: Test evnor form equivalent to evnot. * testsuite/gas/ppc/spe_ambiguous.d: Test Mraw. opcodes/ * ppc-opc.c (powerpc_opcodes): Move evsubw before evsubfw and evsubiw before evsubifw and mark EXT.
2022-10-14e200 LSP supportAlan Modra2-337/+411
It has bothered me for a long time that we have disabled LSP (and SPE) tests. Also the LSP test comment indicating there is something wrong with get_powerpc_dialect. I don't think there is. Decoding of a VLE instruction depends on whether the processor is in VLE mode (some processors support both VLE and standard PPC) which we flag per section with SHF_PPC_VLE for decoding when disassembling. Background: Some versions of powerpc e200 have "Lightweight Signal Processing" support, examples being e200z215 and e200z425. As far as I can tell, LSP and SPE are mutually exclusive. This seems to be borne out by insn encoding, for example LSP "zvaddih" and SPE "evaddw" have the same encoding. So none of the processor descriptions in ppc_opts ought to have both PPC_OPCODE_LSP and PPC_OPCODE_SPE/2, if we want disassembly to work. I also could not find anything to suggest that the LSP insns are enabled only in VLE mode, which means the LSP insns should not be in vle_opcodes. Fix all this by moving the LSP insns to their own table, and add a new e200z2 cpu entry with LSP support, removing LSP from -me200z4 and from -mvle. (Yes, I know, as I said above some of the e200z4 processors have LSP. Others have SPE. It's hard to choose good options. Think of z2 as meaning earlier, z4 as later.) Also add -mlsp to allow adding the LSP insn set. include/ * opcode/ppc.h (lsp_opcodes, lsp_num_opcodes): Declare. (LSP_OP_TO_SEG): Define. binutils/ * doc/binutils.texi: Update ppc docs. gas/ * config/tc-ppc.c (ppc_setup_opcodes): Add lsp opcodes to ppc_hash. * doc/c-ppc.texi: Document e200 and lsp. * testsuite/gas/ppc/lsp-checks.d: Assemble with -me200z2. * testsuite/gas/ppc/lsp.d: Likewise, disassembly too. * testsuite/gas/ppc/ppc.exp: Don't xfail lsp test. opcodes/ * ppc-dis.c (ppc_opts): Add e200z2 and lsp. Don't set PPC_OPCODE_LSP for e200z4 or vle. (ppc_parse_cpu): Mutually exclude LSP and SPE. (LSP_OPCD_SEGS): Define. (lsp_opcd_indices): New array. (disassemble_init_powerpc): Init lsp_opcd_indices. (lookup_lsp): New function. (print_insn_powerpc): Call it. * ppc-opc.c: Include libiberty.h for ARRAY_SIZE and use throughout. (vle_opcodes): Move LSP opcodes to.. (lsp_opcodes): ..here, and sort. (lsp_num_opcodes): New.
2022-10-14opcodes/riscv-dis.c: Remove last_map_stateTsukasa OI1-3/+0
Before changing the core disassembler, we take care of minor code clarity issues and improve readability. This commit removes unused variable last_map_state (set by the print_insn_riscv function but not read anywhere else). opcodes/ChangeLog: * riscv-dis.c (last_map_state): Remove. (print_insn_riscv): Remove setting last_map_state.
2022-10-14opcodes/riscv-dis.c: Make XLEN variable staticTsukasa OI1-1/+1
Before changing the core disassembler, we take care of minor code clarity issues and improve readability. Since xlen variable is not (and should not) used outside riscv-dis.c, this commit makes this variable static. opcodes/ChangeLog: * riscv-dis.c (xlen): Make this variable static.
2022-10-14opcodes/riscv-dis.c: Use bool type whenever possibleTsukasa OI1-5/+5
Before changing the core disassembler, we take care of minor code clarity issues and improve readability. This commit replaces uses of int with bool whenever possible. opcodes/ChangeLog: * riscv-dis.c (no_aliases) Change type to bool. (set_default_riscv_dis_options): Use boolean. (parse_riscv_dis_option_without_args): Likewise. (riscv_disassemble_insn): Use boolean keywords.
2022-10-14opcodes/riscv-dis.c: Tidying with spacingTsukasa OI1-1/+1
Before changing the core disassembler, we take care of minor code clarity issues and improve readability. This commit takes care of improper spacing for code clarity. opcodes/ChangeLog: * riscv-dis.c (riscv_disassemble_insn): Tidying with spacing.
2022-10-14opcodes/riscv-dis.c: Tidying with comments/clarityTsukasa OI1-4/+21
Before changing the core disassembler, we take care of minor code clarity issues and improve readability. First, we need to clarify the roles of variables and code portions. opcodes/ChangeLog: * riscv-dis.c (xlen): Move before default_isa_spec. Add comment. (default_isa_spec, default_priv_spec): Add comment. (riscv_gpr_names, riscv_fpr_names): Likewise. (parse_riscv_dis_option_without_args): Likewise. (parse_riscv_dis_option, parse_riscv_dis_options): Likewise. (maybe_print_address): Likewise. (riscv_disassemble_insn): Fix comment about the Zfinx "extension". Add comment about the riscv_multi_subset_supports call.
2022-10-14RISC-V: Move standard hints before all instructionsTsukasa OI1-4/+8
Because all standard hints must be placed before corresponding instruction for the disassembler, they may taint basic RVI instruction section. This commit moves all standard hints before all basic RVI instructions to improve maintainability. opcodes/ChangeLog: * riscv-opc.c (riscv_opcodes): Move all standard hints before all standard instructions.
2022-10-14RISC-V: Move certain arrays to riscv-opc.cTsukasa OI1-0/+13
This is a part of small tidying (declare tables in riscv-opc.c). include/ChangeLog: * opcode/riscv.h (riscv_rm, riscv_pred_succ): Move declarations to opcodes/riscv-opc.c. New non-static definitions. opcodes/ChangeLog: * riscv-opc.c (riscv_rm, riscv_pred_succ): Move from include/opcode/riscv.h. Add description.
2022-10-06RISC-V: Print XTheadMemPair literal as "immediate"Tsukasa OI1-1/+1
The operand type "Xl(...)" denotes that (...) is a literal. Specifically, they are intended to be a constant immediate value. This commit prints "Xl(...)" operand with dis_style_immediate style, not dis_style_text. opcodes/ChangeLog: * riscv-dis.c (print_insn_args): Use dis_style_immediate on the constant literal of the "Xl..." operand.
2022-10-06RISC-V: Fix T-Head immediate types on printingTsukasa OI1-4/+4
This commit fixes two minor typing-related issues for T-Head immediate operands. 1. A signed type must be specified when printing with %i. 2. unsigned/signed int is not portable enough for max 32-bit immediates. Instead, we should use unsigned/signed long. The format string is changed accordingly. opcodes/ChangeLog: * riscv-dis.c (print_insn_args): Fix T-Head immediate types on printing.
2022-10-06RISC-V: Print comma and tabs as the "text" styleTsukasa OI1-11/+20
On the RISC-V disassembler, some separators have non-text style when printed with another word with another style. This commit splits those, making sure that those comma and tabs are printed with the "text" style. opcodes/ChangeLog: * riscv-dis.c (print_insn_args): Split and print the comma as text. (riscv_disassemble_insn): Split and print tabs as text. (riscv_disassemble_data): Likewise.
2022-10-06RISC-V: Optimize riscv_disassemble_data printfTsukasa OI1-6/+4
This commit makes types of printf arguments on riscv_disassemble_data as small as possible (as long as we can preserve the portability) to reduce the cost of printf (especially on 32-bit host). opcodes/ChangeLog: * riscv-dis.c (riscv_disassemble_data): Use smallest possible type to printing data.
2022-10-06RISC-V: Fix printf argument types corresponding %xTsukasa OI1-7/+7
"%x" format specifier requires unsigned type, not int. This commit fixes this issue on the RISC-V disassembler. opcodes/ChangeLog: * riscv-dis.c (print_insn_args): Fix printf argument types where the format specifier is "%x".
2022-10-06RISC-V: Fix immediates to have "immediate" styleTsukasa OI1-5/+5
This commit fixes certain print calls on immediate operands to have dis_style_immediate. opcodes/ChangeLog: * riscv-dis.c (print_insn_args): Fix immediates to have "immediate" style. (riscv_disassemble_data): Likewise.
2022-10-05Arm64: support CLEARBHB aliasJan Beulich4-1576/+1579
While the Arm v8 ARM (rev I-a) still doesn't mention this alias, it is (typically via a macro) already in use in kernels and alike.
2022-10-04RISC-V: Fix buffer overflow on print_insn_riscvTsukasa OI1-1/+1
Because riscv_insn_length started to support instructions up to 176-bit, we need to increase packet buffer size to 176-bit in size. include/ChangeLog: * opcode/riscv.h (RISCV_MAX_INSN_LEN): Max instruction length for use in buffer size. opcodes/ChangeLog: * riscv-dis.c (print_insn_riscv): Increase buffer size for max 176-bit length instructions.
2022-10-04RISC-V: Renamed INSN_CLASS for floating point in integer extensions.Nelson Chu1-222/+222
Just added suffix _INX for those INSN_CLASS should be enough to represent their fpr can be replaced by gpr.
2022-10-04opcodes/riscv: style csr names as registersAndrew Burgess1-1/+2
While reviewing another patch I noticed that RISC-V CSR names are given the text style, not the register style. This patch fixes this mistake.
2022-10-03RISC-V: Move supervisor instructions after all unprivileged onesTsukasa OI1-32/+32
This location of supervisor instructions is out of place (because many other privileged instructions are located at the tail but after the supervisor instructions, we have many unprivileged instructions including bit manipulation / crypto / vector instructions). Not only that, this is harmful to implement pseudoinstructions in the latest 'P'-extension proposal (CLROV and RDOV). This commit moves supervisor instructions after all unprivileged instructions. opcodes/ChangeLog: * riscv-opc.c (riscv_opcodes): Adjust indents. Move supervisor instructions after all unprivileged instructions.
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