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2021-05-25Regen cris filesAlan Modra5-30/+67
* cris-desc.c: Regenerate. * cris-desc.h: Regenerate. * cris-opc.h: Regenerate. * po/POTFILES.in: Regenerate.
2021-05-24opcodes: cris: move desc & opc files from sim/Mike Frysinger9-4/+3403
All other cgen ports keep their generated desc & opc files under opcodes/, so move the cris files over too. The cris-opc.c file, while not generated, is already here to complement.
2021-05-18RISC-V: PR27814, Objdump crashes when disassembling a non-ELF RISC-V binary.Job Noorman2-10/+20
2021-05-18 Job Noorman <mtvec@pm.me> opcodes/ PR 27814 * riscv-dis.c (riscv_get_disassembler): Get elf attributes only for the elf objects.
2021-05-17arm: Fix bugs with MVE vmov from two GPRs to vector lanesAlex Coplan2-2/+14
The initial problem I wanted to fix here is that GAS was rejecting MVE instructions such as: vmov q3[2], q3[0], r2, r2 with: Error: General purpose registers may not be the same -- `vmov q3[2],q3[0],r2,r2' which is incorrect; such instructions are valid. Note that for moves in the other direction, e.g.: vmov r2, r2, q3[2], q3[0] GAS is correct in rejecting this as it does not make sense to move both lanes into the same register (the Arm ARM says this is CONSTRAINED UNPREDICTABLE). After fixing this issue, I added assembly/disassembly tests for these vmovs. This revealed several disassembly issues, including incorrectly marking the moves into vector lanes as UNPREDICTABLE, and disassembling many of the vmovs as vector loads. These are now fixed. gas/ChangeLog: * config/tc-arm.c (do_mve_mov): Only reject vmov if we're moving into the same GPR twice. * testsuite/gas/arm/mve-vmov-bad-2.l: Tweak error message. * testsuite/gas/arm/mve-vmov-3.d: New test. * testsuite/gas/arm/mve-vmov-3.s: New test. opcodes/ChangeLog: * arm-dis.c (mve_opcodes): Fix disassembly of MVE_VMOV2_GP_TO_VEC_LANE when idx == 1. (is_mve_encoding_conflict): MVE vector loads should not match when P = W = 0. (is_mve_unpredictable): It's not unpredictable to use the same source register twice (for MVE_VMOV2_GP_TO_VEC_LANE).
2021-05-11Fix an illegal memory access when attempting to disassemble a corrupt TIC30 ↵Nick Clifton2-0/+9
binary. PR 27840 * tic30-dis.c (print_insn_tic30): Prevent attempts to read beyond the end of the code buffer.
2021-05-06or1k: Implement relocation R_OR1K_GOT_AHI16 for gotha()Stafford Horne2-1/+11
The gotha() relocation mnemonic will be outputted by OpenRISC GCC when using the -mcmodel=large option. This relocation is used along with got() to generate 32-bit GOT offsets. This increases the previous GOT offset limit from the previous 16-bit (64K) limit. This is needed on large binaries where the GOT grows larger than 64k. bfd/ChangeLog: PR 21464 * bfd-in2.h: Add BFD_RELOC_OR1K_GOT_AHI16 relocation. * elf32-or1k.c (or1k_elf_howto_table, or1k_reloc_map): Likewise. (or1k_final_link_relocate, or1k_elf_relocate_section, or1k_elf_check_relocs): Likewise. * libbfd.h (bfd_reloc_code_real_names): Likewise. * reloc.c: Likewise. cpu/ChangeLog: PR 21464 * or1k.opc (or1k_imm16_relocs, parse_reloc): Define parse logic for gotha() relocation. include/ChangeLog: PR 21464 * elf/or1k.h (elf_or1k_reloc_type): Define R_OR1K_GOT_AHI16 number. opcodes/ChangeLog: PR 21464 * or1k-asm.c: Regenerate. gas/ChangeLog: PR 21464 * testsuite/gas/or1k/reloc-1.s: Add test for new relocation. * testsuite/gas/or1k/reloc-1.d: Add test result for new relocation. Cc: Giulio Benetti <giulio.benetti@benettiengineering.com> fixup reloc, add tests
2021-05-01opcodes: xtensa: support branch visualizationMax Filippov2-0/+15
2021-05-01 Max Filippov <jcmvbkbc@gmail.com> opcodes/ * xtensa-dis.c (print_insn_xtensa): Fill in info->insn_type and info->insn_info_valid.
2021-04-26x86: optimize LEAJan Beulich3-2/+7
Over the years I've seen a number of instances where people used lea (%reg1), %reg2 or lea symbol, %reg despite the same thing being expressable via MOV. Since additionally LEA often has restrictions towards the ports it can be issued to, while MOV typically gets dealt with simply by register renaming, transform to MOV when possible (without growing opcode size and without altering involved relocation types). Note that for Mach-O the new 64-bit testcases would fail (for BFD_RELOC_X86_64_32S not having a representation), and hence get skipped there.
2021-04-23opcodes: xtensa: display loaded literal valueMax Filippov2-1/+24
Display literal value loaded with l32r opcode as a part of disassembly. This significantly simplifies reading of disassembly output. 2020-04-23 Max Filippov <jcmvbkbc@gmail.com> opcodes/ * xtensa-dis.c (print_xtensa_operand): For PC-relative operand of l32r fetch and display referenced literal value.
2021-04-23opcodes: xtensa: improve literal outputMax Filippov2-0/+6
Output literals as 4-byte words, not as separate bytes. 2021-04-23 Max Filippov <jcmvbkbc@gmail.com> opcodes/ * xtensa-dis.c (print_insn_xtensa): Set info->bytes_per_chunk to 4 for literal disassembly.
2021-04-19aarch64: New instructions for maintenance of GPT entries cached in a TLBPrzemyslaw Wirkus2-0/+10
This patch adds support to four new system registers (RPAOS, RPALOS, PAALLOS, PAALL) in conjunction with TLBI instruction. This change is part of RME (Realm Management Extension). gas/ChangeLog: 2021-04-19 Przemyslaw Wirkus <przemyslaw.wirkus@arm.com> * NEWS: Update news. * testsuite/gas/aarch64/rme.d: Update test. * testsuite/gas/aarch64/rme.s: Update test. opcodes/ChangeLog: 2021-04-19 Przemyslaw Wirkus <przemyslaw.wirkus@arm.com> * aarch64-opc.c: Add new registers (RPAOS, RPALOS, PAALLOS, PAALL) support for TLBI instruction.
2021-04-19aarch64: Add new data cache maintenance operationsPrzemyslaw Wirkus2-0/+7
This patch adds support to two new system registers (CIPAPA, CIGDPAPA) in conjunction with DC instruction. This change is part of RME (Realm Management Extension). gas/ChangeLog: 2021-04-19 Przemyslaw Wirkus <przemyslaw.wirkus@arm.com> * testsuite/gas/aarch64/rme.d: Update test. * testsuite/gas/aarch64/rme.s: Update test. opcodes/ChangeLog: 2021-04-19 Przemyslaw Wirkus <przemyslaw.wirkus@arm.com> * aarch64-opc.c: Add new register (CIPAPA, CIGDPAPA) support for DC instruction.
2021-04-19arm64: add two initializersJan Beulich2-2/+8
Old enough gcc can't cope and would warn about the variables potentially remaining uninitialized.
2021-04-16aarch64: Define RME system registersPrzemyslaw Wirkus2-0/+8
This patch introduces RME (Realm Management Extension) system registers. gas/ChangeLog: 2021-03-01 Przemyslaw Wirkus <przemyslaw.wirkus@arm.com> * testsuite/gas/aarch64/rme-invalid.d: New test. * testsuite/gas/aarch64/rme-invalid.l: New test. * testsuite/gas/aarch64/rme-invalid.s: New test. * testsuite/gas/aarch64/rme.d: New test. * testsuite/gas/aarch64/rme.s: New test. opcodes/ChangeLog: 2021-03-01 Przemyslaw Wirkus <przemyslaw.wirkus@arm.com> * aarch64-opc.c: Add RME system registers.
2021-04-16Update the ChangeLog, and add the missing entries.Nelson Chu1-0/+5
2021-04-16RISC-V: compress "addi d,CV,z" to "c.mv d,CV"Lifang Xia1-0/+1
PR 27732 gas/ * testsuite/gas/riscv/c-zero-imm.d: Compress addi a4,a4,0 to c.mv a4,a4. * testsuite/gas/riscv/c-zero-imm.s: Likewise. opcodes/ * riscv-opc.c (riscv_opcodes): New insn alias for addi. Compress "addi d,CV,z" to "c.mv d,CV".
2021-04-13ENABLE_CHECKING in bfd, opcodes, binutils, ldAlan Modra4-2/+42
gas already has this. Here it enables checking hash table type passed to elf_link_hash_lookup and elf_link_hash_traverse. bfd/ * elf-bfd.h (ENABLE_CHECKING): Define. (elf_link_hash_lookup): Abort if wrong type of hash table. (elf_link_hash_traverse): Likewise. * configure.ac (--enable-checking): Add support. * config.in: Regenerate. * configure: Regenerate. binutils/ * configure.ac (--enable-checking): Add support. * config.in: Regenerate. * configure: Regenerate. ld/ * configure.ac (--enable-checking): Add support. * config.in: Regenerate. * configure: Regenerate. opcodes/ * configure.ac (--enable-checking): Add support. * config.in: Regenerate. * configure: Regenerate.
2021-04-09AArch64: Fix Atomic LD64/ST64 classification.Tejas Belagod2-4/+9
Patch 1: Fix diagnostics for exclusive load/stores and reclassify Armv8.7-A ST/LD64 Atomics. Following upstream pointing out some inconsistencies in diagnostics, https://sourceware.org/pipermail/binutils/2021-February/115356.html attached is a patch set that fixes the issues. I believe a combination of two patches mainly contributed to these bugs: https://sourceware.org/pipermail/binutils/2020-November/113961.html https://sourceware.org/pipermail/binutils/2018-June/103322.html A summary of what this patch set fixes: For instructions STXR w0,x2,[x0] STLXR w0,x2,[x0] The warning we emit currently is misleading: Warning: unpredictable: identical transfer and status registers --`stlxr w0,x2,[x0]' Warning: unpredictable: identical transfer and status registers --`stxr w0,x2,[x0]' it ought to be: Warning: unpredictable: identical base and status registers --`stlxr w0,x2,[x0]' Warning: unpredictable: identical base and status registers --`stxr w0,x2,[x0]' For instructions: ldaxp x0,x0,[x0] ldxp x0,x0,[x0] The warning we emit is incorrect Warning: unpredictable: identical transfer and status registers --`ldaxp x0,x0,[x0]' Warning: unpredictable: identical transfer and status registers --`ldxp x0,x0,[x0]' it ought to be: Warning: unpredictable load of register pair -- `ldaxp x0,x0,[x0]' Warning: unpredictable load of register pair -- `ldxp x0,x0,[x0]' For instructions stlxp w0, x2, x2, [x0] stxp w0, x2, x2, [x0] We don't emit any warning when it ought to be: Warning: unpredictable: identical base and status registers --`stlxp w0,x2,x2,[x0]' Warning: unpredictable: identical base and status registers --`stxp w0,x2,x2,[x0]' For instructions: st64bv x0, x2, [x0] st64bv x2, x0, [x0] We incorrectly warn when its not necessary. This is because we classify them incorrectly as ldstexcl when it should be lse_atomics in the opcode table. The incorrect classification makes it pick up the warnings from warning on exclusive load/stores. Patch 2: Reclassify Armv8.7-A ST/LD64 Atomics. This patch reclassifies ST64B{V,V0}, LD64B as lse_atomics rather than ldstexcl according to their encoding class as specified in the architecture. This also has the fortunate side-effect of spurious unpredictable warnings getting eliminated. For eg. For instruction: st64bv x0, x2, [x0] We incorrectly warn when its not necessary: Warning: unpredictable: identical transfer and status registers --`st64bv x0,x2,[x0]' This is because we classify them incorrectly as ldstexcl when it should be lse_atomics in the opcode table. The incorrect classification makes it pick up the warnings from warning on exclusive load/stores. This patch fixes it by reclassifying it and no warnings are issued for this instruction. opcodes/ChangeLog: 2021-04-09 Tejas Belagod <tejas.belagod@arm.com> * aarch64-tbl.h (struct aarch64_opcode aarch64_opcode_table): Reclassify LD64/ST64 instructions to lse_atomic instead of ldstexcl.
2021-04-09PowerPC disassembly of pcrel referencesAlan Modra2-10/+143
This adds some annotation to Power10 pcrel instructions, displaying the target address (ie. pc + D34 field) plus a symbol if there is one at exactly that target address. pld from the .got or .plt will also look up the entry and display it, symbolically if there is a dynamic relocation on the entry. include/ * dis-asm.h (struct disassemble_info): Add dynrelbuf and dynrelcount. binutils/ * objdump.c (struct objdump_disasm_info): Delete dynrelbuf and dynrelcount. (find_symbol_for_address): Adjust for dynrelbuf and dynrelcount move. (disassemble_section, disassemble_data): Likewise. opcodes/ * ppc-dis.c (struct dis_private): Add "special". (POWERPC_DIALECT): Delete. Replace uses with.. (private_data): ..this. New inline function. (disassemble_init_powerpc): Init "special" names. (skip_optional_operands): Add is_pcrel arg, set when detecting R field of prefix instructions. (bsearch_reloc, print_got_plt): New functions. (print_insn_powerpc): For pcrel instructions, print target address and symbol if known, and decode plt and got loads too. gas/ * testsuite/gas/ppc/prefix-pcrel.d: Update expected output. * testsuite/gas/ppc/prefix-reloc.d: Likewise. * gas/testsuite/gas/ppc/vsx_32byte.d: Likewise. ld/ * testsuite/ld-powerpc/inlinepcrel-1.d: Update expected output. * testsuite/ld-powerpc/inlinepcrel-2.d: Likewise. * testsuite/ld-powerpc/notoc2.d: Likewise. * testsuite/ld-powerpc/notoc3.d: Likewise. * testsuite/ld-powerpc/pcrelopt.d: Likewise. * testsuite/ld-powerpc/startstop.d: Likewise. * testsuite/ld-powerpc/tlsget.d: Likewise. * testsuite/ld-powerpc/tlsget2.d: Likewise. * testsuite/ld-powerpc/tlsld.d: Likewise. * testsuite/ld-powerpc/weak1.d: Likewise. * testsuite/ld-powerpc/weak1so.d: Likewise.
2021-04-08PR27684, PowerPC missing mfsprg0 and othersAlan Modra2-4/+10
PR 27684 * ppc-opc.c (powerpc_opcodes): Correct usprg typos, add mfpir.
2021-04-08PR27676, PowerPC missing extended dcbt, dcbtst mnemonicsAlan Modra2-7/+90
Note that this doesn't implement the ISA to the letter regarding dcbtds (and dcbtstds), which says that the TH field may be zero. That doesn't make sense because allowing TH=0 would mean you no long have a dcbtds but rather a dcbtct instruction. I'm interpreting the ISA wording about allowing TH=0 to mean that the TH field of dcbtds is optional (in which case the TH value is 0b1000). opcodes/ PR 27676 * ppc-opc.c (DCBT_EO): Move earlier. (insert_thct, extract_thct, insert_thds, extract_thds): New functions. (powerpc_operands): Add THCT and THDS entries. (powerpc_opcodes): Add dcbtstct, dcbtstds, dcbna, dcbtct, dcbtds. gas/ * testsuite/gas/ppc/pr27676.d, * testsuite/gas/ppc/pr27676.s: New test. * testsuite/gas/ppc/ppc.exp: Run it. * testsuite/gas/ppc/dcbt.d: Update. * testsuite/gas/ppc/power4_32.d: Update.
2021-04-06Return symbol from symbol_at_address_funcAlan Modra3-23/+14
include/ * dis-asm.h (struct disassemble_info <symbol_at_address_func>): Return asymbol*. binutils/ * objdump.c (objdump_symbol_at_address): Return asymbol*. opcodes/ * dis-buf.c (generic_symbol_at_address): Return symbol* NULL. * s12z-dis.c (decode_possible_symbol): Use symbol returned from symbol_at_address_func.
2021-04-05C99 opcodes configuryAlan Modra8-1248/+528
* configure.ac: Don't check for limits.h, string.h, strings.h or stdlib.h. (AC_ISC_POSIX): Don't invoke. * sysdep.h: Include stdlib.h and string.h unconditionally. * i386-opc.h: Include limits.h unconditionally. * wasm32-dis.c: Likewise. * cgen-opc.c: Don't include alloca-conf.h. * config.in: Regenerate. * configure: Regenerate.
2021-04-01Remove strneq macro and use startswith.Martin Liska5-18/+9
bfd/ChangeLog: * ecoff.c (strneq): Remove strneq and use startswith. (_bfd_ecoff_slurp_armap): Likewise. binutils/ChangeLog: * elfcomm.h (strneq): Remove strneq and use startswith. * readelf.c (ia64_process_unwind): Likewise. (process_note): Likewise. gas/ChangeLog: * config/obj-coff.c (strneq): Remove strneq and use startswith. (weak_is_altname): Likewise. (obj_coff_section): Likewise. * config/tc-cr16.c (process_label_constant): Likewise. * config/tc-crx.c (strneq): Likewise. include/ChangeLog: * opcode/cr16.h (strneq): Remove strneq and use startswith. ld/ChangeLog: * ldbuildid.c (strneq): Remove strneq and use startswith. (validate_build_id_style): Likewise. (compute_build_id_size): Likewise. opcodes/ChangeLog: * arm-dis.c (strneq): Remove strneq and use startswith. * cr16-dis.c (print_insn_cr16): Likewise. * score-dis.c (streq): Likewise. (strneq): Likewise. * score7-dis.c (strneq): Likewise.
2021-04-01PR27675, PowerPC missing extended mnemonic mfummcr2Alan Modra2-0/+7
PR 27675 * ppc-opc.c (powerpc_opcodes): Add mfummcr2 and mfmmcr2.
2021-03-31Use bool in opcodesAlan Modra49-1573/+1591
cpu/ * frv.opc: Replace bfd_boolean with bool, FALSE with false, and TRUE with true throughout. opcodes/ * sysdep.h (POISON_BFD_BOOLEAN): Define. * aarch64-asm-2.c, * aarch64-asm.c, * aarch64-asm.h, * aarch64-dis-2.c, * aarch64-dis.c, * aarch64-dis.h, * aarch64-gen.c, * aarch64-opc.c, * aarch64-opc.h, * arc-dis.c, * arc-dis.h, * arc-fxi.h, * arc-opc.c, * arm-dis.c, * bfin-dis.c, * cris-dis.c, * csky-dis.c, * csky-opc.h, * dis-buf.c, * disassemble.c, * frv-opc.c, * frv-opc.h, * h8300-dis.c, * i386-dis.c, * m68k-dis.c, * metag-dis.c, * microblaze-dis.c, * microblaze-dis.h, * micromips-opc.c, * mips-dis.c, * mips-formats.h, * mips-opc.c, * mips16-opc.c, * mmix-dis.c, * msp430-dis.c, * nds32-dis.c, * nfp-dis.c, * nios2-dis.c, * ppc-dis.c, * riscv-dis.c, * score-dis.c, * score7-dis.c, * tic6x-dis.c, * v850-dis.c, * vax-dis.c, * wasm32-dis.c, * xtensa-dis.c: Replace bfd_boolean with bool, FALSE with false, and TRUE with true throughout.
2021-03-31Remove bfd_stdint.hAlan Modra12-11/+25
If we require C99 for binutils then stdint.h is available. bfd/ * .gitignore: Delete bfd_stdint.h entry. * Makefile.am (bfdinclude_HEADERS): Delete bfd_stdint.h. (BUILD_HFILES, LOCAL_H_DEPS): Likewise. * bfd-in.h: Include stdint.h in place of bfd_stdint.h. * configure.ac: Don't invoke GCC_HEADER_STDINT. * configure.com: Don't create bfd_stdint.h. * Makefile.in: Regenerate. * aclocal.m4: Regenerate. * bfd-in2.h: Regenerate. * config.in: Regenerate. * configure: Regenerate. * doc/Makefile.in: Regenerate. * po/BLD-POTFILES.in: Regenerate. binutils/ * coffdump.c: Include stdint.h in place of bfd_stdint.h. * dwarf.c: Likewise. gas/ * config/tc-aarch64.c: Include stdint.h in place of bfd_stdint.h. * config/tc-crx.c: Likewise. * config/tc-nds32.h: Likewise. include/ * cgen/basic-modes.h: Include stdint.h in place of bfd_stdint.h. * elf/nfp.h: Likewise. * opcode/aarch64.h: Likewise. * opcode/cgen.h: Likewise. * opcode/nfp.h: Likewise. * opcode/ppc.h: Likewise. ld/ * elf-hints-local.h: Include stdint.h in place of bfd_stdint.h. * emultempl/nds32elf.em: Likewise. * testsuite/ld-elf/mbind2b.c: Likewise. * testsuite/ld-elf/pr18718.c: Likewise. * testsuite/ld-elf/pr18720a.c: Likewise. * testsuite/ld-elf/pr25749-1.c: Likewise. * testsuite/ld-elf/pr25749-1a.c: Likewise. * testsuite/ld-elf/pr25749-1b.c: Likewise. * testsuite/ld-elf/pr25749-1c.c: Likewise. * testsuite/ld-elf/pr25749-1d.c: Likewise. * testsuite/ld-elf/pr25749-2.c: Likewise. * testsuite/ld-elf/pr25754-1a.c: Likewise. * testsuite/ld-elf/pr25754-2a.c: Likewise. * testsuite/ld-elf/pr25754-3a.c: Likewise. * testsuite/ld-elf/pr25754-4a.c: Likewise. * testsuite/ld-elf/pr25754-5a.c: Likewise. * testsuite/ld-elf/pr25754-6a.c: Likewise. opcodes/ * aarch64-dis.c: Include stdint.h in place of bfd_stdint.h. * aarch64-dis.h: Likewise. * aarch64-opc.c: Likewise. * avr-dis.c: Likewise. * csky-dis.c: Likewise. * nds32-asm.c: Likewise. * nds32-dis.c: Likewise. * nfp-dis.c: Likewise. * riscv-dis.c: Likewise. * s12z-dis.c: Likewise. * wasm32-dis.c: Likewise.
2021-03-30x86: drop seg_entryJan Beulich3-21/+17
Use struct reg_entry instead for most purposes, with a separate array holding just the respective opcode prefix bytes.
2021-03-30x86: drop REGNAM_{AL,AX,EAX}Jan Beulich2-5/+4
The former two are unused anyway. And having such constants isn't very helpful either, when they live in a place where updating the register table wouldn't even allow noticing the need to adjust these constants.
2021-03-30x86: adjust st(<N>) parsingJan Beulich4-12/+13
st(1) ... st(7) will never be looked up in the hash table, so there's no point inserting the entries. It's also not really necessary to do a 2nd hash lookup after parsing the register number, nor is there a real reason for having both st and st(0) entries. Plus we can easily do away with the need for st to be first in the table.
2021-03-29x86: move some opcode table entriesJan Beulich3-489/+500
For a long time there hasn't been a need anymore to keep together all templates with identical mnemonics. Move the MOVQ and MOVABS ones next to their MOV counterparts. Move the string forms of CMPSD and MOVSD next to their CMPS / MOVS counterparts. Re-arrange what so fgar was the SSE3 section. This makes reasonably obvious that MONITOR/MWAIT aren't suitable to cover by CpuSSE3, but adjusting this is left for another time.
2021-03-29x86: VPSADBW's source operands are also commutativeJan Beulich3-6/+12
In commit 79dec6b7baa2 ("x86-64: optimize certain commutative VEX-encoded insns") I missed the fact that there being subtraction involved here doesn't matter, as absolute differences get summed up.
2021-03-29x86: fold SSE2AVX and their base MMX/SSE templatesJan Beulich4-924/+645
This way not only the overall (source) table size shrinks by quite a bit and the risk of related templates going out of sync with one another gets lowered, but also (dis)similarities between neighboring templates become easier to spot. Note that for certain SSE2AVX templates this results in benign attribute changes: - LDMXCSR and STMXCSR: NoAVX gets set, - MOVMSKPS, PMOVMSKB, PEXTR{B,W} (register destination), and PINSR{B,W} (register source): IgnoreSize and NoRex64 get set, - CVT{DQ,PS}2PD, CVTSD2SS, MOVMSKPD, MOVDDUP, PMOV{S,Z}X{BW,WD,DQ}, and ROUNDSD: NoRex64 gets set, - CVTSS2SD, INSERTPS, PEXTRW (memory destination), PINSRW (memory source), and PMOV{S,Z}X{BD,WQ,BQ}: IgnoreSize gets set. Similarly the "normal" (non-SSE2AVX) - non-64-bit CVTS{I,S}2SD forms get NoRex64 set, - CMP{EQ,ORD,NEQ,UNORD}{P,S}{S,D} forms get C set, all again in a benign way. The remaining differences in the generated table are due to re-ordering of entries in the course of being folded into templates.
2021-03-29x86: undo Prefix_0X<nn> use in opcode tableJan Beulich3-375/+383
The table entries are more natural to read (and slightly shorter) when the prefixes, like is the case for VEX/XOP/EVEX-encoded entries, are specified as part of the opcode. This is particularly noticable for side-by-side legacy and SSE2AVX entries. An implication is that we now need to use "unsigned long long" for the initially parsed opcode in i386-gen. I don't expect this to be an issue.
2021-03-29x86: shrink some struct insn_template fieldsJan Beulich2-4/+10
Now that all base opcodes are only at most 2 bytes in size, shrink its template field to just as much. By also shrinking extension_opcode and operands to just what they really need, we can free up an entire 32-bit slot (plus 4 left bits past the bitfields themselves). At present this alters sizeof(struct insn_template) only for 32-bit builds. In 64-bit builds it instead leaves a padding hole that will allow to buffer future growth of other fields (opcode_modifier, cpu_flags, operand_types[]).
2021-03-29x86: derive opcode encoding space attribute from base opcodeJan Beulich3-1601/+1641
Just like is already done for VEX/XOP/EVEX encoded insns, record the encoding space information in the respective opcode modifier field. Do this again without changing the source table, but rather by deriving the values from their existing source representation.
2021-03-29TRUE/FALSE simplificationAlan Modra5-54/+68
There is really no need to write code like "foo != 0 ? TRUE : FALSE" unless we had stupidly defined FALSE as something other than 0 or TRUE as something other than 1. The simpler "foo != 0" does just as well. Similarly "(condition == TRUE)" or "(condition == FALSE) can be simplified to "(condition)" and "(!condition)" respectively. I'll note that there is reason to use "integer_expression != 0" when assigning a bfd_boolean rather than the simpler "integer_expression", if you expect the variable to have 0 or 1 value. It's probably even a good idea to not rely on implicit conversion if bfd_boolean were _Bool. bfd/ * aoutx.h (aout_link_write_symbols): Don't cast boolean expression to bfd_boolean. * elf32-or1k.c (or1k_set_got_and_rela_sizes): Dont compare booleans against FALSE. * elf32-arc.c (name_for_global_symbol): Don't compare boolean to TRUE. (is_reloc_PC_relative): Don't use "boolean_condition ? TRUE : FALSE". (is_reloc_SDA_relative, is_reloc_for_GOT): Likewise. (is_reloc_for_PLT, is_reloc_for_TLS): Likewise. * elf32-arm.c (stm32l4xx_need_create_replacing_stub): Likewise. * elf32-nds32.c (insert_nds32_elf_blank): Likewise. * elf32-rx.c (rx_set_section_contents): Likewise. * elfnn-aarch64.c (elfNN_aarch64_final_link_relocate): Likewise. * elfxx-mips.c (_bfd_mips_elf_ignore_undef_symbol): Likewise. * mach-o.c (bfd_mach_o_read_command): Likewise. * targets.c (bfd_get_target_info): Likewise. binutils/ * dlltool.c (main): Don't use "boolean_condition ? TRUE : FALSE". * dwarf.c (read_and_display_attr_value): Likewise. (display_debug_str_offsets): Likewise. * objdump.c (dump_bfd): Likewise. * readelf.c (dump_section_as_strings): Likewise. (dump_section_as_bytes): Likewise. gas/ * atof-generic.c (FALSE, TRUE): Don't define. * config/obj-elf.h (FALSE, TRUE): Don't define. * config/obj-som.h (FALSE, TRUE): Don't define. * config/tc-hppa.h (FALSE, TRUE): Don't define. * config/tc-pdp11.c (FALSE, TRUE): Don't define. * config/tc-iq2000.h (obj_fix_adjustable): Delete. * config/tc-m32r.h (TC_FIX_ADJUSTABLE): Delete. * config/tc-mt.h (obj_fix_adjustable): Delete. * config/tc-nds32.h (TC_FIX_ADJUSTABLE): Delete. * config/tc-arc.c (parse_opcode_flags): Simplify boolean expression. (relaxable_flag, relaxable_operand, assemble_insn): Likewise. (tokenize_extregister): Likewise. * config/tc-csky.c (parse_opcode, get_operand_value): Likewise. (parse_operands_op, parse_operands, md_assemble): Likewise. * config/tc-d10v.c (build_insn): Likewise. * config/tc-score.c (s3_gen_insn_frag): Likewise. * config/tc-score7.c (s7_gen_insn_frag, s7_relax_frag): Likewise. * config/tc-tic6x.c (tic6x_update_features, md_assemble): Likewise. * config/tc-z80.c (emit_byte): Likewise. include/ * opcode/aarch64.h (alias_opcode_p): Simplify boolean expression. (opcode_has_alias, pseudo_opcode_p, optional_operand_p): Likewise. (opcode_has_special_coder): Likewise. ld/ * emultempl/aix.em (gld${EMULATION_NAME}_before_allocation): Simplify boolean expression. * lexsup.c (parse_args): Likewise. * pe-dll.c (pe_dll_id_target): Likewise. opcodes/ * aarch64-opc.c (vector_qualifier_p): Simplify boolean expression. (fp_qualifier_p, get_data_pattern): Likewise. (aarch64_get_operand_modifier_from_value): Likewise. (aarch64_extend_operator_p, aarch64_shift_operator_p): Likewise. (operand_variant_qualifier_p): Likewise. (qualifier_value_in_range_constraint_p): Likewise. (aarch64_get_qualifier_esize): Likewise. (aarch64_get_qualifier_nelem): Likewise. (aarch64_get_qualifier_standard_value): Likewise. (get_lower_bound, get_upper_bound): Likewise. (aarch64_find_best_match, match_operands_qualifier): Likewise. (aarch64_print_operand): Likewise. * aarch64-opc.h (operand_has_inserter, operand_has_extractor): Likewise. (operand_need_sign_extension, operand_need_shift_by_two): Likewise. (operand_need_shift_by_four, operand_maybe_stack_pointer): Likewise. * arm-dis.c (print_insn_mve, print_insn_thumb32): Likewise. * tic6x-dis.c (tic6x_check_fetch_packet_header): Likewise. (print_insn_tic6x): Likewise.
2021-03-29opcodes int vs bfd_boolean fixesAlan Modra3-10/+15
cpu/ * frv.opc (frv_is_branch_major, frv_is_float_major), (frv_is_media_major, frv_is_branch_insn, frv_is_float_insn), (frv_is_media_insn, spr_valid): Correct prototypes. include/ * opcode/aarch64.h (aarch64_opcode_encode): Correct prototype. opcodes/ * arc-dis.c (extract_operand_value): Correct NULL cast. * frv-opc.h: Regenerate.
2021-03-26x86-64: don't accept supposedly disabled MOVQ formsJan Beulich3-4/+10
While all of MMX, SSE, and SSE2 are included in "generic64", they can be individually disabled. There are two MOVQ forms lacking respective attributes. While the MMX one would get refused anyway (due to MMX registers not recognized with .nommx), the assembler did happily accept the SSE2 form. Add respective CPU settings to both, paralleling what the MOVD counterparts have.
2021-03-25[NIOS2] Fix disassembly of br.n instruction.Hafiz Abid Qadeer2-1/+6
The code was checking wrong bit for sign extension. It caused it to zero-extend instead of sign-extend the immediate value. 2021-03-25 Abid Qadeer <abidh@codesourcery.com> opcodes/ * nios2-dis.c (nios2_print_insn_arg): Fix sign extension of immediate in br.n instruction. gas/ * testsuite/gas/nios2/brn.s: New. * testsuite/gas/nios2/brn.d: New.
2021-03-25x86: flag bad S/G insn operand combinationsJan Beulich3-16/+86
For VEX-encoded ones, all three involved vector registers have to be distinct. For EVEX-encoded ones an actual mask register has to be in use and zeroing-masking cannot be used (violation of either will #UD). Additionally both involved vector registers have to be distinct for EVEX-encoded gathers.
2021-03-25x86: flag as bad AVX512 insns with EVEX.z set but EVEX.aaa clearJan Beulich2-0/+12
This combination makes no sense and is documented to cause #UD.
2021-03-25x86: fix AMD Zen3 insnsJan Beulich3-4/+66
For INVLPGB the operand count was wrong (besides %edx there's also %ecx which is an input to the insn). In this case I see little sense in retaining the bogus 2-operand template. Plus swapping of the operands wasn't properly suppressed for Intel syntax. For PVALIDATE, RMPADJUST, and RMPUPDATE bogus single operand templates were specified. These get retained, as the address operand is the only one really needed to expressed non-default address size, but only for compatibility reasons. Proper multi-operand insn get introduced and the testcases get adjusted / extended accordingly. While at it also drop the redundant definition of __amd64__ - we already have x86_64 defined (or not) to distinguish 64-bit and non-64-bit cases.
2021-03-25PR27647 PowerPC extended conditional branch mnemonicsAlan Modra2-476/+486
opcodes/ PR 27647 * ppc-opc.c (XLOCB_MASK): Delete. (XLBOBB_MASK, XLBOBIBB_MASK, XLBOCBBB_MASK): Define using XLBH_MASK. (powerpc_opcodes): Accept a BH field on all extended forms of bclr, bclrl, bcctr, bcctrl, bctar, bctarl. gas/ PR 27647 * testsuite/gas/ppc/a2.d: Update expected output. * testsuite/gas/ppc/power8.d: Likewise.
2021-03-24x86: derive opcode length from opcode valueJan Beulich5-7463/+7468
In the majority of cases we can easily determine the length from the encoding, irrespective of whether a prefix is specified there as well. We further don't even need to record the value in the table entries, as it's easy enough to determine it (without any guesswork, unless an insn with major opcode 00 appeared that requires a 2nd opcode byte to be specified explicitly) when installing the chosen template for further processing. Should an encoding appear which - has a major opcode byte of 66, F3, or F2, - requires a 2nd opcode byte to be specified explicitly, - doesn't have a mandatory prefix we'd need to convert all templates presently encoding a mandatory prefix this way to the Prefix_0X<nn> model to eliminate the respective guessing i386-gen does.
2021-03-24x86: derive mandatory prefix attribute from base opcodeJan Beulich3-5027/+5028
Just like is already done for legacy encoded insns, record the mandatory prefix information in the respective opcode modifier field. Do this without changing the source table, but rather by deriving the values from their existing source representation.
2021-03-24x86: don't use opcode_length to identify pseudo prefixesJan Beulich5-34/+40
This is in preparation of opcode_length going away as a field in the templates. Identify pseudo prefixes by a base opcode of zero instead: No real prefix has an opcode of zero. This at the same time allows dropping a curious special case from i386-gen. Since most attributes are identical for all pseudo prefixes, take the opportunity and also template them.
2021-03-23x86: re-number PREFIX_0X<nn>Jan Beulich3-153/+160
In preparation to use PREFIX_0X<nn> attributes also in VEX/XOP/EVEX encoding templates, renumber the pseudo-enumerators such that their values can then also be used directly in the respective prefix bit fields.
2021-03-23x86: re-order two fields of struct insn_templateJan Beulich4-12106/+12112
To facilitate a subsequent table parser change, re-order CPU flags and opcode modifier fields. No functional change intended.
2021-03-23x86: split opcode prefix and opcode space representationJan Beulich5-9314/+9341
Commit 8b65b8953af2 ("x86: Remove the prefix byte from non-VEX/EVEX base_opcode") used the opcodeprefix field for two distinct purposes. In preparation of having VEX/XOP/EVEX and non-VEX templates become similar in the representatioon of both encoding space and opcode prefixes, split the field to have a separate one holding an insn's opcode space.
generated by cgit v1.1 at 2024-12-14 13:50:22 +0000