riscv-gnu-toolchain/gdb.git - Unnamed repository; edit this file 'description' to name the repository.

Age	Commit message (Expand)	Author	Files	Lines
2023-12-20	s390: Add suffix to conditional branch instruction descriptions	Jens Remus	1	-34/+44
2023-12-20	s390: Optionally print instruction description in disassembly	Jens Remus	3	-39/+55
2023-12-20	s390: Use safe string functions and length macros in s390-mkopc	Jens Remus	1	-25/+52
2023-12-20	s390: Enhance error handling in s390-mkopc	Jens Remus	1	-14/+35
2023-12-20	s390: Provide IBM z16 (arch14) instruction descriptions	Jens Remus	1	-28/+38
2023-12-20	s390: Align letter case of instruction descriptions	Jens Remus	1	-21/+21
2023-12-20	s390: Fix build when using EXEEXT_FOR_BUILD	Jens Remus	2	-4/+10
2023-12-19	aarch64: Add FEAT_ITE support	Andrea Corallo	3	-2/+12
2023-12-19	aarch64: Add FEAT_ECBHB support	Andrea Corallo	3	-1/+7
2023-12-19	aarch64: Add FEAT_SPECRES2 support	Andrea Corallo	4	-2074/+2083
2023-12-19	x86: Remove the restriction for size of the mask register in AVX10	Haochen Jiang	4	-3777/+3762
2023-12-18	LoongArch: Add call36 and tail36 pseudo instructions for medium code model	mengqinggang	1	-0/+11
2023-12-15	revert "x86: allow 32-bit reg to be used with U{RD,WR}MSR"	Jan Beulich	2	-4/+4
2023-12-15	x86: fold assembly dialect attributes	Jan Beulich	4	-7498/+3755
2023-12-15	x86: Intel syntax implies Intel mnemonics	Jan Beulich	3	-333/+298
2023-12-14	RISC-V: Fix the wrong encoding and operand of the XTheadFmv extension.	Jin Ma	1	-1/+1
2023-12-14	Remove redundant Byte, Word, Dword and Qword from insn templates.	Cui, Lili	1	-123/+123
2023-12-13	Make const_1_mode print $1 in AT&T syntax	Cui, Lili	1	-0/+2
2023-12-11	LoongArch: Add support for <b ".L1"> and <beq, $t0, $t1, ".L1">	mengqinggang	1	-0/+7
2023-12-04	s390: Support for jump visualization in disassembly	Jens Remus	3	-42/+88
2023-12-01	x86: allow 32-bit reg to be used with U{RD,WR}MSR	Jan Beulich	2	-4/+4
2023-12-01	RISC-V: Make riscv_is_mapping_symbol stricter	Patrick O'Neill	1	-3/+1
2023-12-01	RISC-V: Add SiFive custom vector coprocessor interface instructions v1.0	Nelson Chu	2	-0/+57
2023-12-01	RISC-V: Zv*: Add support for Zvkb ISA extension	Christoph Müllner	1	-10/+10
2023-11-30	RISC-V: Avoid updating state until symbol is found	Patrick O'Neill	1	-12/+31
2023-11-27	as: Add new estimated reciprocal instructions in LoongArch v1.1	Jiajie Chen	1	-0/+12
2023-11-27	as: Add new atomic instructions in LoongArch v1.1	Jiajie Chen	1	-0/+42
2023-11-24	RISC-V: drop leftover match_never() references	Jan Beulich	1	-4/+4
2023-11-24	x86: shrink opcode sets table	Jan Beulich	2	-2347/+302
2023-11-24	x86: also prefer VEX encoding over EVEX one for VCVTNEPS2BF16 when possible	Jan Beulich	1	-0/+6
2023-11-24	RISC-V: reduce redundancy in sign/zero extension macro insn handling	Jan Beulich	1	-2/+2
2023-11-24	RISC-V: disallow x0 with certain macro-insns	Jan Beulich	2	-45/+48
2023-11-24	Fix building for the s390 target with clang	Nick Clifton	1	-2/+3
2023-11-23	s390: Correct prno instruction name	Jens Remus	1	-1/+1
2023-11-23	s390: Add missing extended mnemonics	Jens Remus	2	-5/+31
2023-11-23	s390: Align optional operand definition to specs	Jens Remus	1	-9/+11
2023-11-23	s390: Make operand table indices relative to each other	Jens Remus	1	-82/+92
2023-11-23	RISC-V: Add vector permutation instructions for T-Head VECTOR vendor extension	Jin Ma	1	-0/+15
2023-11-23	RISC-V: Add vector mask instructions for T-Head VECTOR vendor extension	Jin Ma	1	-0/+19
2023-11-23	RISC-V: Add reductions instructions for T-Head VECTOR vendor extension	Jin Ma	1	-0/+16
2023-11-23	RISC-V: Add floating-point arithmetic instructions for T-Head VECTOR vendor e...	Jin Ma	1	-0/+86
2023-11-23	RISC-V: Add fixed-point arithmetic instructions for T-Head VECTOR vendor exte...	Jin Ma	1	-0/+36
2023-11-23	RISC-V: Add integer arithmetic instructions for T-Head VECTOR vendor extension	Jin Ma	1	-0/+143
2023-11-23	RISC-V: Add sub-extension XTheadZvamo for T-Head VECTOR vendor extension	Jin Ma	1	-0/+18
2023-11-23	RISC-V: Add load/store segment instructions for T-Head VECTOR vendor extension	Jin Ma	1	-0/+280
2023-11-23	RISC-V: Add load/store instructions for T-Head VECTOR vendor extension	Jin Ma	1	-0/+44
2023-11-23	RISC-V: Add configuration-setting instructions for T-Head VECTOR vendor exten...	Jin Ma	1	-0/+4
2023-11-23	RISC-V: Add CSRs for T-Head VECTOR vendor extension	Jin Ma	1	-2/+12
2023-11-21	[opcodes] ARC + PPC: Fix -Walloc-size warnings	Jan-Benedict Glaw	2	-2/+2
2023-11-17	x86: CPU-qualify {disp16} / {disp32}	Jan Beulich	2	-3/+3