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2021-01-09Binutils: Pass --plugin to AR and RANLIBH.J. Lu2-2/+29
2021-01-09Change version number to 2.36.50 and regenerate filesNick Clifton3-242/+288
2021-01-09Add Changelog entries and NEWS entries for 2.36 branchNick Clifton1-0/+4
2021-01-09POWER10: Add Return-Oriented Programming instructionsPeter Bergner2-1/+51
2021-01-09configure regenAlan Modra2-2/+6
2021-01-08Updated Swedish translation for the opcodes/ subdirectoryNick Clifton2-280/+353
2021-01-08Fix places in the AArch64 opcodes library code where a call to assert() has s...Nick Clifton3-7/+16
2021-01-08Treat the AArch64 register id_aa64mmfr2_el1 as a core system register.Nick Clifton2-1/+7
2021-01-07libtool.m4: update GNU/Hurd test from upstream. In upstream libtool, 47a889a...Samuel Thibault2-11/+5
2021-01-07Updated French translation for the opcodes/ subdirectory.Nick Clifton2-242/+317
2021-01-07m68k: Require m68020up rather than m68000up for CHK.L instruction.Fredrik Noring2-1/+6
2021-01-07RISC-V: Add pause hint instruction.Philipp Tomsich2-0/+7
2021-01-07RISC-V: Support riscv bitmanip frozen ZBA/ZBB/ZBC instructions (v0.93).Claire Xenia Wolf2-4/+63
2021-01-01PR27116, Spelling errors found by Debian style checkerAlan Modra1-1/+1
2021-01-01Update year range in copyright notice of binutils filesAlan Modra276-279/+283
2021-01-01ChangeLog rotationAlan Modra2-3269/+3283
2020-12-10RISC-V: Add sext.[bh] and zext.[bhw] pseudo instructions.Nelson Chu2-0/+9
2020-12-10RISC-V: Dump CSR according to the elf privileged spec attributes.Nelson Chu4-4/+47
2020-12-10RISC-V: Control fence.i and csr instructions by zifencei and zicsr.Nelson Chu2-20/+25
2020-12-04IBM Z: Add risbgz and risbgnz extended mnemonicsAndreas Krebbel3-12/+25
2020-12-03IBM Z: Add support for HLASM extended mnemonicsAndreas Krebbel2-0/+18
2020-12-01RISC-V: Remove the unimplemented extensions.Nelson Chu2-11/+5
2020-12-01RISC-V: Add zifencei and prefixed h class extensions.Nelson Chu2-0/+7
2020-11-29x86: Do not dump DS/CS segment overrides for branch hintsBorislav Petkov2-2/+16
2020-11-16aarch64: Extract Condition flag manipulation feature from Armv8.4-APrzemyslaw Wirkus2-4/+16
2020-11-14x86: Ignore CS/DS/ES/SS segment-override prefixes in 64-bit modeBorislav Petkov2-5/+27
2020-11-11aarch64: Allow LS64 feature with Armv8.6Przemyslaw Wirkus2-1/+5
2020-11-09Add support for the LMBD (left-most bit detect) instruction to the PRU assemb...Spencer E. Olson2-0/+7
2020-11-09aarch64: Update LS64 feature with system registerPrzemyslaw Wirkus2-0/+6
2020-11-09aarch64: Limit Rt register number for LS64 load/store instructionsPrzemyslaw Wirkus6-168/+183
2020-11-06aarch64: Extract Pointer Authentication feature from Armv8.3-APrzemyslaw Wirkus2-33/+45
2020-11-04aarch64: Update feature RAS system registersPrzemyslaw Wirkus2-0/+10
2020-11-03[PATCH][GAS] aarch64: Add atomic 64-byte load/store instructions for Armv8.7Przemyslaw Wirkus5-2181/+2249
2020-11-03[PATCH] aarch64: Update missing ChangeLog for AArch64 commitsPrzemyslaw Wirkus1-0/+54
2020-10-30[PATCH][GAS] aarch64: Add WFIT instruction for Armv8.7-aPrzemyslaw Wirkus4-1347/+1353
2020-10-28aarch64: Add CSR PDEC instructionPrzemyslaw Wirkus5-1417/+1430
2020-10-28aarch64: Add WFET instruction for Armv8.7-aPrzemyslaw Wirkus4-1347/+1353
2020-10-28aarch64: Add DSB instruction Armv8.7-a variantPrzemyslaw Wirkus10-1455/+1513
2020-10-28aarch64: Add basic support for armv8.7-a architecturePrzemyslaw Wirkus1-0/+3
2020-10-26CSKY: Change plsl.u16 to plsl.16.Cooper Qu2-1/+5
2020-10-26CSKY: Fix and add some instructions for VDSPV1.Cooper Qu3-39/+231
2020-10-26Change avxvnni disassembler output from {vex3} to {vex}Cui,Lili2-1/+4
2020-10-22[PATCH][GAS][AArch64] Define BRBE system registersPrzemyslaw Wirkus1-0/+106
2020-10-22aarch64: Define CSRE system registersPrzemyslaw Wirkus1-0/+13
2020-10-22opcodes/po/es.po: Remove the duplicated entryH.J. Lu2-8/+4
2020-10-22Fix printf formatting errors where "0x" is used as a prefix for a decimal num...Dr. David Alan Gilbert2-2/+6
2020-10-20Add AMD znver3 processor supportGanesh Gopalasubramanian7-4213/+4494
2020-10-16Enhancement for avx-vnni patchCui,Lili6-11428/+11439
2020-10-14x86: Support Intel AVX VNNIH.J. Lu7-4539/+4705
2020-10-14x86: Add support for Intel HRESET instructionLili Cui7-4467/+4558
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