aboutsummaryrefslogtreecommitdiff
path: root/opcodes
AgeCommit message (Collapse)AuthorFilesLines
2017-11-30x86: derive DispN from BaseIndexJan Beulich4-4142/+4196
BaseIndex implies - with the exception of string instructions the optional presence of a displacement. This is almost completely uniform for all instructions (the sole exception being MPX ones, which don't allow 16-bit addressing and hence Disp16), so there's no point in explicitly stating this in the main opcode table. Drop those explict specifications in favor of adding logic to i386-gen, shrinking the table size quite a bit and hence making it more readable. The opcodes/i386-tbl.h changes are due to a few cases where pointless Disp* still hadn't been removed from their insns.
2017-11-30x86: drop Vec_Disp8Jan Beulich6-16227/+16225
This is fully redundant with Disp8MemShift being non-zero, and hence can be folded with normal Disp8 handling.
2017-11-29Support --localedir, --datarootdir and --datadirStefan Stroe2-4/+10
bfd/ * po/Make-in (datadir): Define as @datadir@. (localedir): Define as @localedir@. (gnulocaledir, gettextsrcdir): Use @datarootdir@. binutils/ * po/Make-in (datadir): Define as @datadir@. (localedir): Define as @localedir@. (gnulocaledir, gettextsrcdir): Use @datarootdir@. gas/ * po/Make-in (datadir): Define as @datadir@. (localedir): Define as @localedir@. (gnulocaledir, gettextsrcdir): Use @datarootdir@. gold/ * po/Make-in (datadir): Define as @datadir@. (localedir): Define as @localedir@. (gnulocaledir, gettextsrcdir): Use @datarootdir@. gprof/ * po/Make-in (datadir): Define as @datadir@. (localedir): Define as @localedir@. (gnulocaledir, gettextsrcdir): Use @datarootdir@. ld/ * po/Make-in (datadir): Define as @datadir@. (localedir): Define as @localedir@. (gnulocaledir, gettextsrcdir): Use @datarootdir@. opcodes/ * po/Make-in (datadir): Define as @datadir@. (localedir): Define as @localedir@. (gnulocaledir, gettextsrcdir): Use @datarootdir@.
2017-11-27Update the simplified Chinese translation of the messages in the opcodes ↵Nick Clifton2-437/+945
library. * po/zh_CN.po: Updated simplified Chinese translation.
2017-11-24x86: don't omit disambiguating suffixes from "fi*"Jan Beulich2-12/+17
"fi*" typically come in two (loads/stores: three) flavors, distinguished by the suffix. Don't omit the 's' one when disassembling.
2017-11-23Add Disp8MemShift for AVX512 VAES instructions.Igor Tsimbalist3-24/+29
opcodes/ * i386-opc.tbl: Add Disp8MemShift for AVX512 VAES instructions. * i386-tbl.h: Regenerate. gas/ * testsuite/gas/i386/avx512f_vaes-intel.d: Regenerate. * testsuite/gas/i386/avx512f_vaes.d: Likewise. * testsuite/gas/i386/avx512f_vaes-wig1-intel.d: Likewise. * testsuite/gas/i386/avx512f_vaes-wig1.d: Likewise. * testsuite/gas/i386/avx512vl_vaes-intel.d: Likewise. * testsuite/gas/i386/avx512vl_vaes.d: Likewise. * testsuite/gas/i386/x86-64-avx512f_vaes.s: Add instructions with disp8*N. * testsuite/gas/i386/x86-64-avx512f_vaes-intel.d: Regenerate. * testsuite/gas/i386/x86-64-avx512f_vaes.d: Likewise. * testsuite/gas/i386/x86-64-avx512f_vaes-wig.s: Add instructions with disp8*N. * testsuite/gas/i386/x86-64-avx512f_vaes-wig1-intel.d: Regenerate. * testsuite/gas/i386/x86-64-avx512f_vaes-wig1.d: Likewise. * testsuite/gas/i386/x86-64-avx512vl_vaes-intel.d: Regenerate. * testsuite/gas/i386/x86-64-avx512vl_vaes.d: Likewise. * testsuite/gas/i386/x86-64-avx512vl_vaes-wig.s: Add instructions with disp8*N. * testsuite/gas/i386/x86-64-avx512vl_vaes-wig1-intel.d: Regenerate. * testsuite/gas/i386/x86-64-avx512vl_vaes-wig1.d: Regenerate.
2017-11-23x86: fix AVX-512 16-bit addressingJan Beulich2-0/+7
Despite EVEX encodings not being available in real and VM86 modes, 16-bit addressing still needs to be handled properly for 16-bit protected mode as well as 16-bit addressing in 32-bit mode. Neither should displacements be dropped silently by the assembler, nor should the disassembler fail to correctly scale 8-bit displacements.
2017-11-23x86: correct UDnJan Beulich4-14/+47
Make the assembler recognize UD0, supporting only the newer form expecting a ModR/M byte. Make assembler and disassembler properly emit / expect a ModR/M byte for UD1. For the testsuite, as arch-4 already tests all UDn, avoid producing a huge delta for other tests using UD2B by making them use UD2 instead.
2017-11-22Remove Vec_Disp8 field for vgf2p8mulb for AVX flavor.Igor Tsimbalist3-4/+9
* i386-opc.tbl: Remove Vec_Disp8 from vgf2p8mulb. * i386-tbl.h: Regenerate.
2017-11-22Update ChangeLogIgor Tsimbalist1-0/+5
2017-11-22Remove Vec_Disp8 from vpcompressb and vpexpandb.Igor Tsimbalist2-13/+12
* i386-opc.tbl: Remove Vec_Disp8 from vpcompressb and vpexpandb. * i386-tbl.h: Regenerate.
2017-11-22[ARC] Fix handling of ARCv2 H-register class.claziss2-0/+6
For ARCv2, h-regs are only valid unitl r31. gas/ 2017-11-21 Claudiu Zissulescu <claziss@synopsys.com> * testsuite/gas/arc/hregs-err.s: New test. opcodes/ 2017-11-21 Claudiu Zissulescu <claziss@synopsys.com> * arc-opc.c (insert_rhv2): Check h-regs range.
2017-11-21[ARC] Improve printing of pc-relative instructions.claziss3-17/+52
opcodes/ 2017-11-21 Claudiu Zissulescu <claziss@synopsys.com> * arc-dis.c (print_insn_arc): Pretty print pc-relative offsets. * arc-opc.c (SIMM21_A16_5): Make it pc-relative. gas/ 2017-11-21 Claudiu Zissulescu <claziss@synopsys.com> * testsuite/gas/arc/b.d : Update test. * testsuite/gas/arc/bl.d: Likewise. * testsuite/gas/arc/jli-1.d: Likewise. * testsuite/gas/arc/lp.d: Likewise. * testsuite/gas/arc/pcl-relocs.d: Likewise. * testsuite/gas/arc/pcrel-relocs.d: Likewise. * testsuite/gas/arc/pic-relocs.d: Likewise. * testsuite/gas/arc/plt-relocs.d: Likewise. * testsuite/gas/arc/pseudos.d: Likewise. * testsuite/gas/arc/relax-avoid2.d: Likewise. * testsuite/gas/arc/relax-avoid3.d: Likewise. * testsuite/gas/arc/relax-b.d: Likewise. * testsuite/gas/arc/tls-relocs.d: Likewise. * testsuite/gas/arc/relax-add01.d: Likewise. * testsuite/gas/arc/relax-add04.d: Likewise. * testsuite/gas/arc/relax-ld01.d: Likewise. * testsuite/gas/arc/relax-sub01.d: Likewise. * testsuite/gas/arc/relax-sub02.d: Likewise. * testsuite/gas/arc/relax-sub04.d: Likewise. * testsuite/gas/arc/pcl-print.s: New file. * testsuite/gas/arc/pcl-print.d: Likewise. * testsuite/gas/arc/nps400-12.d: Likewise. ld/ 2017-11-21 Claudiu Zissulescu <claziss@synopsys.com> * testsuite/ld-arc/jli-simple.d: Update test.
2017-11-16Add new AArch64 FP16 FM{A|S} instructions.Tamar Christina2-2/+7
This patch separates the new FP16 instructions backported from Armv8.4-a to Armv8.2-a into a new flag order to distinguish them from the rest of the already existing optional FP16 instructions in Armv8.2-a. The new flag "+fp16fml" is available from Armv8.2-a and implies +fp16 and is mandatory on Armv8.4-a. gas/ * config/tc-aarch64.c (fp16fml): New. * doc/c-aarch64.texi (fp16fml): New. * testsuite/gas/aarch64/armv8_2-a-crypto-fp16.d (fp16): Make fp16fml. * testsuite/gas/aarch64/armv8_3-a-crypto-fp16.d (fp16): Make fp16fml. include/ * opcode/aarch64.h: (AARCH64_FEATURE_F16_FML): New. (AARCH64_ARCH_V8_4): Enable AARCH64_FEATURE_F16_FML by default. opcodes/ * aarch64-tbl.h (aarch64_feature_fp_16_v8_2): Require AARCH64_FEATURE_F16_FML and AARCH64_FEATURE_F16.
2017-11-16Correct AArch64 crypto dependencies.Tamar Christina1-4/+6
The crypto options depend on SIMD and FP, the documentation states so but the dependency is not there the code. We have mostly gotten away with this due to the default flags for the architectures (e.g. Armv8.2-a implies +simd) but this discrepancy needs to be addressed. gas/ 2017-11-16 Tamar Christina <tamar.christina@arm.com> * opcodes/aarch64-tbl.h (aarch64_feature_crypto): Add ARCH64_FEATURE_SIMD and AARCH64_FEATURE_FP. (aarch64_feature_crypto_v8_2, aarch64_feature_sm4): Likewise. (aarch64_feature_sha3): Likewise.
2017-11-16Add assembler and disassembler support for the new Armv8.4-a instructions ↵Tamar Christina3-2925/+3534
for AArch64. Some of these instructions have been back-ported as optional extensions to Armv8.2-a and higher, but others are only available for Armv8.4-a. opcodes/ * aarch64-tbl.h (sha512h, sha512h2, sha512su0, sha512su1, eor3): New. (rax1, xar, bcax, sm3ss1, sm3tt1a, sm3tt1b, sm3tt2a, sm3tt2b): New. (sm3partw1, sm3partw2, sm4e, sm4ekey, fmlal, fmlsl): New. (fmlal2, fmlsl2, cfinv, rmif, setf8, setf16, stlurb): New. (ldapurb, ldapursb, stlurh, ldapurh, ldapursh, stlur): New. (ldapur, ldapursw, stlur): New. * aarch64-dis-2.c: Regenerate. gas/ * testsuite/gas/aarch64/armv8_4-a-illegal.d: New. * testsuite/gas/aarch64/armv8_4-a-illegal.l: New. * testsuite/gas/aarch64/armv8_4-a-illegal.s: New. * testsuite/gas/aarch64/armv8_4-a.d: New. * testsuite/gas/aarch64/armv8_4-a.s: New. * testsuite/gas/aarch64/armv8_2-a-crypto-fp16.s: New. * testsuite/gas/aarch64/armv8_2-a-crypto-fp16.d: New. * testsuite/gas/aarch64/armv8_3-a-crypto-fp16.d: New. * testsuite/gas/aarch64/armv8_4-a-crypto-fp16.d: New. * testsuite/gas/aarch64/armv8_2-a-crypto-fp16-illegal.s: New. * testsuite/gas/aarch64/armv8_2-a-crypto-fp16-illegal.l: New. * testsuite/gas/aarch64/armv8_2-a-crypto-fp16-illegal.d: New.
2017-11-16x86: ignore high register select bit(s) in 32- and 16-bit modesJan Beulich2-28/+47
While commits 9889cbb14e ("Check invalid mask registers") and abfcb414b9 ("X86: Ignore REX_B bit for 32-bit XOP instructions") went a bit into the right direction, this wasn't quite enough: - VEX.vvvv has its high bit ignored - EVEX.vvvv has its high bit ignored together with EVEX.v' - the high bits of {,E}VEX.vvvv should not be prematurely zapped, to allow proper checking of them when the fields has to hold al ones - when the high bits of an immediate specify a register, bit 7 is ignored
2017-11-15x86: use correct register namesJan Beulich2-3/+8
VEX.W may be legitimately set (and is then ignored by the CPU) for non-64-bit code. Don't print 64-bit register names in such a case, by utilizing that REX_W would never be set for non-64-bit code, and that it is being set from VEX.W by generic decoding. A test for this is going to be introduced in the next patch of this series.
2017-11-15x86: drop VEXI4_Fixup()Jan Beulich2-50/+45
The low four bits of an immediate being set when the high bits specify a fourth register operand is not a problem: CPUs ignore these bits rather than raising #UD. Take care of incrementing codep in OP_EX_VexW() instead.
2017-11-15x86-64: don't allow use of %axl as accumulatorJan Beulich3-2/+7
Just like %cxl can't be used as shift count register. Otherwise for consistency %cxl would need to gain "ShiftCount" and use of both ought to properly cause REX prefixes to be emitted.
2017-11-14x86: add disassembler support for XOP VPCOM* pseudo-opsJan Beulich2-8/+67
Matching up with the assembler, which already supports them.
2017-11-14x86: add support for AVX-512 VPCMP*{B,W} pseudo-opsJan Beulich4-29/+1554
... matching up with VPCMP*{D,Q}.
2017-11-14x86: string insns don't allow displacementsJan Beulich3-42/+48
Remove the misleading indicators from the table.
2017-11-13x86: {f,}xsave64 / {f,}xrstor64 / xsaveopt64 should not allow q suffixJan Beulich3-10/+16
Just like is the case for xsave{s,c}64 and xrstors64 already. I wonder though why xsave{s,c} and xrstors don't allow for the q suffix, other than the other insns without the "64" suffix do.
2017-11-09Add assembler and disassembler support for the new Armv8.4-a registers for ↵Tamar Christina2-1/+164
AArch64. Some of these instructions have been back-ported as optional extensions to Armv8.2-a and higher, but others are only available for Armv8.4-a. opcodes/ * aarch64-opc.c (aarch64_sys_regs): Add ARMv8.4-a registers; dit, vstcr_el2, vsttbr_el2, cnthvs_tval_el2, cnthvs_cval_el2, cnthvs_ctl_el2, cnthps_tval_el2, cnthps_cval_el2, cnthps_ctl_el2, sder32_el2, vncr_el2. (aarch64_sys_reg_supported_p): Likewise. (aarch64_pstatefields): Add dit register. (aarch64_pstatefield_supported_p): Likewise. (aarch64_sys_regs_tlbi): Add vmalle1os, vae1os, aside1os, vaae1os, vale1os, vaale1os, ipas2e1os, ipas2le1os, vae2os, vale2os, vmalls12e1os, vae3os, vale3os, alle2os, alle1os, alle3os, rvae1, rvaae1, rvale1, rvaale1, rvae1is, rvaae1is, rvale1is, rvaale1is, rvae1os, rvaae1os, rvale1os, rvaale1os, ripas2e1is, ripas2le1is, ripas2e1, ripas2le1, ripas2e1os, ripas2le1os, rvae2, rvale2, rvae2is, rvale2is, rvae2os, rvale2os, rvae3, rvale3, rvae3is, rvale3is, rvae3os, rvale3os. gas/testsuite * gas/aarch64/armv8_4-a-registers-illegal.d: New. * gas/aarch64/armv8_4-a-registers-illegal.l: New. * gas/aarch64/armv8_4-a-registers-illegal.s: New. * gas/aarch64/armv8_4-a-registers.d: New. * gas/aarch64/armv8_4-a-registers.s: New.
2017-11-09Add the operand encoding types for the new Armv8.2-a back-ported ↵Tamar Christina2-0/+97
instructions. These are to be used later when the new instructions are added. opcodes/ * aarch64-tbl.h (QL_SHA512UPT, QL_V2SAME2D, QL_V3SAME2D): New. (QL_V4SAME16B, QL_V4SAME4S, QL_XAR, QL_SM3TT, QL_V3FML2S): New. (QL_V3FML4S, QL_V2FML2S, QL_V2FML4S, QL_RMIF, QL_SETF): New. (QL_STLW, QL_STLX): New.
2017-11-09Adds the new Fields and Operand types for the new instructions in Armv8.4-a.Tamar Christina11-179/+296
gas/ * config/tc-aarch64.c (process_omitted_operand): Add AARCH64_OPND_Va, AARCH64_OPND_SM3_IMM2 and AARCH64_OPND_IMM_2. (parse_operands): Add AARCH64_OPND_Va, AARCH64_OPND_SM3_IMM2, AARCH64_OPND_IMM_2, AARCH64_OPND_MASK and AARCH64_OPND_ADDR_OFFSET. include/ * opcode/aarch64.h: (aarch64_opnd): Add AARCH64_OPND_Va, AARCH64_OPND_MASK, AARCH64_OPND_IMM_2, AARCH64_OPND_ADDR_OFFSET and AARCH64_OPND_SM3_IMM2. (aarch64_insn_class): Add cryptosm3 and cryptosm4. (arch64_feature_set): Make uint64_t. opcodes/ * aarch64-asm.h (ins_addr_offset): New. * aarch64-asm.c (aarch64_ins_reglane): Add cryptosm3. (aarch64_ins_addr_offset): New. * aarch64-asm-2.c: Regenerate. * aarch64-dis.h (ext_addr_offset): New. * aarch64-dis.c (aarch64_ext_reglane): Add cryptosm3. (aarch64_ext_addr_offset): New. * aarch64-dis-2.c: Regenerate. * aarch64-opc.h (aarch64_field_kind): Add FLD_imm6_2, FLD_imm4_2 and FLD_SM3_imm2. * aarch64-opc.c (fields): Add FLD_imm6_2, FLD_imm4_2 and FLD_SM3_imm2. (operand_general_constraint_met_p): Add AARCH64_OPND_ADDR_OFFSET. (aarch64_print_operand): Add AARCH64_OPND_Va, AARCH64_OPND_SM3_IMM2, AARCH64_OPND_MASK, AARCH64_OPND_IMM_2 and AARCH64_OPND_ADDR_OFFSET. * aarch64-opc-2.c (Va, MASK, IMM_2, ADDR_OFFSET, SM3_IMM2): New. * aarch64-tbl.h (aarch64_opcode_table): Add Va, MASK, IMM_2, ADDR_OFFSET, SM3_IMM2.
2017-11-09Split the ARM Crypto ISA extensions for AES and SHA1+2 into their own ↵Tamar Christina2-0/+37
options (+aes and +sha2). The reason for the split is because with the introduction of Armv8.4-a the implementation of AES has explicitly been made independent of the implementation of the other crypto extensions. gas * config/tc-aarch64.c (aarch64_arch_option_table): Add armv8.4-a. (aarch64_features): Added SM4 and SHA3. include * opcode/aarch64.h: (AARCH64_FEATURE_V8_4, AARCH64_FEATURE_SM4): New. (AARCH64_ARCH_V8_4, AARCH64_FEATURE_SHA3): New. opcodes * aarch64-tbl.h (aarch64_feature_v8_4, aarch64_feature_crypto_v8_2): New. (aarch64_feature_sm4, aarch64_feature_sha3): New. (aarch64_feature_fp_16_v8_2): New. (ARMV8_4, SHA3, SM4, CRYPTO_V8_2, FP_F16_V8_2): New. (V8_4_INSN, CRYPTO_V8_2_INSN): New. (SHA3_INSN, SM4_INSN, FP16_V8_2_INSN): New.
2017-11-08Split the AArch64 Crypto instructions for AES and SHA1+2 into their own ↵Nick Clifton2-17/+39
options (+aes and +sha2). The new options are: +aes: Enables the AES instructions of Armv8-a, enabled by default with +crypto. +sha2: Enables the SHA1 and SHA2 instructions of Armv8-a, enabled by default with +crypto. These options have been turned on by default when +crypto is used, as such no breakage is expected. The reason for the split is because with the introduction of Armv8.4-a the implementation of AES has explicitly been made independent of the implementation of the other crypto extensions. Backporting the split does not break any of the previous requirements and so is safe to do. gas * config/tc-aarch64.c (aarch64_features): Include AES and SHA2 in CRYPTO. Add SHA2 and AES. include * opcode/aarch64.h: (AARCH64_FEATURE_SHA2, AARCH64_FEATURE_AES): New. opcodes * aarch64-tbl.h (aarch64_feature_crypto): Add AES and SHA2. (aarch64_feature_sha2, aarch64_feature_aes): New. (SHA2, AES): New. (AES_INSN, SHA2_INSN): New. (pmull, pmull2, aese, aesd, aesmc, aesimc): Change to AES_INS. (sha1h, sha1su1, sha256su0, sha1c, sha1p, sha1m, sha1su0, sha256h, sha256h2, sha256su1): Change to SHA2_INS.
2017-11-08Adds command line support for Armv8.4-A, via the new command line option ↵Jiong Wang2-0/+24
-march=armv8.4-a. Add support for "+dotprod" ARM feature (required for ARMv8.4-A). Add assembler and disassembler support for new FP16 instructions introduced in Armv8.4-A gas * config/tc-arm.c (arm_extensions): (arm_archs): New entry for "armv8.4-a". Add FPU_ARCH_DOTPROD_NEON_VFP_ARMV8. (arm_ext_v8_2): New variable. (enum arm_reg_type): New enumeration REG_TYPE_NSD. (reg_expected_msgs): New entry for REG_TYPE_NSD. (parse_typed_reg_or_scalar): Handle REG_TYPE_NSD. (parse_scalar): Support REG_TYPE_VFS. (enum operand_parse_code): New enumerations OP_RNSD and OP_RNSD_RNSC. (parse_operands): Handle OP_RNSD and OP_RNSD_RNSC. (NEON_SHAPE_DEF): New entries for DHH and DHS. (neon_scalar_for_fmac_fp16_long): New function to generate Rm encoding for new FP16 instructions in ARMv8.2-A. (do_neon_fmac_maybe_scalar_long): New function to encode new FP16 instructions in ARMv8.2-A. (do_neon_vfmal): Wrapper function for vfmal. (do_neon_vfmsl): Wrapper function for vfmsl. (insns): New entries for vfmal and vfmsl. * doc/c-arm.texi (-march): Document "armv8.4-a". * testsuite/gas/arm/dotprod-mandatory.d: New test. * testsuite/gas/arm/armv8_2-a-fp16.s: New test source. * testsuite/gas/arm/armv8_2-a-fp16-illegal.s: New test source. * testsuite/gas/arm/armv8_2-a-fp16.d: New test. * testsuite/gas/arm/armv8_3-a-fp16.d: New test. * testsuite/gas/arm/armv8_4-a-fp16.d: New test. * testsuite/gas/arm/armv8_2-a-fp16-thumb2.d: New test. * testsuite/gas/arm/armv8_2-a-fp16-illegal.d: New test. * testsuite/gas/arm/armv8_2-a-fp16-illegal.l: New error file. opcodes * arm-dis.c (coprocessor_opcodes): New entries for ARMv8.2-A new FP16 instructions, including vfmal.f16 and vfmsl.f16. include * opcode/arm.h (ARM_AEXT2_V8_4A): Include Dot Product feature. (ARM_EXT2_V8_4A): New macro. (ARM_AEXT2_V8_4A): Likewise. (ARM_ARCH_V8_4A): Likewise.
2017-11-07opcodes/arc: Fix incorrect insn_class for some nps insnsAndrew Burgess2-4/+8
A small number of NPS400 instruction incorrectly used NONE as an insn_class_t, which would trigger a build warning. Fixed by changing to MISC. opcodes/ChangeLog: * arc-nps400-tbl.h: Change incorrect use of NONE to MISC.
2017-11-07ngettext supportAlan Modra2-16/+35
binutils has lacked proper pluralization of output messages for a long time, for example, readelf will display information about a section that "contains 1 entries" or "There are 1 section headers". Fixing this properly requires us to use ngettext, because other languages have different rules to English. This patch defines macros for ngettext and friends to handle builds with --disable-nls, and tidies the existing nls support. I've redefined gettext rather than just defining "_" as dgettext in bfd and opcodes in case someone wants to use gettext there (which might conceivably happen with generated code). bfd/ * sysdep.h: Formatting, comment fixes. (gettext, ngettext): Redefine when ENABLE_NLS. (ngettext, dngettext, dcngettext): Define when !ENABLE_NLS. (_): Define using gettext. (textdomain, bindtextdomain): Use safer "do nothing". * hosts/alphavms.h (textdomain, bindtextdomain): Likewise. (ngettext, dngettext, dcngettext): Define when !ENABLE_NLS. opcodes/ * opintl.h: Formatting, comment fixes. (gettext, ngettext): Redefine when ENABLE_NLS. (ngettext, dngettext, dcngettext): Define when !ENABLE_NLS. (_): Define using gettext. (textdomain, bindtextdomain): Use safer "do nothing". binutils/ * sysdep.h (textdomain, bindtextdomain): Use safer "do nothing". (ngettext, dngettext, dcngettext): Define when !ENABLE_NLS. gas/ * asintl.h (textdomain, bindtextdomain): Use safer "do nothing". (ngettext, dngettext, dcngettext): Define when !ENABLE_NLS. gold/ * system.h (textdomain, bindtextdomain): Use safer "do nothing". (ngettext, dngettext, dcngettext): Define when !ENABLE_NLS. ld/ * ld.h (textdomain, bindtextdomain): Use safer "do nothing". (ngettext, dngettext, dcngettext): Define when !ENABLE_NLS.
2017-11-03[ARC] Force the disassam to use the hexadecimal number for printingclaziss2-1/+21
Force printing of the short/signed values using hexadecimal representation via disassembler option. opcode/ 2017-11-03 Claudiu Zissulescu <claziss@synopsys.com> * arc-dis.c (print_hex): New variable. (parse_option): Check for hex option. (print_insn_arc): Use hexadecimal representation for short immediate values when requested. (print_arc_disassembler_options): Add hex option to the list. binutils/ 2017-11-03 Claudiu Zissulescu <claziss@synopsys.com> * doc/binutils.texi (ARC): Update disassembler options. * testsuite/binutils-all/arc/hexprint.s: New file. * testsuite/binutils-all/arc/objdump.exp: Test hex printing feature.
2017-11-03[ARC] Sync opcode data base.claziss3-1588/+3455
New EM and HS variants are developed, sync the data base to match them. opcodes/ 2017-11-03 Claudiu Zissulescu <claziss@synopsys.com> * arc-tbl.h (abss, abssh, adc, adcs, adds, aslacc, asls, aslsacc) (asrs, asrsr, cbflyhf0r, cbflyhf1r, cmacchfr, cmacchnfr, cmachfr) (cmachnfr, cmpychfr, cmpychnfr, cmpyhfmr, cmpyhfr, cmpyhnfr, divf) (dmachbl, dmachbm, dmachf, dmachfr, dmacwhf, dmpyhbl, dmpyhbm) (dmpyhf, dmpyhfr, dmpyhwf, dmpywhf, dsync, flagacc, getacc, macdf) (macf, macfr, macwhfl, macwhflr, macwhfm, macwhfmr, macwhkl) (macwhkul, macwhl, macwhul, mpydf, mpyf, mpyfr, mpywhfl, mpywhflr) (mpywhfm, mpywhfmr, mpywhkl, mpywhkul, mpywhl, mpywhul, msubdf) (msubf, msubfr, msubwhfl, msubwhflr, msubwhfm, msubwhfmr, mul64) (negs, negsh, normacc, qmachf, qmpyh, qmpyhf, rndh, satf, sath) (sbcs, setacc, sflag, sqrt, sqrtf, subs, swi_s, vabs2h, vabss2h) (vadd4b, vadds2, vadds2h, vadds4h, vaddsubs, vaddsubs2h) (vaddsubs4h, valgn2h, vasl2h, vasls2h, vasr2h, vasrs2h, vasrsr2h) (vext2bhl, vext2bhlf, vext2bhm, vext2bhmf, vlsr2h, vmac2hf) (vmac2hfr, vmac2hnfr, vmax2h, vmin2h, vmpy2h, vmpy2hf, vmpy2hfr) (vmpy2hwf, vmsub2hf, vmsub2hfr, vmsub2hnfr, vneg2h, vnegs2h) (vnorm2h, vpack2hbl, vpack2hblf, vpack2hbm, vpack2hbmf, vpack2hl) (vpack2hm, vperm, vrep2hl, vrep2hm, vsext2bhl, vsext2bhm, vsub4b) (vsubadds, vsubadds2h, vsubadds4h, vsubs2, vsubs2h, vsubs4h): Changed opcodes. (prealloc, prefetch*): Place them before ld instruction. * arc-opc.c (skip_this_opcode): Add ARITH class.
2017-10-25PR22348, conflicting global vars in crx and cr16Alan Modra4-20/+33
include/ PR 22348 * opcode/cr16.h (instruction): Delete. (cr16_words, cr16_allWords, cr16_currInsn): Delete. * opcode/crx.h (crx_cst4_map): Rename from cst4_map. (crx_cst4_maps): Rename from cst4_maps. (crx_no_op_insn): Rename from no_op_insn. (instruction): Delete. opcodes/ PR 22348 * cr16-dis.c (cr16_cinvs, instruction, cr16_currInsn): Make static. (cr16_words, cr16_allWords, processing_argument_number): Likewise. (imm4flag, size_changed): Likewise. * crx-dis.c (crx_cinvs, NUMCINVS, instruction, currInsn): Likewise. (words, allWords, processing_argument_number): Likewise. (cst4flag, size_changed): Likewise. * crx-opc.c (crx_cst4_map): Rename from cst4_map. (crx_cst4_maps): Rename from cst4_maps. (crx_no_op_insn): Rename from no_op_insn. gas/ PR 22348 * config/tc-crx.c (instruction, output_opcode): Make static. (relocatable, ins_parse, cur_arg_num): Likewise. (parse_insn): Adjust for renamed opcodes globals. (check_range): Likewise
2017-10-24RISC-V: Fix disassembly of c.addi4spn, c.addi16sp, c.lui when imm=0Andrew Waterman2-7/+33
These are all invalid instructions, so they should not disassemble. opcodes/ChangeLog 2017-10-24 Andrew Waterman <andrew@sifive.com> * riscv-opc.c (match_c_addi16sp) : New function. (match_c_addi4spn): New function. (match_c_lui): Don't allow 0-immediate encodings. (riscv_opcodes) <addi>: Use the above functions. <add>: Likewise. <c.addi4spn>: Likewise. <c.addi16sp>: Likewise. gas/ChangeLog 2017-10-24 Andrew Waterman <andrew@sifive.com> * testsuite/gas/riscv/c-addi16sp-fail.d: New test. testsuite/gas/riscv/c-addi16sp-fail.l: Likewise. testsuite/gas/riscv/c-addi16sp-fail.s: Likewise. testsuite/gas/riscv/c-addi4spn-fail.d: Likewise. testsuite/gas/riscv/c-addi4spn-fail.l: Likewise. testsuite/gas/riscv/c-addi4spn-fail.s: Likewise. testsuite/gas/riscv/riscv.exp: Add new tests.
2017-10-23Add missing ChangeLog entriesIgor Tsimbalist1-0/+110
2017-10-23Fix the master due to bad regenerated filesIgor Tsimbalist3-5469/+11545
* i386-init.h: Regenerate * i386-tbl.h: Likewise
2017-10-23Enable Intel AVX512_BITALG instructions.Igor Tsimbalist5-3/+51
Intel has disclosed a set of new instructions. The spec is https://software.intel.com/sites/default/files/managed/c5/15/architecture-instruction-set-extensions-programming-reference.pdf gas/ * config/tc-i386.c (cpu_arch): Add .avx512_bitalg. (cpu_noarch): noavx512_bitalg. * doc/c-i386.texi: Document .avx512_bitalg, noavx512_bitalg. * testsuite/gas/i386/i386.exp: Add AVX512_BITALG tests. * testsuite/gas/i386/avx512f_bitalg-intel.d: New test. * testsuite/gas/i386/avx512f_bitalg.d: Likewise. * testsuite/gas/i386/avx512f_bitalg.s: Likewise. * testsuite/gas/i386/avx512vl_bitalg-intel.d: Likewise. * testsuite/gas/i386/avx512vl_bitalg.d: Likewise. * testsuite/gas/i386/avx512vl_bitalg.s: Likewise. * testsuite/gas/i386/x86-64-avx512f_bitalg-intel.d: Likewise. * testsuite/gas/i386/x86-64-avx512f_bitalg.d: Likewise. * testsuite/gas/i386/x86-64-avx512f_bitalg.s: Likewise. * testsuite/gas/i386/x86-64-avx512vl_bitalg-intel.d: Likewise. * testsuite/gas/i386/x86-64-avx512vl_bitalg.d: Likewise. * testsuite/gas/i386/x86-64-avx512vl_bitalg.s: Likewise. opcodes/ * i386-dis.c (enum): Add PREFIX_EVEX_0F3854, PREFIX_EVEX_0F388F. (enum): Add EVEX_W_0F3854_P_2. * i386-dis-evex.h (evex_table): Updated. * i386-gen.c (cpu_flag_init): Add CPU_AVX512_BITALG, CPU_ANY_AVX512_BITALG_FLAGS. Update CPU_ANY_AVX512F_FLAGS. (cpu_flags): Add CpuAVX512_BITALG. * i386-opc.h (enum): Add CpuAVX512_BITALG. (i386_cpu_flags): Add cpuavx512_bitalg.. * i386-opc.tbl: Add Intel AVX512_BITALG instructions. * i386-init.h: Regenerate. * i386-tbl.h: Likewise.
2017-10-23Enable Intel AVX512_VNNI instructions.Igor Tsimbalist5-6/+48
Intel has disclosed a set of new instructions. The spec is https://software.intel.com/sites/default/files/managed/c5/15/architecture-instruction-set-extensions-programming-reference.pdf gas/ * config/tc-i386.c (cpu_arch): Add .avx512_vnni. (cpu_noarch): Add noavx512_vnni. * doc/c-i386.texi: Document .avx512_vnni. * testsuite/gas/i386/i386.exp: Add AVX512_VNNI tests. * testsuite/gas/i386/avx512vnni-intel.d: New test. * testsuite/gas/i386/avx512vnni.d: Likewise. * testsuite/gas/i386/avx512vnni.s: Likewise. * testsuite/gas/i386/avx512vnni_vl-intel.d: Likewise. * testsuite/gas/i386/avx512vnni_vl.d: Likewise. * testsuite/gas/i386/avx512vnni_vl.s: Likewise. * testsuite/gas/i386/x86-64-avx512vnni-intel.d: Likewise. * testsuite/gas/i386/x86-64-avx512vnni.d: Likewise. * testsuite/gas/i386/x86-64-avx512vnni.s: Likewise. * testsuite/gas/i386/x86-64-avx512vnni_vl-intel.d: Likewise. * testsuite/gas/i386/x86-64-avx512vnni_vl.d: Likewise. * testsuite/gas/i386/x86-64-avx512vnni_vl.s: Likewise. opcodes/ * i386-dis.c (enum): Add PREFIX_EVEX_0F3850, PREFIX_EVEX_0F3851. * i386-dis-evex.h (evex_table): Updated. * i386-gen.c (cpu_flag_init): Add CPU_AVX512_VNNI, CPU_ANY_AVX512_VNNI_FLAGS. Update CPU_ANY_AVX512F_FLAGS. (cpu_flags): Add CpuAVX512_VNNI. * i386-opc.h (enum): Add CpuAVX512_VNNI. (i386_cpu_flags): Add cpuavx512_vnni. * i386-opc.tbl Add Intel AVX512_VNNI instructions. * i386-init.h: Regenerate. * i386-tbl.h: Likewise.
2017-10-23Enable Intel VPCLMULQDQ instruction.Igor Tsimbalist5-14/+30
Intel has disclosed a set of new instructions. The spec is https://software.intel.com/sites/default/files/managed/c5/15/architecture-instruction-set-extensions-programming-reference.pdf gas/ * config/tc-i386.c (cpu_arch): Add VPCLMULQDQ. * doc/c-i386.texi: Document VPCLMULQDQ. * testsuite/gas/i386/i386.exp: Run VPCLMULQDQ tests. * testsuite/gas/i386/avx512f_vpclmulqdq-intel.d: New test. * testsuite/gas/i386/avx512f_vpclmulqdq-wig.s: Ditto. * testsuite/gas/i386/avx512f_vpclmulqdq-wig1-intel.d: Ditto. * testsuite/gas/i386/avx512f_vpclmulqdq-wig1.d: Ditto. * testsuite/gas/i386/avx512f_vpclmulqdq.d: Ditto. * testsuite/gas/i386/avx512f_vpclmulqdq.s: Ditto. * testsuite/gas/i386/avx512vl_vpclmulqdq-intel.d: Ditto. * testsuite/gas/i386/avx512vl_vpclmulqdq-wig.s: Ditto. * testsuite/gas/i386/avx512vl_vpclmulqdq-wig1-intel.d: Ditto. * testsuite/gas/i386/avx512vl_vpclmulqdq-wig1.d: Ditto. * testsuite/gas/i386/avx512vl_vpclmulqdq.d: Ditto. * testsuite/gas/i386/avx512vl_vpclmulqdq.s: Ditto. * testsuite/gas/i386/vpclmulqdq-intel.d: Ditto. * testsuite/gas/i386/vpclmulqdq.d: Ditto. * testsuite/gas/i386/vpclmulqdq.s: Ditto. * testsuite/gas/i386/x86-64-avx512f_vpclmulqdq-intel.d: Ditto. * testsuite/gas/i386/x86-64-avx512f_vpclmulqdq-wig.s: Ditto. * testsuite/gas/i386/x86-64-avx512f_vpclmulqdq-wig1-intel.d: Ditto. * testsuite/gas/i386/x86-64-avx512f_vpclmulqdq-wig1.d: Ditto. * testsuite/gas/i386/x86-64-avx512f_vpclmulqdq.d: Ditto. * testsuite/gas/i386/x86-64-avx512f_vpclmulqdq.s: Ditto. * testsuite/gas/i386/x86-64-avx512vl_vpclmulqdq-intel.d: Ditto. * testsuite/gas/i386/x86-64-avx512vl_vpclmulqdq-wig.s: Ditto. * testsuite/gas/i386/x86-64-avx512vl_vpclmulqdq-wig1-intel.d: Ditto. * testsuite/gas/i386/x86-64-avx512vl_vpclmulqdq-wig1.d: Ditto. * testsuite/gas/i386/x86-64-avx512vl_vpclmulqdq.d: Ditto. * testsuite/gas/i386/x86-64-avx512vl_vpclmulqdq.s: Ditto. * testsuite/gas/i386/x86-64-vpclmulqdq-intel.d: Ditto. * testsuite/gas/i386/x86-64-vpclmulqdq.d: Ditto. * testsuite/gas/i386/x86-64-vpclmulqdq.s: Ditto. opcodes/ * i386-dis.c (enum): Add PREFIX_EVEX_0F3A44. (enum): Remove VEX_LEN_0F3A44_P_2. (vex_len_table): Ditto. (enum): Remove VEX_W_0F3A44_P_2. (vew_w_table): Ditto. (prefix_table): Adjust instructions (see prefixes above). * i386-dis-evex.h (evex_table): Add new instructions (see prefixes above). * i386-gen.c (cpu_flag_init): Add VPCLMULQDQ. (bitfield_cpu_flags): Ditto. * i386-opc.h (enum): Ditto. (i386_cpu_flags): Ditto. (CpuUnused): Comment out to avoid zero-width field problem. * i386-opc.tbl (vpclmulqdq): New instruction. * i386-init.h: Regenerate. * i386-tbl.h: Ditto.
2017-10-23Enable Intel VAES instructions.Igor Tsimbalist7-5576/+5902
Intel has disclosed a set of new instructions. The spec is https://software.intel.com/sites/default/files/managed/c5/15/architecture-instruction-set-extensions-programming-reference.pdf gas/ * config/tc-i386.c (cpu_arch): Add VAES. * doc/c-i386.texi: Document VAES. * testsuite/gas/i386/i386.exp: Run VAES tests. * testsuite/gas/i386/avx512f_vaes-intel.d: New test. * testsuite/gas/i386/avx512f_vaes-wig.s: Ditto. * testsuite/gas/i386/avx512f_vaes-wig1-intel.d: Ditto. * testsuite/gas/i386/avx512f_vaes-wig1.d: Ditto. * testsuite/gas/i386/avx512f_vaes.d: Ditto. * testsuite/gas/i386/avx512f_vaes.s: Ditto. * testsuite/gas/i386/avx512vl_vaes-intel.d: Ditto. * testsuite/gas/i386/avx512vl_vaes-wig.s: Ditto. * testsuite/gas/i386/avx512vl_vaes-wig1-intel.d: Ditto. * testsuite/gas/i386/avx512vl_vaes-wig1.d: Ditto. * testsuite/gas/i386/avx512vl_vaes.d: Ditto. * testsuite/gas/i386/avx512vl_vaes.s: Ditto. * testsuite/gas/i386/vaes-intel.d: Ditto. * testsuite/gas/i386/vaes.d: Ditto. * testsuite/gas/i386/vaes.s: Ditto. * testsuite/gas/i386/x86-64-avx512f_vaes-intel.d: Ditto. * testsuite/gas/i386/x86-64-avx512f_vaes-wig.s: Ditto. * testsuite/gas/i386/x86-64-avx512f_vaes-wig1-intel.d: Ditto. * testsuite/gas/i386/x86-64-avx512f_vaes-wig1.d: Ditto. * testsuite/gas/i386/x86-64-avx512f_vaes.d: Ditto. * testsuite/gas/i386/x86-64-avx512f_vaes.s: Ditto. * testsuite/gas/i386/x86-64-avx512vl_vaes-intel.d: Ditto. * testsuite/gas/i386/x86-64-avx512vl_vaes-wig.s: Ditto. * testsuite/gas/i386/x86-64-avx512vl_vaes-wig1-intel.d: Ditto. * testsuite/gas/i386/x86-64-avx512vl_vaes-wig1.d: Ditto. * testsuite/gas/i386/x86-64-avx512vl_vaes.d: Ditto. * testsuite/gas/i386/x86-64-avx512vl_vaes.s: Ditto. * testsuite/gas/i386/x86-64-vaes-intel.d: Ditto. * testsuite/gas/i386/x86-64-vaes.d: Ditto. * testsuite/gas/i386/x86-64-vaes.s: Ditto. opcodes/ * i386-dis.c (enum): Add PREFIX_EVEX_0F38DC, PREFIX_EVEX_0F38DD, PREFIX_EVEX_0F38DE, PREFIX_EVEX_0F38DF. (enum): Remove VEX_LEN_0F38DC_P_2, VEX_LEN_0F38DD_P_2, VEX_LEN_0F38DE_P_2, VEX_LEN_0F38DF_P_2. (vex_len_table): Ditto. (enum): Remove VEX_W_0F38DC_P_2, VEX_W_0F38DD_P_2, VEX_W_0F38DE_P_2, VEX_W_0F38DF_P_2. (vew_w_table): Ditto. (prefix_table): Adjust instructions (see prefixes above). * i386-dis-evex.h (evex_table): Add new instructions (see prefixes above). * i386-gen.c (cpu_flag_init): Add VAES. (bitfield_cpu_flags): Ditto. * i386-opc.h (enum): Ditto. (i386_cpu_flags): Ditto. * i386-opc.tbl (vaes{enc,dec}{last,}): New instructions. * i386-init.h: Regenerate. * i386-tbl.h: Ditto.
2017-10-23Enable Intel GFNI instructions.Igor Tsimbalist7-5443/+6011
Intel has disclosed a set of new instructions. The spec is https://software.intel.com/sites/default/files/managed/c5/15/architecture-instruction-set-extensions-programming-reference.pdf gas/ * config/tc-i386.c (cpu_arch): Add .gfni. * doc/c-i386.texi: Document .gfni. * testsuite/gas/i386/i386.exp: Add GFNI tests. * testsuite/gas/i386/avx.s: New GFNI test. * testsuite/gas/i386/x86-64-avx.s: Likewise. * testsuite/gas/i386/avx.d: Adjust. * testsuite/gas/i386/avx-intel.d: Likewise * testsuite/gas/i386/ilp32/x86-64-avx-intel.d: Likewise. * testsuite/gas/i386/ilp32/x86-64-avx.d: Likewise. * testsuite/gas/i386/avx512f_gfni-intel.d: New test. * testsuite/gas/i386/avx512f_gfni.d: Likewise. * testsuite/gas/i386/avx512f_gfni.s: Likewise. * testsuite/gas/i386/avx512vl_gfni-intel.d: Likewise. * testsuite/gas/i386/avx512vl_gfni.d: Likewise. * testsuite/gas/i386/avx512vl_gfni.s: Likewise. * testsuite/gas/i386/gfni-intel.d: Likewise. * testsuite/gas/i386/gfni.d: Likewise. * testsuite/gas/i386/gfni.s: Likewise. * testsuite/gas/i386/x86-64-avx512f_gfni-intel.d: Likewise. * testsuite/gas/i386/x86-64-avx512f_gfni.d: Likewise. * testsuite/gas/i386/x86-64-avx512f_gfni.s: Likewise. * testsuite/gas/i386/x86-64-avx512vl_gfni-intel.d: Likewise. * testsuite/gas/i386/x86-64-avx512vl_gfni.d: Likewise. * testsuite/gas/i386/x86-64-avx512vl_gfni.s: Likewise. * testsuite/gas/i386/x86-64-avx_gfni-intel.d: Likewise. * testsuite/gas/i386/x86-64-avx_gfni.d: Likewise. * testsuite/gas/i386/x86-64-avx_gfni.s: Likewise. * testsuite/gas/i386/x86-64-gfni-intel.d: Likewise. * testsuite/gas/i386/x86-64-gfni.d: Likewise. * testsuite/gas/i386/x86-64-gfni.s: Likewise. opcodes/ * i386-dis.c (enum): Add PREFIX_0F38CF, PREFIX_0F3ACE, PREFIX_0F3ACF, PREFIX_VEX_0F38CF, PREFIX_VEX_0F3ACE, PREFIX_VEX_0F3ACF, PREFIX_EVEX_0F38CF, PREFIX_EVEX_0F3ACE, PREFIX_EVEX_0F3ACF. (enum): Add VEX_W_0F38CF_P_2, VEX_W_0F3ACE_P_2, VEX_W_0F3ACF_P_2, EVEX_W_0F3ACE_P_2, EVEX_W_0F3ACF_P_2. (prefix_table): Updated (see prefixes above). (three_byte_table): Likewise. (vex_w_table): Likewise. * i386-dis-evex.h: Likewise. * i386-gen.c (cpu_flag_init): Add CPU_GFNI_FLAGS, CpuGFNI. (cpu_flags): Add CpuGFNI. * i386-opc.h (enum): Add CpuGFNI. (i386_cpu_flags): Add cpugfni. * i386-opc.tbl: Add Intel GFNI instructions. * i386-init.h: Regenerate. * i386-tbl.h: Likewise.
2017-10-23Enable Intel AVX512_VBMI2 instructions.Igor Tsimbalist7-5389/+6652
Intel has disclosed a set of new instructions. The spec is https://software.intel.com/sites/default/files/managed/c5/15/architecture-instruction-set-extensions-programming-reference.pdf gas/ * config/tc-i386.c (cpu_arch): Add .avx512_vbmi2. (cpu_noarch): noavx512_vbmi2. * doc/c-i386.texi: Document .avx512_vbmi2, noavx512_vbmi2. * testsuite/gas/i386/i386.exp: Add AVX512_VBMI2 tests. * testsuite/gas/i386/avx512vbmi2-intel.d: New test. * testsuite/gas/i386/avx512vbmi2.d: Likewise. * testsuite/gas/i386/avx512vbmi2.s: Likewise. * testsuite/gas/i386/avx512vbmi2_vl-intel.d: Likewise. * testsuite/gas/i386/avx512vbmi2_vl.d: Likewise. * testsuite/gas/i386/avx512vbmi2_vl.s: Likewise. * testsuite/gas/i386/x86-64-avx512vbmi2-intel.d: Likewise. * testsuite/gas/i386/x86-64-avx512vbmi2.d: Likewise. * testsuite/gas/i386/x86-64-avx512vbmi2.s: Likewise. * testsuite/gas/i386/x86-64-avx512vbmi2_vl-intel.d: Likewise. * testsuite/gas/i386/x86-64-avx512vbmi2_vl.d: Likewise. * testsuite/gas/i386/x86-64-avx512vbmi2_vl.s: Likewise. opcodes/ * i386-dis.c (enum): Add b_scalar_mode, w_scalar_mode. Define EXbScalar and EXwScalar for OP_EX. (enum): Add PREFIX_EVEX_0F3862, PREFIX_EVEX_0F3863, PREFIX_EVEX_0F3870, PREFIX_EVEX_0F3871, PREFIX_EVEX_0F3872, PREFIX_EVEX_0F3873, PREFIX_EVEX_0F3A70, PREFIX_EVEX_0F3A71, PREFIX_EVEX_0F3A72, PREFIX_EVEX_0F3A73. (enum): Add EVEX_W_0F3862_P_2, EVEX_W_0F3863_P_2, EVEX_W_0F3870_P_2, EVEX_W_0F3871_P_2, EVEX_W_0F3872_P_2, EVEX_W_0F3873_P_2, EVEX_W_0F3A70_P_2, EVEX_W_0F3A71_P_2, EVEX_W_0F3A72_P_2, EVEX_W_0F3A73_P_2. (intel_operand_size): Handle b_scalar_mode and w_scalar_mode. (OP_E_memory): Likewise. * i386-dis-evex.h: Updated. * i386-gen.c (cpu_flag_init): Add CPU_AVX512_VBMI2, CPU_ANY_AVX512_VBMI2_FLAGS. Update CPU_ANY_AVX512F_FLAGS. (cpu_flags): Add CpuAVX512_VBMI2. * i386-opc.h (enum): Add CpuAVX512_VBMI2. (i386_cpu_flags): Add cpuavx512_vbmi2. * i386-opc.tbl: Add Intel AVX512_VBMI2 instructions. * i386-init.h: Regenerate. * i386-tbl.h: Likewise.
2017-10-18[Visium] Disassemble the operands of the stop instruction.Eric Botcazou2-1/+5
binutils/ * MAINTAINERS: Add myself as Visium maintainer. opcodes/ * visium-dis.c (disassem_class1) <case 0>: Print the operands.
2017-10-12FT32: support for FT32B processor - part 1James Bowman3-22/+49
FT32B is a new FT32 family member. It has a code compression scheme, which requires the use of linker relaxations. The change is quite large, so submission is in several parts. Part 1 adds a 15-bit instruction field, and CPU-specific functions for the code compression that are used in binutils and GDB. bfd/ChangeLog: 2017-10-12 James Bowman <james.bowman@ftdichip.com> * bfd-in2.h: Regenerate. * libbfd.h: Regenerate. * elf32-ft32.c: Add HOWTO R_FT32_15. * reloc.c: Add BFD_RELOC_FT32_15. gas/ChangeLog: 2017-10-12 James Bowman <james.bowman@ftdichip.com> * config/tc-ft32.c (md_assemble): Replace FT32_FLD_K8 with K15. (md_apply_fix, tc_gen_reloc): Add BFD_RELOC_FT32_15. include/ChangeLog: 2017-10-12 James Bowman <james.bowman@ftdichip.com> * elf/ft32.h: Add R_FT32_15. * opcode/ft32.h: Replace FT32_FLD_K8 with K15. (ft32_shortcode, sc_compar, ft32_split_shortcode, ft32_merge_shortcode, ft32_merge_shortcode): New functions. opcodes/ChangeLog: 2017-10-12 James Bowman <james.bowman@ftdichip.com> * opcodes/ft32-dis.c (print_insn_ft32): Replace FT32_FLD_K8 with K15. * opcodes/ft32-opc.c (ft32_opc_info): Replace FT32_FLD_K8 with K15. Add jmpix pattern. sim/ChangeLog: 2017-10-12 James Bowman <james.bowman@ftdichip.com> * sim/ft32/interp.c (step_once): Replace FT32_FLD_K8 with K15.
2017-10-09S/390: Sync with latest POP - 3 new instructionsAndreas Krebbel2-0/+8
prno, tpei, and irbm are missing in the optable. gas/ChangeLog: 2017-10-09 Andreas Krebbel <krebbel@linux.vnet.ibm.com> * testsuite/gas/s390/zarch-arch12.d (prno, tpei, irbm): New instructions added. * testsuite/gas/s390/zarch-arch12.s: Likewise. * testsuite/gas/s390/zarch-z13.d: Rename ppno to prno. opcodes/ChangeLog: 2017-10-09 Andreas Krebbel <krebbel@linux.vnet.ibm.com> * s390-opc.txt (prno, tpei, irbm): New instructions added.
2017-10-09S/390: Sync with IBM z14 POP - SI_RD formatAndreas Krebbel3-4/+13
The recent POP adjusted a few of the instruction formats. This patch adjusts our optable accordingly. No user visible change - hopefully. opcodes/ChangeLog: 2017-10-09 Heiko Carstens <heiko.carstens@de.ibm.com> * s390-opc.c (INSTR_SI_RD): New macro. (INSTR_S_RD): Adjust example instruction. * s390-opc.txt (lpsw, ssm, ts): Change S_RD instruction format to SI_RD.
2017-10-01Add new mnemonics for VLE multiple load instructionsAlexander Fedotov2-0/+15
opcodes/ * ppc-opc.c (vle_opcodes): Add e_lmvsprw, e_lmvgprw, e_lmvsrrw, e_lmvcsrrw and e_lmvcsrrw as official mnemonics for VLE multimple load/store instructions. Old e_ldm* variants are kept as aliases. Add missing e_lmvmcsrrw and e_stmvmcsrrw. gas/ * testsuite/gas/ppc/vle-mult-ld-st-insns.s: New file: Tests the support for the VLE multiple load/store instructions. * testsuite/gas/ppc/vle-mult-ld-st-insns.d: New file: Test driver. * testsuite/gas/ppc/ppc.exp: Run it.
2017-09-27Add support for the new names of the RISC-V fmv.x.s and fmv.s.x ↵Nick Clifton2-0/+11
instructions, vis: fmv.x.w and fmv.w.x. PR 22179 opcodes * riscv-opc.c (riscv_opcodes): Add fmv.x.w and fmv.w.x as the new names for the fmv.x.s and fmv.s.x instructions respectively. gas * testsuite/gas/riscv/fmv.x.s: New file: Tests the support for the renamed fmv.x.s and fmv.s.x instructions. * testsuite/gas/riscv/fmv.x.d: New file: Test driver.
generated by cgit v1.1 at 2024-11-23 19:43:08 +0000