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AgeCommit message (Expand)AuthorFilesLines
2015-12-31opcodes/arc: Support dmb instruction with no operandsAndrew Burgess2-0/+8
2015-12-30Fix assorted ChangeLog errorsAlan Modra1-9/+8
2015-12-24Add assembler support for ARMv8-M BaselineThomas Preud'homme2-13/+21
2015-12-24Add assembler support for ARMv8-M MainlineThomas Preud'homme2-12/+25
2015-12-22RXv2 support updateYoshinori Sato3-8/+17
2015-12-15Add support for RX V2 Instruction SetYoshinori Sato4-1280/+2862
2015-12-14[AArch64][PATCH 14/14] Support FP16 Adv.SIMD Scalar Shift By Immediate instru...Matthew Wahab5-1021/+1052
2015-12-14[AArch64][PATCH 13/14] Support FP16 Adv.SIMD Shift By Immediate instructions.Matthew Wahab5-1259/+1288
2015-12-14[AArch64][PATCH 12/14] Support FP16 Adv.SIMD Scalar Pairwise instructions.Matthew Wahab5-1101/+1181
2015-12-14[AArch64][PATCH 11/14] Add support for the 2H vector type.Matthew Wahab3-1/+15
2015-12-14[AArch64][PATCH 9/14] Support FP16 Adv.SIMD Modified Immediate instructions.Matthew Wahab5-1535/+1555
2015-12-14[AArch64][PATCH 8/14] Support FP16 Adv.SIMD Across Lanes instructions.Matthew Wahab5-1660/+1728
2015-12-14[AArch64][PATCH 7/14] Support FP16 Scalar Indexed Element instructions.Matthew Wahab5-1215/+1275
2015-12-14[AArch64][PATCH 6/14] Support FP16 Vector Indexed Element instructions.Matthew Wahab5-1580/+1648
2015-12-14[AArch64][PATCH 5/14] Support FP16 Scalar Two Register Misc. instructions.Matthew Wahab5-1238/+1522
2015-12-14[AArch64][PATCH 4/14] Support FP16 Vector Two Register Misc. instructions.Matthew Wahab5-1773/+2169
2015-12-14[AArch64][PATCH 3/14] Support ARMv8.2 FP16 Scalar Three Same instructions.Matthew Wahab5-1081/+1207
2015-12-14[AArch64][PATCH 2/14] Support ARMv8.2 FP16 Vector Three Same instructions.Matthew Wahab5-1363/+1693
2015-12-14[AArch64][PATCH 1/14] Support ARMv8.2 FP16 Adv.SIMD instructions.Matthew Wahab2-0/+8
2015-12-14[AArch64] Fix errors rebasing the ARMv8.2 AT and system registers patchMatthew Wahab2-6/+15
2015-12-12Enable 2 operand form of powerpc mfcr with -manyAlan Modra2-3/+8
2015-12-11[AArch64][Patch 5/5] Add instruction PSB CSYNCMatthew Wahab5-25/+44
2015-12-11[AArch64][Patch 4/5] Support HINT aliases taking operands.Matthew Wahab8-4/+68
2015-12-11[AArch64][Patch 3/5] Adjust maximum number of instruction aliases.Matthew Wahab2-2/+6
2015-12-11[AArch64][Patch 2/5] Add Statistical Profiling Extension system registers.Matthew Wahab2-1/+39
2015-12-10[Aarch64] Support ARMv8.2 AT instructionsMatthew Wahab2-0/+14
2015-12-10[AArch64][PATCH 2/2] Support ARMv8.2 DC CVAP instruction.Matthew Wahab2-0/+21
2015-12-10[AArch64][PATCH 1/2] Add support for ARMv8.2 DC CVAP instruction.Matthew Wahab3-47/+74
2015-12-10[AArch64][binutils] Add support for ARMv8.2 PSTATE.UAO.Matthew Wahab2-0/+21
2015-12-10[AArch64][PATCH 2/2] Add RAS system registers.Matthew Wahab2-0/+45
2015-12-10[AArch64][PATCH 1/2] Add support for RAS instruction ESB.Matthew Wahab4-24/+38
2015-12-09Implement Intel OSPKE instructionsH.J. Lu7-5305/+5384
2015-12-08rl78: Enable MULU for all ISAs.DJ Delorie3-162/+165
2015-12-07Reorder some power9 insnsAlan Modra2-11/+16
2015-12-04Fix failures in the GAS testsuite for the ARC architecture.Claudiu Zissulescu4-106/+162
2015-12-02Fix ldah being disassembled as ldaexhAndre Vieira2-1/+6
2015-11-27[AArch64][PATCH 3/3] Add floating-point FP16 instructionsMatthew Wahab5-682/+964
2015-11-27[AArch64][PATCH 2/3] Adjust a utility function for floating point values.Matthew Wahab2-7/+37
2015-11-27[AArch64][PATCH 1/3] Support ARMv8.2 FP16 floating point instructions.Matthew Wahab2-0/+8
2015-11-27[AArch64] Add ARMv8.2 instruction alias REV64.Matthew Wahab5-768/+785
2015-11-27[AArch64] Add ARMv8.2 instructions BFC and REV64.Matthew Wahab8-861/+967
2015-11-27[AArch64] Let aliased instructions be their preferred form.Matthew Wahab5-2/+202
2015-11-27[Aarch64] Support an ARMv8.2 system register.Matthew Wahab2-0/+11
2015-11-23opcodes: handle mach-o for thumb/arm disambiguation.Tristan Gingold2-0/+12
2015-11-20[AArch64] Add support for ARMv8.1 Virtulization Host Extensions.Matthew Wahab2-0/+78
2015-11-20Remove a if-clause that is redundant because the same test has been performed...Nick Clifton2-4/+5
2015-11-20Update translations.Nick Clifton2-317/+1153
2015-11-19[AArch64] Reject invalid immediate operands to MSR PANMatthew Wahab2-0/+13
2015-11-17Fix the disassembly of conditional instructions will illegal condition select...Nick Clifton2-1/+6
2015-11-14Bump version to 2.26.51Tristan Gingold2-10/+14
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