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AgeCommit message (Expand)AuthorFilesLines
2017-11-07opcodes/arc: Fix incorrect insn_class for some nps insnsAndrew Burgess2-4/+8
2017-11-07ngettext supportAlan Modra2-16/+35
2017-11-03[ARC] Force the disassam to use the hexadecimal number for printingclaziss2-1/+21
2017-11-03[ARC] Sync opcode data base.claziss3-1588/+3455
2017-10-25PR22348, conflicting global vars in crx and cr16Alan Modra4-20/+33
2017-10-24RISC-V: Fix disassembly of c.addi4spn, c.addi16sp, c.lui when imm=0Andrew Waterman2-7/+33
2017-10-23Add missing ChangeLog entriesIgor Tsimbalist1-0/+110
2017-10-23Fix the master due to bad regenerated filesIgor Tsimbalist3-5469/+11545
2017-10-23Enable Intel AVX512_BITALG instructions.Igor Tsimbalist5-3/+51
2017-10-23Enable Intel AVX512_VNNI instructions.Igor Tsimbalist5-6/+48
2017-10-23Enable Intel VPCLMULQDQ instruction.Igor Tsimbalist5-14/+30
2017-10-23Enable Intel VAES instructions.Igor Tsimbalist7-5576/+5902
2017-10-23Enable Intel GFNI instructions.Igor Tsimbalist7-5443/+6011
2017-10-23Enable Intel AVX512_VBMI2 instructions.Igor Tsimbalist7-5389/+6652
2017-10-18[Visium] Disassemble the operands of the stop instruction.Eric Botcazou2-1/+5
2017-10-12FT32: support for FT32B processor - part 1James Bowman3-22/+49
2017-10-09S/390: Sync with latest POP - 3 new instructionsAndreas Krebbel2-0/+8
2017-10-09S/390: Sync with IBM z14 POP - SI_RD formatAndreas Krebbel3-4/+13
2017-10-01Add new mnemonics for VLE multiple load instructionsAlexander Fedotov2-0/+15
2017-09-27Add support for the new names of the RISC-V fmv.x.s and fmv.s.x instructions,...Nick Clifton2-0/+11
2017-09-26Allow the macw and macl instructions to be used on CPUs that have emacs support.Nick Clifton2-0/+20
2017-09-25Initialize 'imm' on opcodes/aarch64-opc.c:expand_fp_imm (and fix breakage on ...Sergio Durigan Junior2-1/+5
2017-09-11nds32: Rename __BIT() to N32_BIT().Kuan-Lin Chen4-40/+46
2017-09-09x86: Remove restriction on NOTRACK prefix positionH.J. Lu2-16/+8
2017-08-31Add updated French translations for opcodes and gprofNick Clifton2-418/+786
2017-08-30FT32: improve disassembly readabilityJames Bowman2-7/+17
2017-08-24[PowerPC VLE] Add SPE2 and EFS2 instructions supportAlexander Fedotov3-12/+1239
2017-08-23ppc-opc.c formattingAlan Modra2-1089/+1101
2017-08-22RISC-V: Mark "c.nop" as an aliasPalmer Dabbelt2-1/+5
2017-08-21[PowerPC VLE] Add LSP (Lightweight Signal Processing) instruction supportAlexander Fedotov3-6/+920
2017-08-09[ARM] Don't warn on REG_SP when used in CRC32 instructionsJiong Wang2-11/+13
2017-08-07Mark big and mach with ATTRIBUTE_UNUSEDH.J. Lu2-1/+8
2017-08-07GDB/opcodes: Remove arch/mach/endian disassembler assertionsMaciej W. Rozycki2-12/+6
2017-07-25Fix typos in error and option messages in OPCODES library.Nick Clifton3-36/+75
2017-07-24[AArch64] Fix the bit pattern order in the comments in auto-generated fileJiong Wang3-1689/+1699
2017-07-21S/390: Support z14 as CPU name.Andreas Krebbel2-1/+7
2017-07-20Update the German translation for the opcodes library.Nick Clifton2-466/+890
2017-07-19[ARC] Add SecureShield AUX registersclaziss2-0/+21
2017-07-19[ARC] Add SJLI instruction.Claudiu Zissulescu3-1/+27
2017-07-19[ARC] Add JLI support.John Eric Martin4-2/+17
2017-07-18Fix spelling typos.Yuri Chornovian3-2/+8
2017-07-14binutils/objdump: Fix disassemble for huge elf sectionsRavi Bangoria2-3/+8
2017-07-12Update PO filesAlan Modra16-875/+2049
2017-07-11Mark generated cgen files read-onlyAlan Modra96-8/+211
2017-07-07Move print_insn_XXX to an opcodes internal header, againAlan Modra4-3/+9
2017-07-05X86: Disassemble primary opcode map's group 2 ModRM.reg == 6 aliases correctlyBorislav Petkov2-6/+10
2017-07-05Fixup changelog entries for previous commitRamana Radhakrishnan1-0/+5
2017-07-04[Patch ARM] Support MVFR2 VFP Coprocessor register for ARMv8-ARamana Radhakrishnan1-0/+4
2017-07-04Regenerate configure.Tristan Gingold2-10/+14
2017-07-03Regenerate pot files.Tristan Gingold2-133/+150
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