| Age | Commit message (Expand) | Author | Files | Lines |
|---|
| 2016-09-21 | [AArch64][SVE 27/32] Add SVE integer immediate operands | Richard Sandiford | 11 | -100/+647 |
| 2016-09-21 | [AArch64][SVE 26/32] Add SVE MUL VL addressing modes | Richard Sandiford | 10 | -38/+290 |
| 2016-09-21 | [AArch64][SVE 25/32] Add support for SVE addressing modes | Richard Sandiford | 11 | -41/+739 |
| 2016-09-21 | [AArch64][SVE 24/32] Add AARCH64_OPND_SVE_PATTERN_SCALED | Richard Sandiford | 11 | -17/+126 |
| 2016-09-21 | [AArch64][SVE 23/32] Add SVE pattern and prfop operands | Richard Sandiford | 7 | -11/+127 |
| 2016-09-21 | [AArch64][SVE 22/32] Add qualifiers for merging and zeroing predication | Richard Sandiford | 2 | -0/+13 |
| 2016-09-21 | [AArch64][SVE 21/32] Add Zn and Pn registers | Richard Sandiford | 11 | -1/+291 |
| 2016-09-21 | [AArch64][SVE 20/32] Add support for tied operands | Richard Sandiford | 3 | -16/+41 |
| 2016-09-21 | [AArch64][SVE 19/32] Refactor address-printing code | Richard Sandiford | 2 | -36/+65 |
| 2016-09-21 | [AArch64][SVE 18/32] Tidy definition of aarch64-opc.c:int_reg | Richard Sandiford | 2 | -18/+17 |
| 2016-09-21 | [AArch64][SVE 17/32] Add a prefix parameter to print_register_list | Richard Sandiford | 2 | -13/+21 |
| 2016-09-21 | [AArch64][SVE 16/32] Use specific insert/extract methods for fpimm | Richard Sandiford | 8 | -6/+40 |
| 2016-09-21 | [AArch64][SVE 15/32] Add {insert,extract}_all_fields helpers | Richard Sandiford | 3 | -14/+50 |
| 2016-09-21 | [AArch64][SVE 14/32] Make aarch64_logical_immediate_p take an element size | Richard Sandiford | 3 | -29/+39 |
| 2016-09-21 | [AArch64][SVE 13/32] Add an F_STRICT flag | Richard Sandiford | 2 | -1/+14 |
| 2016-09-21 | [AArch64][SVE 02/32] Avoid hard-coded limit in indented_print | Richard Sandiford | 2 | -5/+5 |
| 2016-09-16 | [ARC] Disassemble correctly extension instructions. | Claudiu Zissulescu | 2 | -3/+7 |
| 2016-09-14 | Modify POWER9 support to match final ISA 3.0 documentation. | Peter Bergner | 2 | -22/+23 |
| 2016-09-14 | Stop the ARC disassembler from seg-faulting if initialised without a BFD pres... | Anton Kolesov | 2 | -3/+12 |
| 2016-09-12 | S/390: Add alternate processor names. | Andreas Krebbel | 2 | -9/+21 |
| 2016-09-12 | S/390: Fix kmctr instruction type. | Patrick Steuer | 2 | -1/+5 |
| 2016-09-07 | X86: Allow additional ISAs for IAMCU in assembler | H.J. Lu | 3 | -9/+5 |
| 2016-08-30 | Fixed issue with NULL pointer access on header var. | Cupertino Miranda | 2 | -1/+8 |
| 2016-08-26 | opcodes, gas: fix mnemonic of sparc camellia_fl | Jose E. Marchesi | 2 | -1/+6 |
| 2016-08-26 | Add missing ARMv8-M special registers | Thomas Preud'homme | 2 | -14/+29 |
| 2016-08-24 | X86: Add ptwrite instruction | H.J. Lu | 7 | -5329/+5392 |
| 2016-08-24 | [ARC] C++ compatibility for arc-dis.h | Anton Kolesov | 2 | -0/+13 |
| 2016-08-23 | [AArch64] Add V8_2_INSN macro | Richard Sandiford | 2 | -2/+9 |
| 2016-08-23 | [AArch64] Make more use of CORE/FP/SIMD_INSN | Richard Sandiford | 2 | -67/+72 |
| 2016-08-23 | [AArch64] Add OP parameter to aarch64-tbl.h macros | Richard Sandiford | 2 | -722/+727 |
| 2016-08-01 | Fix some PowerPC VLE BFD issues and add some PowerPC VLE instructions. | Andrew Jenner | 3 | -2/+40 |
| 2016-07-27 | MIPS/GAS: Implement microMIPS branch/jump compaction | Maciej W. Rozycki | 2 | -7/+21 |
| 2016-07-27 | Begin implementing ARC NPS-400 Accelerator instructions | Graham Markall | 5 | -32/+283 |
| 2016-07-21 | Set BFD_VERSION to 2.27.51 | H.J. Lu | 2 | -10/+14 |
| 2016-07-20 | Add support to the ARC disassembler for selecting instruction classes. | Claudiu Zissulescu | 3 | -127/+364 |
| 2016-07-13 | MIPS/opcodes: Address issues with NAL disassembly | Maciej W. Rozycki | 2 | -1/+6 |
| 2016-07-13 | opcodes,gas: support for the ldtxa SPARC instructions. | Jose E. Marchesi | 2 | -0/+42 |
| 2016-07-08 | FT32: adjust disassembly opcode match fields | jamesbowman | 2 | -2/+7 |
| 2016-07-01 | x86: allow suffix-less movzw and 64-bit movzb | Jan Beulich | 3 | -80/+14 |
| 2016-07-01 | x86: remove stray instruction attributes | Jan Beulich | 3 | -88/+103 |
| 2016-07-01 | x86/Intel: fix operand checking for MOVSD | Jan Beulich | 3 | -4/+9 |
| 2016-06-30 | Fix typo in comment | Yao Qi | 2 | -1/+5 |
| 2016-06-28 | [AArch64] Make register indices be full 64-bit values | Richard Sandiford | 2 | -2/+19 |
| 2016-06-25 | remove a few sentinals | Trevor Saunders | 3 | -8/+13 |
| 2016-06-23 | [ARC] Misc minor edits/fixes | Graham Markall | 2 | -3/+6 |
| 2016-06-22 | Add support for yet some more new ISA 3.0 instructions. | Peter Bergner | 2 | -5/+54 |
| 2016-06-22 | addmore extern C | Trevor Saunders | 2 | -0/+12 |
| 2016-06-21 | Arc assembler: Convert nps400 from a machine type to an extension. | Graham Markall | 4 | -198/+208 |
| 2016-06-17 | opcodes,gas: sparc: fix rdasr,wrasr,rdpr,wrpr,rdhpr,wrhpr insns. | Jose E. Marchesi | 3 | -52/+146 |
| 2016-06-17 | opcodes,gas: adjust sparc insns and make GAS aware of it | Jose E. Marchesi | 2 | -170/+175 |
