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2017-06-23RISC-V: Fix SLTI disassemblyAndrew Waterman2-2/+7
2017-06-21x86: CET v2.0: Update incssp and setssbsyH.J. Lu4-25/+41
2017-06-21x86: CET v2.0: Rename savessp to saveprevsspH.J. Lu4-3/+9
2017-06-21x86: CET v2.0: Update NOTRACK prefixH.J. Lu2-8/+13
2017-06-19Prevent address violation when attempting to disassemble a corrupt score binary.Nick Clifton2-0/+6
2017-06-17Regen rx-decode.cAlan Modra2-712/+716
2017-06-15i386-dis: Check valid bnd registerH.J. Lu2-0/+16
2017-06-15Prevent address violation problem when disassembling corrupt aarch64 binary.Nick Clifton2-0/+9
2017-06-15Fix address violation when disassembling a corrupt RL78 binary.Nick Clifton3-411/+424
2017-06-15Prevent invalid array accesses when disassembling a corrupt bfin binary.Nick Clifton2-4/+12
2017-06-14Fix seg-fault when trying to disassemble a corrupt score binary.Nick Clifton2-1/+7
2017-06-14Don't use print_insn_XXX in GDBYao Qi7-5/+26
2017-06-14Fix address violation problems when disassembling a corrupt RX binary.Nick Clifton3-20/+37
2017-06-14[opcodes][arm] Remove bogus entry added by accident in former patchAndre Vieira2-2/+4
2017-06-01S/390: idte/ipte fixesAndreas Krebbel1-5/+2
2017-05-30[ARC] Allow CPU to be enforced via disassemble_info optionsAnton Kolesov2-26/+114
2017-05-30S/390: Fix instruction types of csdtr and csxtrAndreas Krebbel2-2/+6
2017-05-30S/390: Add missing operand to tb instructionAndreas Krebbel1-1/+1
2017-05-30S/390: Add ipte/idte variants with optional operandsAndreas Krebbel2-1/+4
2017-05-30S/390: Improve error checking for optional operandsAndreas Krebbel2-3/+16
2017-05-24Move print_insn_XXX to an opcodes internal headerYao Qi70-68/+198
2017-05-24Use disassemble.c:disassembler select rl78 disassemblerYao Qi2-1/+10
2017-05-24Refactor disassembler selectionYao Qi2-15/+31
2017-05-22x86: Add NOTRACK prefix supportH.J. Lu6-10652/+10726
2017-05-19binutils: support for the SPARC M8 processorJose E. Marchesi3-14/+266
2017-05-18Don't compare boolean values against TRUE or FALSEAlan Modra5-14/+20
2017-05-17S/390: Fix arch level of pckmo instruction.Andreas Krebbel1-1/+1
2017-05-15MIPS16e2: Add MIPS16e2 ASE supportMaciej W. Rozycki3-16/+198
2017-05-15MIPS/opcodes: Remove an incorrect MT ASE reference in MFC0/MTC0 decodingMaciej W. Rozycki2-1/+6
2017-05-12MIPS16/opcodes: Make the handling of BREAK and SDBBP consistentMaciej W. Rozycki2-1/+9
2017-05-12MIPS/opcodes: Mark descriptive SYNC mnemonics as aliasesMaciej W. Rozycki3-14/+22
2017-05-10[ARC] Object attributes.Claudiu Zissulescu4-29/+37
2017-05-04RISC-V: Fix disassemble for c.li, c.andi and c.addiwKito Cheng2-0/+5
2017-05-02RISC-V: Change CALL macro to use ra as the temporary address registerMichael Clark2-1/+6
2017-05-02MIPS16/opcodes: Keep the LSB of PC-relative offsets in disassemblyMaciej W. Rozycki2-3/+9
2017-05-02Fix value in comment of disassembled ARM type A opcodes.Bernd Edlinger2-2/+6
2017-04-25[ARC] Enhance enter/leave mnemonics.Claudiu Zissulescu4-4/+44
2017-04-25[ARC] Prefer NOP instead of MOV 0,0Claudiu Zissulescu2-3/+7
2017-04-25MIPS16/opcodes: Add `-M no-aliases' disassembler option help textMaciej W. Rozycki2-0/+8
2017-04-25MIPS16/opcodes: Annotate instruction aliasesMaciej W. Rozycki2-5/+13
2017-04-24Fix snafu in aarch64 opcodes debugging statement.Tamar Christina2-2/+7
2017-04-22PowerPC VLE insn set additionsAlan Modra2-7/+19
2017-04-21opcodes: mark SPARC RETT instructions as v6notv9.Jose E. Marchesi2-7/+11
2017-04-21Fix detection of illegal AArch64 opcodes that resemble LD1R, LD2R, LD3R and L...Nick Clifton2-8/+14
2017-04-13Regen cgen filesAlan Modra14-24/+53
2017-04-11Reorder PPC_OPCODE_* and set PPC_OPCODE_TMR for e6500Alan Modra3-6/+7
2017-04-11Bye bye PPC_OPCODE_HTM and -mhtmAlan Modra3-9/+8
2017-04-11Bye Bye PPC_OPCODE_VSX3Alan Modra3-7/+8
2017-04-11Bye bye PPC_OPCODE_ALTIVEC2Alan Modra3-7/+13
2017-04-10Tidy ppc476 opcodesAlan Modra3-43/+50
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