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2017-10-09S/390: Sync with latest POP - 3 new instructionsAndreas Krebbel2-0/+8
prno, tpei, and irbm are missing in the optable. gas/ChangeLog: 2017-10-09 Andreas Krebbel <krebbel@linux.vnet.ibm.com> * testsuite/gas/s390/zarch-arch12.d (prno, tpei, irbm): New instructions added. * testsuite/gas/s390/zarch-arch12.s: Likewise. * testsuite/gas/s390/zarch-z13.d: Rename ppno to prno. opcodes/ChangeLog: 2017-10-09 Andreas Krebbel <krebbel@linux.vnet.ibm.com> * s390-opc.txt (prno, tpei, irbm): New instructions added.
2017-10-09S/390: Sync with IBM z14 POP - SI_RD formatAndreas Krebbel3-4/+13
The recent POP adjusted a few of the instruction formats. This patch adjusts our optable accordingly. No user visible change - hopefully. opcodes/ChangeLog: 2017-10-09 Heiko Carstens <heiko.carstens@de.ibm.com> * s390-opc.c (INSTR_SI_RD): New macro. (INSTR_S_RD): Adjust example instruction. * s390-opc.txt (lpsw, ssm, ts): Change S_RD instruction format to SI_RD.
2017-10-01Add new mnemonics for VLE multiple load instructionsAlexander Fedotov2-0/+15
opcodes/ * ppc-opc.c (vle_opcodes): Add e_lmvsprw, e_lmvgprw, e_lmvsrrw, e_lmvcsrrw and e_lmvcsrrw as official mnemonics for VLE multimple load/store instructions. Old e_ldm* variants are kept as aliases. Add missing e_lmvmcsrrw and e_stmvmcsrrw. gas/ * testsuite/gas/ppc/vle-mult-ld-st-insns.s: New file: Tests the support for the VLE multiple load/store instructions. * testsuite/gas/ppc/vle-mult-ld-st-insns.d: New file: Test driver. * testsuite/gas/ppc/ppc.exp: Run it.
2017-09-27Add support for the new names of the RISC-V fmv.x.s and fmv.s.x ↵Nick Clifton2-0/+11
instructions, vis: fmv.x.w and fmv.w.x. PR 22179 opcodes * riscv-opc.c (riscv_opcodes): Add fmv.x.w and fmv.w.x as the new names for the fmv.x.s and fmv.s.x instructions respectively. gas * testsuite/gas/riscv/fmv.x.s: New file: Tests the support for the renamed fmv.x.s and fmv.s.x instructions. * testsuite/gas/riscv/fmv.x.d: New file: Test driver.
2017-09-26Allow the macw and macl instructions to be used on CPUs that have emacs support.Nick Clifton2-0/+20
From PR 22123: The common opcodes of emac and mac seem to be only implemented for mac. To reproduce: echo "macw %d3l,%a0l" > /tmp/dummy.S m68k-unknown-elf-as -m5208 /tmp/dummy.S Outputs something like: /tmp/dummy.S: Assembler messages: /tmp/dummy.S:1: Error: operands mismatch -- statement `macw %d3l,%a0l' ignored This behavior occurs only if the CPU supports only emac but not explicitly mac (but emac is a superset of mac).
2017-09-25Initialize 'imm' on opcodes/aarch64-opc.c:expand_fp_imm (and fix breakage on ↵Sergio Durigan Junior2-1/+5
mingw) Hi, While compiling GDB using a mingw compiler from Fedora 26: ../gdb/configure --host=x86_64-w64-mingw32 --target=x86_64-w64-mingw32 \ --disable-binutils --disable-ld --disable-gold --disable-gas --disable-sim \ --disable-gprof --enable-targets=all I stumbled upon a simple occurrence of -Werror=maybe-uninitialized: ../../gdb/opcodes/aarch64-opc.c: In function 'expand_fp_imm': ../../gdb/opcodes/aarch64-opc.c:2880:10: error: 'imm' may be used uninitialized in this function [-Werror=maybe-uninitialized] return imm; ^~~ It is the compiler's fault, because this function always assigns to 'imm' if the necessary conditions are met, and it calls "assert (0)" otherwise, but I thought it'd be clearer to have 'imm' explicitly set to zero anyway. opcodes/ChangeLog: 2017-09-21 Sergio Durigan Junior <sergiodj@redhat.com> * aarch64-opc.c (expand_fp_imm): Initialize 'imm'.
2017-09-11nds32: Rename __BIT() to N32_BIT().Kuan-Lin Chen4-40/+46
2017-09-09x86: Remove restriction on NOTRACK prefix positionH.J. Lu2-16/+8
Since the NOTRACK prefix is no longer required to be the last prefix before the REX prefix, restriction on the NOTRACK prefix position is removed from assembler as well as disassembler. Assembler encodes the NOTRACK prefix the same way as the DS segment register, which places it before other prefixes. Disassembler displays prefixes in the order they appear. gas/ * config/tc-i386.c (NOTRACK_PREFIX): Removed. (REX_PREFIX): Updated. (MAX_PREFIXES): Likewise. (parse_insn): Remove restriction on NOTRACK prefix position. * testsuite/gas/i386/notrack.s: Add tests with NOTRACK prefix before other prefixes. * testsuite/gas/i386/x86-64-notrack.s: Likewise. * testsuite/gas/i386/notrackbad.s: Remove tests with NOTRACK prefix before other prefixes. * testsuite/gas/i386/x86-64-notrackbad.s: Likewise. * testsuite/gas/i386/notrack-intel.d: Updated. * testsuite/gas/i386/notrack.d: Likewise. * testsuite/gas/i386/notrackbad.l: Likewise. * testsuite/gas/i386/x86-64-notrack-intel.d: Likewise. * testsuite/gas/i386/x86-64-notrack.d: Likewise. * testsuite/gas/i386/x86-64-notrackbad.l: Likewise. opcodes/ * i386-dis.c (last_active_prefix): Removed. (ckprefix): Don't set last_active_prefix. (NOTRACK_Fixup): Don't check last_active_prefix.
2017-08-31Add updated French translations for opcodes and gprofNick Clifton2-418/+786
2017-08-30FT32: improve disassembly readabilityJames Bowman2-7/+17
For opcode fields that are not addresses, display as integers instead of using print_address_func. opcodes/ChangeLog: 2017-08-31 James Bowman <james.bowman@ftdichip.com> * ft32-dis.c (print_insn_ft32): Correct display of non-address fields.
2017-08-24[PowerPC VLE] Add SPE2 and EFS2 instructions supportAlexander Fedotov3-12/+1239
include/ * opcode/ppc.h: (spe2_opcodes, spe2_num_opcodes): New. (PPC_OPCODE_SPE2): New define. (PPC_OPCODE_EFS2): Likewise. (SPE2_XOP): Likewise. (SPE2_XOP_TO_SEG): Likewise. opcodes/ * ppc-dis.c (ppc_mopt): Add PPC_OPCODE_SPE2 and PPC_OPCODE_EFS2 flag to "e200z4" entry. New entries efs2 and spe2. Add PPC_OPCODE_SPE2 and PPC_OPCODE_EFS2 flag to "vle" entry. (SPE2_OPCD_SEGS): New macro. (spe2_opcd_indices): New. (disassemble_init_powerpc): Handle SPE2 opcodes. (lookup_spe2): New function. (print_insn_powerpc): call lookup_spe2. * ppc-opc.c (insert_evuimm1_ex0): New function. (extract_evuimm1_ex0): Likewise. (insert_evuimm_lt8): Likewise. (extract_evuimm_lt8): Likewise. (insert_off_spe2): Likewise. (extract_off_spe2): Likewise. (insert_Ddd): Likewise. (extract_Ddd): Likewise. (DD): New operand. (EVUIMM_LT8): Likewise. (EVUIMM_LT16): Adjust. (MMMM): New operand. (EVUIMM_1): Likewise. (EVUIMM_1_EX0): Likewise. (EVUIMM_2): Adjust. (NNN): New operand. (VX_OFF_SPE2): Likewise. (BBB): Likewise. (DDD): Likewise. (VX_MASK_DDD): New mask. (HH): New operand. (VX_RA_CONST): New macro. (VX_RA_CONST_MASK): Likewise. (VX_RB_CONST): Likewise. (VX_RB_CONST_MASK): Likewise. (VX_OFF_SPE2_MASK): Likewise. (VX_SPE_CRFD): Likewise. (VX_SPE_CRFD_MASK VX): Likewise. (VX_SPE2_CLR): Likewise. (VX_SPE2_CLR_MASK): Likewise. (VX_SPE2_SPLATB): Likewise. (VX_SPE2_SPLATB_MASK): Likewise. (VX_SPE2_OCTET): Likewise. (VX_SPE2_OCTET_MASK): Likewise. (VX_SPE2_DDHH): Likewise. (VX_SPE2_DDHH_MASK): Likewise. (VX_SPE2_HH): Likewise. (VX_SPE2_HH_MASK): Likewise. (VX_SPE2_EVMAR): Likewise. (VX_SPE2_EVMAR_MASK): Likewise. (PPCSPE2): Likewise. (PPCEFS2): Likewise. (vle_opcodes): Add EFS2 and some missing SPE opcodes. (powerpc_macros): Map old SPE instructions have new names with the same opcodes. Add SPE2 instructions which just are mapped to SPE2. (spe2_opcodes): Add SPE2 opcodes. gas/ * config/tc-ppc.c: (md_parse_option): Add mspe2 switch. (md_show_usage): Document -mspe2. (ppc_setup_opcodes): Handle spe2_opcodes. * doc/as.texinfo: Document -mspe2. * doc/c-ppc.texi: Likewise. * testsuite/gas/ppc/efs.d: New file. * testsuite/gas/ppc/efs.s: Likewise. * testsuite/gas/ppc/efs2.d: Likewise. * testsuite/gas/ppc/efs2.s: Likewise. * testsuite/gas/ppc/ppc.exp: Run new tests. * testsuite/gas/ppc/spe.d: New file. * testsuite/gas/ppc/spe.s: Likewise. * testsuite/gas/ppc/spe2-checks.d: Likewise. * testsuite/gas/ppc/spe2-checks.l: Likewise. * testsuite/gas/ppc/spe2-checks.s: Likewise. * testsuite/gas/ppc/spe2.d: Likewise. * testsuite/gas/ppc/spe2.s: Likewise. * testsuite/gas/ppc/spe_ambiguous.d: Likewise. * testsuite/gas/ppc/spe_ambiguous.s: Likewise.
2017-08-23ppc-opc.c formattingAlan Modra2-1089/+1101
* ppc-opc.c: Formatting and comment fixes. Move insert and extract functions earlier, deleting forward declarations. (insert_nbi, insert_raq, insert_rbx): Expand use of RT_MASK and RA_MASK.
2017-08-22RISC-V: Mark "c.nop" as an aliasPalmer Dabbelt2-1/+5
This fixes "-M noaliases" disassembly for "c.nop", which is an alias for "c.addi x0, 0". opcodes/ChangeLog 2017-08-01 Palmer Dabbelt <palmer@dabbelt.com> * riscv-opc.c (riscv_opcodes): Mark "c.nop" as an alias.
2017-08-21[PowerPC VLE] Add LSP (Lightweight Signal Processing) instruction supportAlexander Fedotov3-6/+920
include/ * opcode/ppc.h (PPC_OPCODE_LSP): New define. opcodes/ * ppc-opc.c (insert_evuimm2_ex0): New function. (extract_evuimm2_ex0): Likewise. (insert_evuimm4_ex0): Likewise. (extract_evuimm4_ex0): Likewise. (insert_evuimm8_ex0): Likewise. (extract_evuimm8_ex0): Likewise. (insert_evuimm_lt16): Likewise. (extract_evuimm_lt16): Likewise. (insert_rD_rS_even): Likewise. (extract_rD_rS_even): Likewise. (insert_off_lsp): Likewise. (extract_off_lsp): Likewise. (RD_EVEN): New operand. (RS_EVEN): Likewise. (RSQ): Adjust. (EVUIMM_LT16): New operand. (HTM_SI): Adjust. (EVUIMM_2_EX0): New operand. (EVUIMM_4): Adjust. (EVUIMM_4_EX0): New operand. (EVUIMM_8): Adjust. (EVUIMM_8_EX0): New operand. (WS): Adjust. (VX_OFF): New operand. (VX_LSP): New macro. (VX_LSP_MASK): Likewise. (VX_LSP_OFF_MASK): Likewise. (PPC_OPCODE_LSP): Likewise. (vle_opcodes): Add LSP opcodes. * ppc-dis.c (ppc_mopt): Add PPC_OPCODE_LSP flag to "vle" entry. gas/ * testsuite/gas/ppc/lsp-checks.d, * testsuite/gas/ppc/lsp-checks.l, * testsuite/gas/ppc/lsp-checks.s: New test. * testsuite/gas/ppc/lsp.d, * testsuite/gas/ppc/lsp.s: New test. * testsuite/gas/ppc/ppc.exp: Run new tests.
2017-08-09[ARM] Don't warn on REG_SP when used in CRC32 instructionsJiong Wang2-11/+13
According to ARMv8-A architecture manual, REG_SP is allowed in CRC32 instructions in Thumb mode. It is REG_PC that will cause unpredictable behaviours on both ARM and Thumb. This patch removes the incorrect warning on Thumb mode. Meanwhile the disassembler is updated to use format "<bitfield>R" instead of "<bitfield>S". "<bitfield>S" is not used elsewhere. so I have deleted related code from the disassembler. gas/ * config/tc-arm.c (do_crc32_1): Remove warning on REG_SP for thumb_mode. * testsuite/gas/arm/crc32-armv8-a-bad.d: Update exepcted result. * testsuite/gas/arm/crc32-armv8-r-bad.d: Likewise. * testsuite/gas/arm/crc32-armv8-a.d: Likewise. * testsuite/gas/arm/crc32-armv8-r.d: Likewise. * testsuite/gas/arm/crc32-armv8-ar-bad.s: Update test case. * testsuite/gas/arm/crc32-armv8-ar.s: Likewise. * testsuite/gas/arm/crc32-bad.l: Update expected error message. opcode/ * arm-dis.c (thumb32_opcodes): Use format 'R' instead of 'S' for register operands in CRC instructions. (print_insn_thumb32): Remove "<bitfield>S" support. Updated the comments.
2017-08-07Mark big and mach with ATTRIBUTE_UNUSEDH.J. Lu2-1/+8
Fix build on x86: opcodes/disassemble.c: In function ‘disassembler’: opcodes/disassemble.c:113:52: error: unused parameter ‘big’ [-Werror=unused-parameter] disassembler (enum bfd_architecture a, bfd_boolean big, unsigned long mach, ^~~ opcodes/disassemble.c:113:71: error: unused parameter ‘mach’ [-Werror=unused-parameter] disassembler (enum bfd_architecture a, bfd_boolean big, unsigned long mach, ^~~~ cc1: all warnings being treated as errors * disassemble.c (disassembler): Mark big and mach with ATTRIBUTE_UNUSED.
2017-08-07GDB/opcodes: Remove arch/mach/endian disassembler assertionsMaciej W. Rozycki2-12/+6
Fix `set architecture' and `set endian' command disassembly regressions from commit 39503f82427e ("Delegate opcodes to select disassembler in GDB"), and commit 003ca0fd2286 ("Refactor disassembler selection"), as well as a MIPS compressed ISA disassembly target regression from commit 6394c606997f ("Don't use print_insn_XXX in GDB"), which caused assertion failures to trigger. For example with the `mips-linux-gnu' target we get: $ cat main.c int main (void) { return 0; } $ gcc -mips32r2 -O2 main.c -o main $ gcc -mips16 -mips32r2 -O2 main.c -o main16 $ gdb GNU gdb (GDB) 8.0.50.20170731-git [...] (gdb) file main Reading symbols from main...done. (gdb) show architecture The target architecture is set automatically (currently mips:isa32r2) (gdb) show endian The target endianness is set automatically (currently big endian) (gdb) disassemble main Dump of assembler code for function main: 0x00400500 <+0>: jr ra 0x00400504 <+4>: move v0,zero End of assembler dump. (gdb) set architecture mips:isa64r2 The target architecture is assumed to be mips:isa64r2 (gdb) disassemble main Dump of assembler code for function main: 0x00400500 <+0>: .../gdb/arch-utils.c:979: internal-error: int default_print_insn(bfd_vma, disassemble_info*): Assertion `info->mach == bfd_get_mach (exec_bfd)' failed. A problem internal to GDB has been detected, further debugging may prove unreliable. Quit this debugging session? (y or n) n [...] Command aborted. (gdb) set architecture auto The target architecture is set automatically (currently mips:isa32r2) (gdb) set endian little The target is assumed to be little endian (gdb) disassemble main Dump of assembler code for function main: 0x00400500 <+0>: .../gdb/arch-utils.c:978: internal-error: int default_print_insn(bfd_vma, disassemble_info*): Assertion `info->endian == (bfd_big_endian (exec_bfd) ? BFD_ENDIAN_BIG : BFD_ENDIAN_LITTLE)' failed. A problem internal to GDB has been detected, further debugging may prove unreliable. Quit this debugging session? (y or n) n [...] Command aborted. (gdb) set endian auto The target endianness is set automatically (currently big endian) (gdb) set architecture i386 The target architecture is assumed to be i386 (gdb) disassemble main Dump of assembler code for function main: 0x00400500 <+0>: .../gdb/arch-utils.c:976: internal-error: int default_print_insn(bfd_vma, disassemble_info*): Assertion `info->arch == bfd_get_arch (exec_bfd)' failed. A problem internal to GDB has been detected, further debugging may prove unreliable. Quit this debugging session? (y or n) n [...] Command aborted. (gdb) set architecture auto The target architecture is set automatically (currently mips:isa32r2) (gdb) file main16 Load new symbol table from "main16"? (y or n) y Reading symbols from main16...done. (gdb) disassemble main Dump of assembler code for function main: 0x00400501 <+0>: .../gdb/arch-utils.c:979: internal-error: int default_print_insn(bfd_vma, disassemble_info*): Assertion `info->mach == bfd_get_mach (exec_bfd)' failed. A problem internal to GDB has been detected, further debugging may prove unreliable. Quit this debugging session? (y or n) n Command aborted. (gdb) Remove the assertions then, restoring previous semantics: (gdb) file main Reading symbols from main...done. (gdb) set architecture mips:isa64r2 The target architecture is assumed to be mips:isa64r2 (gdb) disassemble main Dump of assembler code for function main: 0x00400500 <+0>: jr ra 0x00400504 <+4>: move v0,zero End of assembler dump. (gdb) set endian little The target is assumed to be little endian (gdb) disassemble main Dump of assembler code for function main: 0x00400500 <+0>: j 0x3800c 0x00400504 <+4>: addiu s0,t0,0 End of assembler dump. (gdb) set architecture i386 The target architecture is assumed to be i386 (gdb) disassemble main Dump of assembler code for function main: 0x00400500 <+0>: add %eax,%esp 0x00400502 <+2>: add %cl,(%eax) 0x00400504 <+4>: add %al,(%eax) 0x00400506 <+6>: adc %ah,0x0 End of assembler dump. (gdb) set architecture auto The target architecture is set automatically (currently mips:isa32r2) (gdb) set endian auto The target endianness is set automatically (currently big endian) (gdb) file main16 Load new symbol table from "main16"? (y or n) y Reading symbols from main16...done. (gdb) disassemble main Dump of assembler code for function main: 0x00400501 <+0>: jr ra 0x00400503 <+2>: li v0,0 End of assembler dump. (gdb) gdb/ * arch-utils.c (default_print_insn): Remove arch/mach/endian assertions. opcodes/ * disassemble.c (disassembler): Remove arch/mach/endian assertions.
2017-07-25Fix typos in error and option messages in OPCODES library.Nick Clifton3-36/+75
PR 21739 opcodes * arc-opc.c (insert_rhv2): Use lower case first letter in error message. (insert_r0): Likewise. (insert_r1): Likewise. (insert_r2): Likewise. (insert_r3): Likewise. (insert_sp): Likewise. (insert_gp): Likewise. (insert_pcl): Likewise. (insert_blink): Likewise. (insert_ilink1): Likewise. (insert_ilink2): Likewise. (insert_ras): Likewise. (insert_rbs): Likewise. (insert_rcs): Likewise. (insert_simm3s): Likewise. (insert_rrange): Likewise. (insert_r13el): Likewise. (insert_fpel): Likewise. (insert_blinkel): Likewise. (insert_pclel): Likewise. (insert_nps_bitop_size_2b): Likewise. (insert_nps_imm_offset): Likewise. (insert_nps_imm_entry): Likewise. (insert_nps_size_16bit): Likewise. (insert_nps_##NAME##_pos): Likewise. (insert_nps_##NAME): Likewise. (insert_nps_bitop_ins_ext): Likewise. (insert_nps_##NAME): Likewise. (insert_nps_min_hofs): Likewise. (insert_nps_##NAME): Likewise. (insert_nps_rbdouble_64): Likewise. (insert_nps_misc_imm_offset): Likewise. * riscv-dis.c (print_riscv_disassembler_options): Fix typo in option description. gas * testsuite/gas/arc/add_s-err.s: Update expected error message.
2017-07-24[AArch64] Fix the bit pattern order in the comments in auto-generated fileJiong Wang3-1689/+1699
The bit pattern comment in "aarch64_opcode_lookup_1" is reversed. This patch fixed this. opcode/ * aarch64-gen.c (print_decision_tree_1): Reverse the index of PATTERN to correct the print. * aarch64-dis-2.c: Regenerated.
2017-07-21S/390: Support z14 as CPU name.Andreas Krebbel2-1/+7
With IBM z14 officially announced I can add z14 as CPU name. No regressions with that patch on s390x. gas/ChangeLog: 2017-07-21 Andreas Krebbel <krebbel@linux.vnet.ibm.com> * config/tc-s390.c (s390_parse_cpu): Add z14 as alternate CPU name. * doc/as.texinfo: Add z14 to CPU string list. * doc/c-s390.texi: Likewise. opcodes/ChangeLog: 2017-07-21 Andreas Krebbel <krebbel@linux.vnet.ibm.com> * s390-mkopc.c (main): Enable z14 as CPU string in the opcode table.
2017-07-20Update the German translation for the opcodes library.Nick Clifton2-466/+890
* po/de.po: Updated German translation.
2017-07-19[ARC] Add SecureShield AUX registersclaziss2-0/+21
Update auxiliary registers with SecureShield ones. opcodes/ 2017-07-19 Claudiu Zissulescu <claziss@synopsys.com> * arc-regs.h (sec_stat): New aux register. (aux_kernel_sp): Likewise. (aux_sec_u_sp): Likewise. (aux_sec_k_sp): Likewise. (sec_vecbase_build): Likewise. (nsc_table_top): Likewise. (nsc_table_base): Likewise. (ersec_stat): Likewise. (aux_sec_except): Likewise.
2017-07-19[ARC] Add SJLI instruction.Claudiu Zissulescu3-1/+27
include/ 2017-07-19 Claudiu Zissulescu <claziss@synopsys.com> * opcode/arc.h (SJLI): Add. opcode/ 2017-07-19 Claudiu Zissulescu <claziss@synopsys.com> * arc-opc.c (extract_uimm12_20): New function. (UIMM12_20): New operand. (SIMM3_5_S): Adjust. * arc-tbl.h (sjli): Add new instruction.
2017-07-19[ARC] Add JLI support.John Eric Martin4-2/+17
The following relocation types were added to GCC/binutils: ARC_JLI_SECTOFF is a relocation type in Metaware that is now used by GCC as well to adjust the index of function calls to functions with attribute jli_call_always. bfd/ 2017-07-19 Claudiu Zissulescu <claziss@synopsys.com> John Eric Martin <John.Martin@emmicro-us.com> * bfd-in2.h: Regenerate. * libbfd.h: Regenerate. * elf32-arc.c (JLI): Define. * reloc.c: Add JLI relocations. gas/ 2017-07-19 Claudiu Zissulescu <claziss@synopsys.com> * testsuite/gas/arc/jli-1.d: New file. * testsuite/gas/arc/jli-1.s: Likewise. * testsuite/gas/arc/taux.d: Update for jli_base. include/ 2017-07-19 Claudiu Zissulescu <claziss@synopsys.com> John Eric Martin <John.Martin@emmicro-us.com> * elf/arc-reloc.def: Add JLI relocs howto. * opcode/arc-func.h (replace_jli): New function. ld/ 2017-07-19 Claudiu Zissulescu <claziss@synopsys.com> John Eric Martin <John.Martin@emmicro-us.com> * emulparams/arcelf.sh (JLI_START_TABLE): Define. * scripttempl/elfarc.sc: Handle jlitab section. * scripttempl/elfarcv2.sc: Likewise. * testsuite/ld-arc/arc.exp: Add JLI test. * testsuite/ld-arc/jli-script.ld: New file. * testsuite/ld-arc/jli-simple.dd: Likewise. * testsuite/ld-arc/jli-simple.rd: Likewise. * testsuite/ld-arc/jli-simple.s: Likewise. * testsuite/ld/testsuite/ld-arc/jli-overflow.s: Likewise. * testsuite/ld/testsuite/ld-arc/jli-overflow.d: Likewise. * testsuite/ld/testsuite/ld-arc/jli-overflow.err: Likewise. opcode/ 2017-07-19 Claudiu Zissulescu <claziss@synopsys.com> John Eric Martin <John.Martin@emmicro-us.com> * arc-opc.c (UIMM10_6_S_JLIOFF): Define. (UIMM3_23): Adjust accordingly. * arc-regs.h: Add/correct jli_base register. * arc-tbl.h (jli_s): Likewise.
2017-07-18Fix spelling typos.Yuri Chornovian3-2/+8
2017-07-14binutils/objdump: Fix disassemble for huge elf sectionsRavi Bangoria2-3/+8
When elf section size is beyond unsigned int max value, objdump fails to disassemble from that section. Ex on PowerPC, $ objdump -h /proc/kcore Idx Name Size VMA 4 load2 100000000 c000000000000000 Here, size of load2 section is 0x100000000. Also note that, 0xc00.... address range is kernel space for PowerPC. Now let's try to disassemble do_sys_open() using /proc/kcore. $ cat /proc/kallsyms | grep -A1 -w do_sys_open c00000000036c000 T do_sys_open c00000000036c2d0 T SyS_open Before patch: $ objdump -d --start-address=0xc00000000036c000 --stop-address=0xc00000000036c2d0 /proc/kcore /proc/kcore: file format elf64-powerpcle Disassembly of section load2: c00000000036c000 <load2+0x36c000>: c00000000036c000: Address 0xc00000000036c000 is out of bounds. Fix this by changing type of 'buffer_length' from unsigned int to size_t. After patch: $ objdump -d --start-address=0xc00000000036c000 --stop-address=0xc00000000036c2d0 /proc/kcore /proc/kcore: file format elf64-powerpcle Disassembly of section load2: c00000000036c000 <load2+0x36c000>: c00000000036c000: fc 00 4c 3c addis r2,r12,252 c00000000036c004: 00 53 42 38 addi r2,r2,21248 c00000000036c008: a6 02 08 7c mflr r0 include/ * dis-asm.h (struct disassemble_info): Change type of buffer_length field to size_t. opcodes/ * dis-buf.c (buffer_read_memory): Change type of end_addr_offset, max_addr_offset and octets variables to size_t.
2017-07-12Update PO filesAlan Modra16-875/+2049
bfd/ * po/es.po: Update from translationproject.org/latest/bfd/. * po/fi.po: Likewise. * po/fr.po: Likewise. * po/id.po: Likewise. * po/ja.po: Likewise. * po/ro.po: Likewise. * po/ru.po: Likewise. * po/sr.po: Likewise. * po/sv.po: Likewise. * po/tr.po: Likewise. * po/uk.po: Likewise. * po/vi.po: Likewise. * po/zh_CN.po: Likewise. * po/hr.po: New file from translationproject.org. * configure.ac (ALL_LINGUAS): Add hr. Sort. * configure: Regenerate. binutils/ * po/bg.po: Update from translationproject.org/latest/binutils/. * po/ca.po: Likewise. * po/da.po: Likewise. * po/es.po: Likewise. * po/fi.po: Likewise. * po/fr.po: Likewise. * po/hr.po: Likewise. * po/id.po: Likewise. * po/it.po: Likewise. * po/ja.po: Likewise. * po/ro.po: Likewise. * po/ru.po: Likewise. * po/sk.po: Likewise. * po/sr.po: Likewise. * po/sv.po: Likewise. * po/tr.po: Likewise. * po/uk.po: Likewise. * po/vi.po: Likewise. * po/zh_CN.po: Likewise. * po/zh_TW.po: Likewise. gas/ * po/es.po: Update from translationproject.org/latest/gas/. * po/fi.po: Likewise. * po/fr.po: Likewise. * po/id.po: Likewise. * po/ja.po: Likewise. * po/ru.po: Likewise. * po/sv.po: Likewise. * po/tr.po: Likewise. * po/uk.po: Likewise. * po/zh_CN.po: Likewise. gold/ * po/es.po: Update from translationproject.org/latest/gold/. * po/fi.po: Likewise. * po/fr.po: Likewise. * po/id.po: Likewise. * po/it.po: Likewise. * po/vi.po: Likewise. * po/zh_CN.po: Likewise. * po/ja.po: New file from translationproject.org. * po/sv.po: Likewise. * po/uk.po: Likewise. gprof/ * po/bg.po: Update from translationproject.org/latest/gprof/. * po/da.po: Likewise. * po/de.po: Likewise. * po/eo.po: Likewise. * po/es.po: Likewise. * po/fi.po: Likewise. * po/fr.po: Likewise. * po/ga.po: Likewise. * po/hu.po: Likewise. * po/id.po: Likewise. * po/it.po: Likewise. * po/ja.po: Likewise. * po/ms.po: Likewise. * po/nl.po: Likewise. * po/pt_BR.po: Likewise. * po/ro.po: Likewise. * po/ru.po: Likewise. * po/sr.po: Likewise. * po/sv.po: Likewise. * po/tr.po: Likewise. * po/uk.po: Likewise. * po/vi.po: Likewise. ld/ * po/bg.po: Update from translationproject.org/latest/ld/. * po/da.po: Likewise. * po/es.po: Likewise. * po/fi.po: Likewise. * po/fr.po: Likewise. * po/id.po: Likewise. * po/it.po: Likewise. * po/ja.po: Likewise. * po/tr.po: Likewise. * po/uk.po: Likewise. * po/vi.po: Likewise. * po/zh_CN.po: Likewise. * po/zh_TW.po: Likewise. * po/de.po: New file from translationproject.org. * po/ru.po: Likewise. * configure.ac (ALL_LINGUAS): Add de, ru. Sort. * configure: Regenerate. opcodes/ * po/da.po: Update from translationproject.org/latest/opcodes/. * po/de.po: Likewise. * po/es.po: Likewise. * po/fi.po: Likewise. * po/fr.po: Likewise. * po/id.po: Likewise. * po/it.po: Likewise. * po/nl.po: Likewise. * po/pt_BR.po: Likewise. * po/ro.po: Likewise. * po/sv.po: Likewise. * po/tr.po: Likewise. * po/uk.po: Likewise. * po/vi.po: Likewise. * po/zh_CN.po: Likewise.
2017-07-11Mark generated cgen files read-onlyAlan Modra96-8/+211
* cgen.sh: Mark generated files read-only. * epiphany-asm.c: Regenerate. * epiphany-desc.c: Regenerate. * epiphany-desc.h: Regenerate. * epiphany-dis.c: Regenerate. * epiphany-ibld.c: Regenerate. * epiphany-opc.c: Regenerate. * epiphany-opc.h: Regenerate. * fr30-asm.c: Regenerate. * fr30-desc.c: Regenerate. * fr30-desc.h: Regenerate. * fr30-dis.c: Regenerate. * fr30-ibld.c: Regenerate. * fr30-opc.c: Regenerate. * fr30-opc.h: Regenerate. * frv-asm.c: Regenerate. * frv-desc.c: Regenerate. * frv-desc.h: Regenerate. * frv-dis.c: Regenerate. * frv-ibld.c: Regenerate. * frv-opc.c: Regenerate. * frv-opc.h: Regenerate. * ip2k-asm.c: Regenerate. * ip2k-desc.c: Regenerate. * ip2k-desc.h: Regenerate. * ip2k-dis.c: Regenerate. * ip2k-ibld.c: Regenerate. * ip2k-opc.c: Regenerate. * ip2k-opc.h: Regenerate. * iq2000-asm.c: Regenerate. * iq2000-desc.c: Regenerate. * iq2000-desc.h: Regenerate. * iq2000-dis.c: Regenerate. * iq2000-ibld.c: Regenerate. * iq2000-opc.c: Regenerate. * iq2000-opc.h: Regenerate. * lm32-asm.c: Regenerate. * lm32-desc.c: Regenerate. * lm32-desc.h: Regenerate. * lm32-dis.c: Regenerate. * lm32-ibld.c: Regenerate. * lm32-opc.c: Regenerate. * lm32-opc.h: Regenerate. * lm32-opinst.c: Regenerate. * m32c-asm.c: Regenerate. * m32c-desc.c: Regenerate. * m32c-desc.h: Regenerate. * m32c-dis.c: Regenerate. * m32c-ibld.c: Regenerate. * m32c-opc.c: Regenerate. * m32c-opc.h: Regenerate. * m32r-asm.c: Regenerate. * m32r-desc.c: Regenerate. * m32r-desc.h: Regenerate. * m32r-dis.c: Regenerate. * m32r-ibld.c: Regenerate. * m32r-opc.c: Regenerate. * m32r-opc.h: Regenerate. * m32r-opinst.c: Regenerate. * mep-asm.c: Regenerate. * mep-desc.c: Regenerate. * mep-desc.h: Regenerate. * mep-dis.c: Regenerate. * mep-ibld.c: Regenerate. * mep-opc.c: Regenerate. * mep-opc.h: Regenerate. * mt-asm.c: Regenerate. * mt-desc.c: Regenerate. * mt-desc.h: Regenerate. * mt-dis.c: Regenerate. * mt-ibld.c: Regenerate. * mt-opc.c: Regenerate. * mt-opc.h: Regenerate. * or1k-asm.c: Regenerate. * or1k-desc.c: Regenerate. * or1k-desc.h: Regenerate. * or1k-dis.c: Regenerate. * or1k-ibld.c: Regenerate. * or1k-opc.c: Regenerate. * or1k-opc.h: Regenerate. * or1k-opinst.c: Regenerate. * xc16x-asm.c: Regenerate. * xc16x-desc.c: Regenerate. * xc16x-desc.h: Regenerate. * xc16x-dis.c: Regenerate. * xc16x-ibld.c: Regenerate. * xc16x-opc.c: Regenerate. * xc16x-opc.h: Regenerate. * xstormy16-asm.c: Regenerate. * xstormy16-desc.c: Regenerate. * xstormy16-desc.h: Regenerate. * xstormy16-dis.c: Regenerate. * xstormy16-ibld.c: Regenerate. * xstormy16-opc.c: Regenerate. * xstormy16-opc.h: Regenerate.
2017-07-07Move print_insn_XXX to an opcodes internal header, againAlan Modra4-3/+9
88c1242dc0a changed some generated files rather than the source. * cgen-dis.in: Include disassemble.h, not dis-asm.h. * m32c-dis.c: Regenerate. * mep-dis.c: Regenerate.
2017-07-05X86: Disassemble primary opcode map's group 2 ModRM.reg == 6 aliases correctlyBorislav Petkov2-6/+10
The instructions are not documented in the Intel SDM but are documented in the AMD APM as an alias to the group 2, ModRM.reg == 4 variant. Both AMD and Intel CPUs execute the C[0-1] and D[0-3] instructions as expected, i.e., like the /4 aliases: #include <stdio.h> int main(void) { int a = 2; printf ("a before: %d\n", a); asm volatile(".byte 0xd0,0xf0" /* SHL %al */ : "+a" (a)); printf("a after : %d\n", a); return 0; } $ ./a.out a before: 2 a after : 4
2017-07-05Fixup changelog entries for previous commitRamana Radhakrishnan1-0/+5
40c7d50720e04c3d1ef1695a8097f735bafbe54f
2017-07-04[Patch ARM] Support MVFR2 VFP Coprocessor register for ARMv8-ARamana Radhakrishnan1-0/+4
This patch adds support mvfr2 control registers for armv8-a as this was missed from the original port to armv8-a (documented at G6.2.109 in (Issue B.a) of the ARM-ARM. This was discovered by an internal user of the GNU toolchain. I'd like to backport this to the binutils 2.28 and binutils 2.29 release branch if possible (with suitable testing and basically checking removing the armv8-r parts). Tristan - are you ok with the backports ? Applied to trunk. regards Ramana 2017-07-04 Ramana Radhakrishnan <ramana.radhakrishnan@arm.com> * gas/config/tc-arm.c (arm_regs): Add MVFR2. (do_vmrs): Constraint for MVFR2 and armv8. (do_vmsr): Likewise. * gas/testsuite/gas/arm/armv8-a+fp.d: Update. * gas/testsuite/gas/arm/armv8-ar+fp.s: Likewise. * gas/testsuite/gas/arm/armv8-r+fp.d: Likewise. * gas/testsuite/gas/arm/vfp-bad.s: Likewise. * gas/testsuite/gas/arm/vfp-bad.l: Likewise. * opcodes/arm-dis.c: Support MVFR2 in disassembly with vmrs and vmsr.
2017-07-04Regenerate configure.Tristan Gingold2-10/+14
bfd/ 2017-07-04 Tristan Gingold <gingold@adacore.com> * version.m4: Bump version to 2.29.51 * configure: Regenerate. binutils/ 2017-07-04 Tristan Gingold <gingold@adacore.com> * configure: Regenerate. gas/ 2017-07-04 Tristan Gingold <gingold@adacore.com> * configure: Regenerate. gprof/ 2017-07-04 Tristan Gingold <gingold@adacore.com> * configure: Regenerate. ld/ 2017-07-04 Tristan Gingold <gingold@adacore.com> * configure: Regenerate. opcodes/ 2017-07-04 Tristan Gingold <gingold@adacore.com> * configure: Regenerate.
2017-07-03Regenerate pot files.Tristan Gingold2-133/+150
2017-06-30MIPS/opcodes: Reorder LSA and DLSA instructionsMaciej W. Rozycki2-3/+8
Correct an issue introduced with commit 7361da2c952e ("Add support for MIPS R6.") and move the LSA and DLSA instructions back to the MSA ASE instruction block in the regular MIPS opcode table. Adjust formatting around the "MIPS r6" heading. opcodes/ * mips-opc.c (mips_builtin_opcodes): Move "lsa" and "dlsa" entries to the MSA ASE instruction block.
2017-06-30MIPS: Add Imagination interAptiv MR2 MIPS32r3 processor support (ChangeLog)Maciej W. Rozycki1-1/+1
Correct ChangeLog entry for commit 38bf472a1521 ("MIPS: Add Imagination interAptiv MR2 MIPS32r3 processor support").
2017-06-30MIPS: Add microMIPS XPA supportMaciej W. Rozycki2-0/+19
Add support for the base and Virtualization ASE microMIPS instructions as per the architecture specifications[1][2][3][4]. Most of this change by Andrew Bennett. [1] "MIPS Architecture for Programmers Volume II-B: The microMIPS32 Instruction Set", MIPS Technologies, Inc., Document Number: MD00582, Revision 5.04, January 15, 2014, Section 5.5 "Recoded 32-Bit Instructions", p. 340 [2] "microMIPS32 Architecture for Programmers Volume IV-i: Virtualization Module of the microMIPS32 Architecture", MIPS Technologies, Inc., Document Number: MD00848, Revision 1.06, December 10, 2013, Section 6.1 "Overview", pp. 133, 136 [3] "MIPS Architecture for Programmers Volume II-B: The microMIPS64 Instruction Set", MIPS Technologies, Inc., Document Number: MD00594, Revision 5.04, January 15, 2014, Section 5.5 "Recoded 32-Bit Instructions", pp. 415, 444 [4] "microMIPS64 Architecture for Programmers Volume IV-i: Virtualization Module of the microMIPS64 Architecture", MIPS Technologies, Inc., Document Number: MD00849, Revision 1.06, December 10, 2013, Section 6.1 "Overview", pp. 134-135, 139-140 binutils/ * NEWS: Mention microMIPS XPA support. opcodes/ * micromips-opc.c (XPA, XPAVZ): New macros. (micromips_opcodes): Add "mfhc0", "mfhgc0", "mthc0" and "mthgc0". gas/ * config/tc-mips.c (mips_ases): Add microMIPS XPA support. * testsuite/gas/mips/micromips@xpa.d: New test. * testsuite/gas/mips/mips.exp: Run the new test. Enable `xpa-virt-err' test for `micromips'.
2017-06-30MIPS: Add microMIPS R5 supportMaciej W. Rozycki2-0/+8
Add base microMIPS Release 5 ISA support and the ERETNC instruction in particular, as per the architecture specifications[1][2]. Most of this change by Andrew Bennett. References: [1] "MIPS Architecture for Programmers Volume II-B: The microMIPS32 Instruction Set", MIPS Technologies, Inc., Document Number: MD00582, Revision 5.04, January 15, 2014, Section 5.5 "Recoded 32-Bit Instructions", pp. 266-267 [2] "MIPS Architecture for Programmers Volume II-B: The microMIPS64 Instruction Set", MIPS Technologies, Inc., Document Number: MD00594, Revision 5.04, January 15, 2014, Section 5.5 "Recoded 32-Bit Instructions", pp. 326-327 binutils/ * NEWS: Mention microMIPS Release 5 ISA support. opcodes/ * micromips-opc.c (I36): New macro. (micromips_opcodes): Add "eretnc". gas/ * testsuite/gas/mips/micromips@r5.d: New test. * testsuite/gas/mips/mips.exp: Run the new test.
2017-06-30MIPS: Fix XPA base and Virtualization ASE instruction handlingMaciej W. Rozycki3-24/+53
Correct a commit 7d64c587c15f ("Add support for the MIPS eXtended Physical Address (XPA) ASE.") bug, causing XPA base and Virtualization ASE instructions to be wrongly always enabled with the selection of the MIPS32r2 or higher ISA. For example this source assembles successfully as shown below: $ cat xpa.s mfhc0 $2, $1 $ as -32 -mips32 -o xpa.o xpa.s xpa.s: Assembler messages: xpa.s:1: Error: opcode not supported on this processor: mips32 (mips32) `mfhc0 $2,$1' $ as -32 -mips32r2 -o xpa.o xpa.s $ objdump -d xpa.o xpa.o: file format elf32-tradbigmips Disassembly of section .text: 00000000 <.text>: 0: 40420800 mfhc0 v0,c0_random ... $ To address this issue remove the I33 (INSN_ISA32R2) marking from all XPA instructions in the opcode table. Additionally, for XPA Virtualization ASE instructions implement an XPAVZ (ASE_XPA_VIRT) combination ASE flag and use it in place of IVIRT|XPA (ASE_VIRT|ASE_XPA). Now the same source is correctly rejected unless the `-mxpa' option is also used: $ as -32 -mips32r2 -o xpa.o xpa.s xpa.s: Assembler messages: xpa.s:1: Error: opcode not supported on this processor: mips32r2 (mips32r2) `mfhc0 $2,$1' $ as -32 -mips32r2 -mxpa -o xpa.o xpa.s $ Add test cases for XPA base and XPA Virtualization ASE instructions. Parts of this change by Andrew Bennett. include/ * opcode/mips.h (ASE_XPA_VIRT): New macro. opcodes/ * mips-dis.c (mips_calculate_combination_ases): Handle the ASE_XPA_VIRT flag. (parse_mips_ase_option): New function. (parse_mips_dis_option): Factor out ASE option handling to the new function. Call `mips_calculate_combination_ases'. * mips-opc.c (XPAVZ): New macro. (mips_builtin_opcodes): Correct ISA and ASE flags for "mfhc0", "mfhgc0", "mthc0" and "mthgc0". gas/ * config/tc-mips.c (mips_set_ase): Handle the ASE_XPA_VIRT flag. * testsuite/gas/mips/xpa.d: Remove `xpa' from `-M' in `objdump' flags. Add `-mvirt' to `as' flags. * testsuite/gas/mips/xpa-err.d: New test. * testsuite/gas/mips/xpa-virt-err.d: New test. * testsuite/gas/mips/xpa-err.l: New stderr output. * testsuite/gas/mips/xpa-virt-err.l: New stderr output. * testsuite/gas/mips/xpa-err.s: New test source. * testsuite/gas/mips/xpa-virt-err.s: New test source. * testsuite/gas/mips/mips.exp: Run the new tests. binutils/ * testsuite/binutils-all/mips/mips-xpa-virt-1.d: New test. * testsuite/binutils-all/mips/mips-xpa-virt-2.d: New test. * testsuite/binutils-all/mips/mips-xpa-virt-3.d: New test. * testsuite/binutils-all/mips/mips-xpa-virt-4.d: New test. * testsuite/binutils-all/mips/mips-xpa-virt.s: New test source. * testsuite/binutils-all/mips/mips.exp: Run the new tests.
2017-06-30MIPS/opcodes: Correctly combine ASE flags for ASE_MIPS16E2_MT calculationMaciej W. Rozycki2-3/+20
Correct a commit 25499ac7ee92 ("MIPS16e2: Add MIPS16e2 ASE support") disassembler bug with the handling of the ASE_MIPS16E2_MT combination ASE flag, where the calculation uses MIPS ABI Flags directly rather than calculated internal ASE flags. Consequently code does not correctly set the ASE_MIPS16E2_MT flag when the MIPS16e2 ASE flag and the MT ASE flag come from different sources, i.e. one from the BFD chosen and the other one from MIPS ABI Flags. Fix this by using internal ASE_MT and ASE_MIPS16E2 flags in a separate subsequent step, factored out to a dedicated function for use with future combination ASE flags. Adjust the `mips16e2@mips16e2-mt-sub.d' test case accordingly, where the MT flag comes from the BFD selected for the disassembler and the MIPS16e2 flag comes from the ELF binary itself. opcodes/ * mips-dis.c (mips_calculate_combination_ases): New function. (mips_convert_abiflags_ases): Factor out ASE_MIPS16E2_MT calculation to the new function. (set_default_mips_dis_options): Call the new function. gas/ * testsuite/gas/mips/mips16e2@mips16e2-mt-sub.d: Adjust for the ASE_MIPS16E2_MT flag disassembler fix. * testsuite/gas/mips/mips16e2-interaptiv-mr2@mips16e2-mt-sub.d: Likewise.
2017-06-29[ARC] Use FOR_EACH_DISASSEMBLER_OPTION to iterate over optionsAnton Kolesov2-14/+11
This patch updates arc-dis.c:parse_disassembler_options to use a macro FOR_EACH_DISASSEMBLER_OPTION, which has been introduced in [1], instead of a homegrown solution to split option string. [1] https://sourceware.org/git/?p=binutils-gdb.git;a=commit;h=65b48a81 opcodes/ChangeLog: yyyy-mm-dd Anton Kolesov <Anton.Kolesov@synopsys.com> * arc-dis.c (parse_disassembler_options): Use FOR_EACH_DISASSEMBLER_OPTION.
2017-06-29[ARC] Fix handling of cpu=... disassembler option valueAnton Kolesov2-8/+14
There is a bug in handling of cpu=... disassembler option in case there are other options after it, for example, `cpu=EM,dsp'. In this case `EM,dsp' is treated as an option value, and strcasecmp reports is as non-equal to "EM". This is fixed by using disassembler_options_cmp function, which compares string treating `,' the same way as `\0'. This function also solves a problem with option order in parse_option. Previously, if several option had same prefix (e.g. fpud, fpuda), then the longer one should have been compared first, otherwise when longer option is passed it would be treated as a short one, because CONST_STRNEQ ("fpud", "fpuda") would be true. The order of options was correct for ARC, so there were no bugs per se, but with disassembler_option_cmp there is no risk of such a bug being introduced in the future. opcodes/ChangeLog: yyyy-mm-dd Anton Kolesov <Anton.Kolesov@synopsys.com> * arc-dis.c (parse_option): Use disassembler_options_cmp to compare disassembler option strings. (parse_cpu_option): Likewise. binutils/ChangeLog yyyy-mm-dd Anton Kolesov <Anton.Kolesov@synopsys.com> * testsuite/binutils-all/arc/double_store.s: New file. * testsuite/binutils-all/arc/objdump.exp: Tests for disassembler options. (do_objfile): New function. (check_assembly): Likewise.
2017-06-28[AArch64] Add dot product support for AArch64 to binutilsTamar Christina5-179/+265
gas/ * config/tc-aarch64.c (aarch64_reg_parse_32_64): Accept 4B. (aarch64_features): Added dotprod. * doc/c-aarch64.texi: Added dotprod. * testsuite/gas/aarch64/dotproduct.d: New. * testsuite/gas/aarch64/dotproduct.s: New. opcodes/ * aarch64-asm.c (aarch64_ins_reglane): Added 4B dotprod. * aarch64-dis.c (aarch64_ext_reglane): Likewise. * aarch64-tbl.h (QL_V3DOT, QL_V2DOT): New. (aarch64_feature_dotprod, DOT_INSN): New. (udot, sdot): New. * aarch64-dis-2.c: Regenerated. include/ * opcode/aarch64.h: (AARCH64_FEATURE_DOTPROD): New. (aarch64_insn_class): Added dotprod.
2017-06-28[ARM] Assembler and disassembler support Dot Product ExtensionJiong Wang2-0/+10
This patch add assembler and disassembler support for new Dot Product Extension. The support can be enabled through the new "+dotprod" extension. include/ * opcode/arm.h (FPU_NEON_EXT_DOTPROD): New macro. (FPU_ARCH_DOTPROD_NEON_VFP_ARMV8): New macro. gas/ * config/tc-arm.c (fpu_neon_ext_dotprod): New variable. (neon_scalar_for_mul): Improve comments. (do_neon_dotproduct): New function to encode Dot Product instructions. (do_neon_dotproduct_s): Wrapper function for signed Dot Product instructions. (do_neon_dotproduct_u): Wrapper function for unsigned Dot Product instructions. (insns): New entries for vsdot and vudot. (arm_extensions): New entry for "dotprod". * doc/c-arm.texi: Document new "dotprod" extension. * testsuite/gas/arm/dotprod.s: New test source. * testsuite/gas/arm/dotprod-illegal.s: New test source. * testsuite/gas/arm/dotprod.d: New test. * testsuite/gas/arm/dotprod-thumb2.d: New test. * testsuite/gas/arm/dotprod-illegal.d: New test. * testsuite/gas/arm/dotprod-legacy-arch.d: New test. * testsuite/gas/arm/dotprod-illegal.l: New error file. * testsuite/gas/arm/dotprod-legacy-arch.l: New error file. opcodes/ * arm-dis.c (coprocessor_opcodes): New entries for vsdot and vudot.
2017-06-28MIPS: Add Imagination interAptiv MR2 MIPS32r3 processor supportMaciej W. Rozycki5-73/+152
Add support for the Imagination interAptiv MR2 MIPS32r3 processor with the MIPS16e2 ASE as per documentation, including in particular: 1. Support for implementation-specific interAptiv MR2 COPYW and UCOPYW MIPS16e2 instructions[1], for assembly and disassembly, 2. Support for implementation-specific interAptiv MR2 SAVE and RESTORE regular MIPS instructions[2], for assembly and disassembly, 3. ELF binary file annotation for the interAptiv MR2 MIPS architecture extension. 4. Support for interAptiv MR2 architecture selection for assembly, in the form of the `-march=interaptiv-mr2' command-line option and its corresponding `arch=interaptiv-mr2' setting for the `.set' and `.module' pseudo-ops. 5. Support for interAptiv MR2 architecture selection for disassembly, in the form of the `mips:interaptiv-mr2' target architecture, for use e.g. with the `-m' command-line option for `objdump'. Parts of this change by Matthew Fortune and Andrew Bennett. References: [1] "MIPS32 interAptiv Multiprocessing System Software User's Manual", Imagination Technologies Ltd., Document Number: MD00904, Revision 02.01, June 15, 2016, Section 24.3 "MIPS16e2 Implementation Specific Instructions", pp. 878-883 [2] same, Chapter 25 "Implementation-specific Instructions", pp. 911-917 include/ * elf/mips.h (E_MIPS_MACH_IAMR2): New macro. (AFL_EXT_INTERAPTIV_MR2): Likewise. * opcode/mips.h: Document new operand codes defined. (INSN_INTERAPTIV_MR2): New macro. (INSN_CHIP_MASK): Adjust accordingly. (CPU_INTERAPTIV_MR2): New macro. (cpu_is_member) <CPU_INTERAPTIV_MR2>: New case. (MIPS16_ALL_ARGS): Rename to... (MIPS_SVRS_ALL_ARGS): ... this. (MIPS16_ALL_STATICS): Rename to... (MIPS_SVRS_ALL_STATICS): ... this. bfd/ * archures.c (bfd_mach_mips_interaptiv_mr2): New macro. * cpu-mips.c (I_interaptiv_mr2): New enum value. (arch_info_struct): Add "mips:interaptiv-mr2" entry. * elfxx-mips.c (_bfd_elf_mips_mach) <E_MIPS_MACH_IAMR2>: New case. (mips_set_isa_flags) <bfd_mach_mips_interaptiv_mr2>: Likewise. (bfd_mips_isa_ext) <bfd_mach_mips_interaptiv_mr2>: Likewise. (print_mips_isa_ext) <AFL_EXT_INTERAPTIV_MR2>: Likewise. (mips_mach_extensions): Add `bfd_mach_mipsisa32r3' and `bfd_mach_mips_interaptiv_mr2' entries. * bfd-in2.h: Regenerate. opcodes/ * mips-formats.h (INT_BIAS): New macro. (INT_ADJ): Redefine in INT_BIAS terms. * mips-dis.c (mips_arch_choices): Add "interaptiv-mr2" entry. (mips_print_save_restore): New function. (print_insn_arg) <OP_SAVE_RESTORE_LIST>: Update comment. (validate_insn_args) <OP_SAVE_RESTORE_LIST>: Remove `abort' call. (print_insn_args): Handle OP_SAVE_RESTORE_LIST. (print_mips16_insn_arg): Call `mips_print_save_restore' for OP_SAVE_RESTORE_LIST handling, factored out from here. * mips-opc.c (decode_mips_operand) <'-'> <'m'>: New case. (RD_31, RD_SP, WR_SP, MOD_SP, IAMR2): New macros. (mips_builtin_opcodes): Add "restore" and "save" entries. * mips16-opc.c (decode_mips16_operand) <'n', 'o'>: New cases. (IAMR2): New macro. (mips16_opcodes): Add "copyw" and "ucopyw" entries. binutils/ * readelf.c (get_machine_flags) <E_MIPS_MACH_IAMR2>: New case. (print_mips_isa_ext) <AFL_EXT_INTERAPTIV_MR2>: Likewise. * NEWS: Mention Imagination interAptiv MR2 processor support. gas/ * config/tc-mips.c (validate_mips_insn): Handle OP_SAVE_RESTORE_LIST specially. (mips_encode_save_restore, mips16_encode_save_restore): New functions. (match_save_restore_list_operand): Factor out SAVE/RESTORE operand insertion into the instruction word or halfword to these new functions. (mips_cpu_info_table): Add "interaptiv-mr2" entry. * doc/c-mips.texi (MIPS Options): Add `interaptiv-mr2' to the `-march=' argument list.
2017-06-23RISC-V: Fix SLTI disassemblyAndrew Waterman2-2/+7
2017-06-23 Andrew Waterman <andrew@sifive.com> * riscv-opc.c (riscv_opcodes): Mark I-type SLT instruction as an alias; do not mark SLTI instruction as an alias.
2017-06-21x86: CET v2.0: Update incssp and setssbsyH.J. Lu4-25/+41
Update x86 assembler and disassembler for CET v2.0: https://software.intel.com/sites/default/files/managed/4d/2a/control-flow-enforcement-technology-preview.pdf 1. incsspd and incsspq are changed to take a register opeand with a different opcode. 2. setssbsy is changed to take no opeand with a different opcode. gas/ * testsuite/gas/i386/cet-intel.d: Updated. * testsuite/gas/i386/cet.d: Likewise. * testsuite/gas/i386/x86-64-cet-intel.d: Likewise. * testsuite/gas/i386/x86-64-cet.d: Likewise. * testsuite/gas/i386/cet.s: Update incsspd and setssbsy tests. * testsuite/gas/i386/x86-64-cet.s: Likewise. opcodes/ * i386-dis.c (RM_0FAE_REG_5): Removed. (PREFIX_MOD_3_0F01_REG_5_RM_1): Likewise. (PREFIX_MOD_3_0F01_REG_5_RM_0): New. (PREFIX_MOD_3_0FAE_REG_5): Likewise. (prefix_table): Remove PREFIX_MOD_3_0F01_REG_5_RM_1. Add PREFIX_MOD_3_0F01_REG_5_RM_0. (prefix_table): Update PREFIX_MOD_0_0FAE_REG_5. Add PREFIX_MOD_3_0FAE_REG_5. (mod_table): Update MOD_0FAE_REG_5. (rm_table): Update RM_0F01_REG_5. Remove RM_0FAE_REG_5. * i386-opc.tbl: Update incsspd, incsspq and setssbsy. * i386-tbl.h: Regenerated.
2017-06-21x86: CET v2.0: Rename savessp to saveprevsspH.J. Lu4-3/+9
Replace savessp with saveprevssp for CET v2.0: https://software.intel.com/sites/default/files/managed/4d/2a/control-flow-enforcement-technology-preview.pdf gas/ * testsuite/gas/i386/cet-intel.d: Updated. * testsuite/gas/i386/cet.d: Likewise. * testsuite/gas/i386/x86-64-cet-intel.d: Likewise. * testsuite/gas/i386/x86-64-cet.d: Likewise. * testsuite/gas/i386/cet.s: Replace savessp with saveprevssp. * testsuite/gas/i386/x86-64-cet.s: Likewise. opcodes/ * i386-dis.c (prefix_table): Replace savessp with saveprevssp. * i386-opc.tbl: Likewise. * i386-tbl.h: Regenerated.
2017-06-21x86: CET v2.0: Update NOTRACK prefixH.J. Lu2-8/+13
Update NOTRACK prefix handling to support memory indirect branch for CET v2.0: https://software.intel.com/sites/default/files/managed/4d/2a/control-flow-enforcement-technology-preview.pdf gas/ * config/tc-i386.c (md_assemble): Update NOTRACK prefix check. * testsuite/gas/i386/notrack-intel.d: Updated. * testsuite/gas/i386/notrack.d: Likewise. * testsuite/gas/i386/notrackbad.l: Likewise. * testsuite/gas/i386/x86-64-notrack-intel.d: Likewise. * testsuite/gas/i386/x86-64-notrack.d: Likewise. * testsuite/gas/i386/x86-64-notrackbad.l: Likewise. * testsuite/gas/i386/notrack.s: Add NOTRACK prefix tests with memory indirect branch. * testsuite/gas/i386/x86-64-notrack.s: Likewise. * testsuite/gas/i386/notrackbad.s: Remove memory indirect branch with NOTRACK prefix. * testsuite/gas/i386/x86-64-notrackbad.s: Likewise. opcodes/ * i386-dis.c (reg_table): Swap indirEv with NOTRACK on "call{&|}" and "jmp{&|}". (NOTRACK_Fixup): Support memory indirect branch with NOTRACK prefix.
2017-06-19Prevent address violation when attempting to disassemble a corrupt score binary.Nick Clifton2-0/+6
PR binutils/21614 * score-dis.c (score_opcodes): Add sentinel.
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