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2005-10-03oops - delayed commit for addtion of Irish translation for gprof and opcodesNick Clifton4-2/+819
2005-09-302005-09-30 H.J. Lu <hongjiu.lu@intel.com>H.J. Lu4-890/+871
* Makefile.am: Run "make dep-am". * Makefile.in: Regenerated. * aclocal.m4: Likewise. * configure: Likewise.
2005-09-30 * Makefile.am: Bfin support.Catherine Moore8-138/+6139
* Makefile.in: Regenerated. * aclocal.m4: Regenerated. * bfin-dis.c: New file. * configure.in: Bfin support. * configure: Regenerated. * disassemble.c (ARCH_bfin): Define. (disassembler): Add case for bfd_arch_bfin.
2005-09-28gas/testsuite/Jan Beulich2-46/+74
2005-09-28 Jan Beulich <jbeulich@novell.com> * gas/i386/x86-64-stack.s, gas/i386/x86-64-stack.d, gas/i386/x86-64-stack-suffix.d, gas/i386/x86-64-stack-intel.d: New. * gas/i386/i386.exp: Run new tests. ld/testsuite/ 2005-09-28 Jan Beulich <jbeulich@novell.com> * ld-x86-64/tlspic.dd: Adjust. opcodes/ 2005-09-28 Jan Beulich <jbeulich@novell.com> * i386-dis.c (stack_v_mode): Renamed from branch_v_mode. (indirEv): Use it. (stackEv): New. (Ob64, Ov64): Rename to Ob, Ov. Delete unused original definitions. (dis386): Document and use new 'V' meta character. Use it for single-byte push/pop opcode forms. Use stackEv for mod-r/m push/pop opcode forms. Correct typo in 'pop ss'. Replace Ob64/Ov64 by Ob/Ov. (putop): 'q' suffix for 'T' and 'U' meta depends on DFLAG. Mark data prefix as used whenever DFLAG was examined. Handle 'V'. (intel_operand_size): Use stack_v_mode. (OP_E): Use stack_v_mode, but handle only the special case of 64-bit mode without operand size override here; fall through to v_mode case otherwise. (OP_REG): Special case rAX_reg ... rDI_reg only when 64-bit mode and no operand size override is present. (OP_J): Use get32s for obtaining the displacement also when rex64 is present.
2005-09-082005-09-08 Paul Brook <paul@codesourcery.com>Paul Brook2-2/+6
bfd/ * reloc.c: Rename BFD_RELOC_ARM_SMI to BFD_RELOC_ARM_SMC. * bfd-in2.h: Regenerate. * libbfd.h: Regenerate. opcodes/ * arm-dis.c (arm_opcodes, thumb32_opcodes): Rename smi to smc. gas/ * config/tc-arm.c (do_smi, do_t_smi): Rename ... (do_smc, do_t_smc): ... to this. (insns): Remane smi to smc. (md_apply_fix, tc_gen_reloc): Rename BFD_RELOC_ARM_SMI to BFD_RELOC_ARM_SMC. gas/testsuite/ * gas/arm/arch6zk.d: Rename smi to smc. * gas/arm/arch6zk.s: Ditto. * gas/arm/thumb32.d: Ditto. * gas/arm/thumb32.s: Ditto.
2005-09-06* mips-opc.c (MT32): New define.Chao-ying Fu3-5/+127
(mips_builtin_opcodes): Move "bc0f", "bc0fl", "bc0t", "bc0tl" to the bottom to avoid opcode collision with "mftr" and "mttr". Add MT instructions. * mips-dis.c (mips_arch_choices): Enable INSN_MT for mips32r2. (print_insn_args): Add supports for +t, +T, !, $, *, &, g operand formats.
2005-09-022005-09-02 Paul Brook <paul@codesourcery.com>Paul Brook2-1/+5
* arm-dis.c (coprocessor_opcodes): Add null terminator.
2005-09-022005-09-02 Paul Brook <paul@codesourcery.com>Paul Brook2-539/+743
bfd/ * libbdf.h: Regenerate. * bfd-in2.h: Regenerate. * reloc.c: Add BFD_RELOC_ARM_T32_CP_OFF_IMM and BFD_RELOC_ARM_T32_CP_OFF_IMM_S2. gas/ * config/tc-arm.c (encode_arm_cp_address): Use BFD_RELOC_ARM_T32_CP_OFF_IMM in thumb mode. (do_iwmmxt_wldstbh): Use BFD_RELOC_ARM_T32_CP_OFF_IMM_S2 in thumb mode. (md_assemble): Only allow coprocessor instructions when Thumb-2 is available. (cCE, cC3): Define. (insns): Use them for coprocessor instructions. (md_pcrel_from_section): Handle BFD_RELOC_ARM_T32_CP_OFF_IMM. (get_thumb32_insn): New function. (put_thumb32_insn): New function. (md_apply_fix): Handle BFD_RELOC_ARM_T32_CP_OFF_IMM and BFD_RELOC_ARM_T32_CP_OFF_IMM_S2. gas/testsuite/ * gas/arm/vfp-bad_t2.d, gas/arm/vfp-bad_t2.l, arm/vfp-bad_t2.s, gas/arm/vfp1_t2.d, gas/arm/vfp1_t2.s, gas/arm/vfp1xD_t2.d, gas/arm/vfp1xD_t2.s, gas/arm/vfp2_t2.d, gas/arm/vfp2_t2.s): New files. opcodes/ * arm-dis.c (coprocessor_opcodes): New. (arm_opcodes, thumb32_opcodes): Remove coprocessor insns. (print_insn_coprocessor): New function. (print_insn_arm): Use print_insn_coprocessor. Remove coprocessor format characters. (print_insn_thumb32): Use print_insn_coprocessor.
2005-08-302005-08-30 Paul Brook <paul@codesourcery.com>Paul Brook2-2/+6
opcodes/ * arm-dis.c (thumb_opcodes): Disassemble sub(3) as subs. gas/testsuite/ * gas/arm/thumb.d: Change "sub rn, rn, rn" to "subs rn, rn, rn". * gas/arm/thumb32.d: Ditto.
2005-08-26opcodes/Jan Beulich2-89/+89
2005-08-26 Jan Beulich <jbeulich@novell.com> * i386-dis.c (intel_operand_size): New, broken out from OP_E for re-use. (OP_E): Call intel_operand_size, move call site out of mode dependent code. (OP_OFF): Call intel_operand_size if suffix_always. Remove ATTRIBUTE_UNUSED from parameters. (OP_OFF64): Likewise. (OP_ESreg): Call intel_operand_size. (OP_DSreg): Likewise. (OP_DIR): Use colon rather than semicolon as separator of far jump/call operands. gas/testsuite/ 2005-08-26 Jan Beulich <jbeulich@novell.com> * gas/i386/intelok.d: Adjust.
2005-08-25* mips-opc.c (WR_a, RD_a, MOD_a, DSP_VOLA, D32): New define.Chao-ying Fu3-4/+211
(mips_builtin_opcodes): Add DSP instructions. * mips-dis.c (mips_arch_choices): Enable INSN_DSP for mips32, mips32r2, mips64, mips64r2. (print_insn_args): Add supports for 3, 4, 5, 6, 7, 8, 9, 0, :, ', @ operand formats.
2005-08-23* mips16-opc.c (mips16_opcodes): Add the MIPS16e jalrc/jrcDavid Ung2-0/+9
instructions to the table.
2005-08-18Remove a29k files.Alan Modra2-358/+1
2005-08-18Remove a29k support.Alan Modra7-22/+9
2005-08-15gas/Daniel Jacobowitz3-1/+13
* config/tc-ppc.c (parse_cpu): Add -me300 support. (md_show_usage): Likewise. * doc/c-ppc.texi (PowerPC-Opts): Document it. include/opcode/ * ppc.h (PPC_OPCODE_E300): Define. opcodes/ * ppc-dis.c (powerpc_dialect): Handle e300. (print_ppc_disassembler_options): Likewise. * ppc-opc.c (PPCE300): Define. (powerpc_opcodes): Mark icbt as available for the e300. binutils/ * doc/binutils.texi (objdump): Document -M e300.
2005-08-14 * hppa-dis.c (print_insn_hppa): Don't print '%' before register names.Dave Anglin2-4/+9
Use "rp" instead of "%r2" in "b,l" insns.
2005-08-12 * s390-dis.c (print_insn_s390): Print unsigned operands with %u.Martin Schwidefsky5-12/+109
* s390-mkopc.c (s390_opcode_cpu_val): Add support for cpu type z9-109. (main): Likewise. * s390-opc.c (I32_16, U32_16, M_16): Add defines 32 bit immediates and 4 bit optional masks. (INSTR_RIL_RI, INSTR_RIL_RU, INSTR_RRF_M0RR, INSTR_RSE_CCRD, INSTR_RSY_CCRD, INSTR_SSF_RRDRD): Add new instruction formats. (MASK_RIL_RI, MASK_RIL_RU, MASK_RRF_M0RR, MASK_RSE_CCRD, MASK_RSY_CCRD, MASK_SSF_RRDRD): Likewise. (s390_opformats): Likewise. * s390-opc.txt: Add new instructions for cpu type z9-109.
2005-08-05 * hppa-dis.c (print_insn_hppa): Prefix 21-bit values with "L%".Dave Anglin2-0/+5
2005-07-292005-07-29 Paul Brook <paul@codesourcery.com>Paul Brook2-4/+8
bfd/ * reloc.c: Add BFD_RELOC_ARM_T32_ADD_PC12. * bfd-in2.h: Regenerate. * libbfd.h: Regenerate. gas/ * config/tc-arm.c (T16_32_TAB): Add "addr". Fix encoding of push and pop. (do_t_addr): Implement 32-bit variant. (do_t_push_pop): Make some errors warnings. Handle single register 32-bit case. (insns): Use tCE for adr. (md_pcrel_from_section): Handle BFD_RELOC_ARM_T32_ADD_PC12. (md_apply_fix): Ditto. gas/testsuite/ * gas/arm/thumb32.d: Fix expected output for writeback addressing modes. Add single high reg push/pop test. * gas/asm/thumb32.s: Add single high reg push/pop test. opcodes/ * arm-dis.c: Fix disassebly of thumb2 writeback addressing modes.
2005-07-292005-07-29 Paul Brook <paul@codesourcery.com>Paul Brook2-2/+7
bfd/ * reloc.c (BFD_RELOC_ARM_T32_IMM12): Add. * bfd-in2.h: Regeenrate. * libbfd.h: Regenerate. gas/ * config/tc-arm.c (parse_tb): New function. (enum operand_parse_code): Add OP_TB. (parse_operands): Handle OP_TB. (do_t_add_sub_w, do_t_tb): New functions. (insns): Add entries for addw, subw, tbb and tbh. (md_apply_fix): Handle BFD_RELOC_ARM_T32_IMM12. gas/testsuite/ * gas/arm/thumb32.s: Add tests for addw, subw, tbb and tbh. * gas/arm/thumb32.d: Ditto. opcodes/ * arm-dis.c (thumb32_opc): Fix addressing mode for tbh. (print_insn_thumb32): Fix decoding of thumb2 'I' operands.
2005-07-26missed from 2005-07-18 commitAlan Modra1-2/+2
2005-07-26[bfd]DJ Delorie3-5/+120
* reloc.c: Remove unused M32C relocs, add BFD_RELOC_M32C_HI8. * libbfd.h: Regenerate. * bfd-in2.h: Regenerate. * elf32-m32c.c (m32c_elf_howto_table): Add R_M32C_8, R_M32C_LO16, R_M32C_HI8, R_M32C_HI16. (m32c_reloc_map): Likewise. (m32c_elf_relocate_section): Add R_M32C_HI8 and R_M32C_HI16. [cpu] * m32c.opc (parse_unsigned8): Add %dsp8(). (parse_signed8): Add %hi8(). (parse_unsigned16): Add %dsp16(). (parse_signed16): Add %lo16() and %hi16(). (parse_lab_5_3): Make valuep a bfd_vma *. [gas] * config/tc-m32c.c (md_cgen_lookup_reloc): Add 8 bit operands. Support %mod() modifiers from opcodes. * doc/c-m32c.texi (M32C-Modifiers): New section. [include/elf] * m32c.h: Add R_M32C_8, R_M32C_LO16, R_M32C_HI8, and R_M32C_HI16. [opcodes] * m32c-asm.c Regenerate. * m32c-dis.c Regenerate.
2005-07-20* disassemble.c (disassemble_init_for_target): M32C ISAs areDJ Delorie2-2/+7
enums, so convert them to bit masks, which attributes are.
2005-07-19Add ChangeLog entries for yesterdays deltas (oops!)Nick Clifton1-0/+16
2005-07-19gas/testsuite/H.J. Lu2-3/+8
2005-07-18 H.J. Lu <hongjiu.lu@intel.com> * gas/i386/i386.exp: Add suffix. * gas/i386/suffix.d: New file. * gas/i386/suffix.s: Likewise. opcodes/ 2005-07-18 H.J. Lu <hongjiu.lu@intel.com> * i386-dis.c (PNI_Fixup): Update comment. (VMX_Fixup): Properly handle the suffix check.
2005-07-18Fix building for MS1 and M32C.Nick Clifton9-1021/+783
Restore alpha- sorting to the architecture tables.
2005-07-17 * hppa-dis.c (print_insn_hppa): Add space after 'w' in wide-modeDave Anglin2-1/+6
mfctl disassembly.
2005-07-16bfd/Alan Modra4-45/+94
* Makefile.am: Run "make dep-am". * Makefile.in: Regenerate. opcodes/ * Makefile.am: Run "make dep-am". (stamp-m32c): Fix cpu dependencies. * Makefile.in: Regenerate. * ip2k-dis.c: Regenerate. binutils/ * Makefile.am: Run "make dep-am". * Makefile.in: Regenerate. gas/ * Makefile.am: Run "make dep-am". * Makefile.in: Regenerate. ld/ * Makefile.am: Run "make dep-am". (emipsidt.c, emipsidtl.c): Depend on generic.em. * Makefile.in: Regenerate.
2005-07-15gas/H.J. Lu2-6/+76
2007-07-15 H.J. Lu <hongjiu.lu@intel.com> * gas/config/tc-i386.h (CpuVMX): New. (CpuUnknownFlags): Add CpuVMX. gas/testsuite/ 2007-07-15 H.J. Lu <hongjiu.lu@intel.com> * gas/i386/i386.exp: Add vmx and x86-64-vmx. * gas/i386/vmx.d: New file. * gas/i386/vmx.s: Likewise. * gas/i386/x86-64-vmx.d: Likewise. * gas/i386/x86-64-vmx.s: Likewise. include/opcode/ 2007-07-15 H.J. Lu <hongjiu.lu@intel.com> * i386.h (i386_optab): Support Intel VMX Instructions. opcodes/ 2007-07-15 H.J. Lu <hongjiu.lu@intel.com> * i386-dis.c (OP_VMX): New. Handle Intel VMX Instructions. (VMX_Fixup): New. Fix up Intel VMX Instructions. (Em): New. (Gm): New. (VM): New. (dis386_twobyte): Updated entries 0x78 and 0x79. (twobyte_has_modrm): Likewise. (grps): Use OP_VMX in the "sgdtIQ" entry. Updated GRP9. (OP_G): Handle m_mode.
2005-07-14ChangeLog:Jim Blandy18-493/+155222
2005-07-14 Jim Blandy <jimb@redhat.com> * configure.in: Add cases for Renesas m32c. * configure: Regenerated. bfd/ChangeLog: 2005-07-14 Jim Blandy <jimb@redhat.com> Add support for m32c-*-elf (Renesas m32c and m16c). * Makefile.am (ALL_MACHINES): Add cpu-m32c.lo. (ALL_MACHINES_CFILES): Add cpu-m32c.c. (BFD32_BACKENDS): Add elf32-m32c.lo. (BFD32_BACKENDS_CFILES): Add elf32-m32c.c. (cpu-m32c.lo, elf32-m32c.lo): New rules, generated by 'make dep-am'. * Makefile.in: Regenerated. * archures.c (bfd_arch_m32c, bfd_mach_m16c, bfd_mach_m32c): New arch and mach codes. (bfd_m32c_arch): New arch info object. (bfd_archures_list): List bfd_m32c_arch. * bfd-in2.h: Regenerated. * config.bfd: Add case for the m32c. * configure.in: Add case for the m32c. * configure: Regenerated. * cpu-m32c.c, elf32-m32c.c: New files. * libbfd.h: Regenerated. * targets.c (bfd_elf32_m32c_vec): Declare. (_bfd_target_vector): List bfd_elf32_m32c_vec. binutils/ChangeLog: 2005-07-14 Jim Blandy <jimb@redhat.com> * readelf.c: #include "elf/m32c.h" (guess_is_rela, dump_relocations, get_machine_name): Add cases for EM_M32C. * Makefile.am (readelf.o): Update dependencies. * Makefile.in: Regenerated. cpu/ChangeLog: 2005-07-14 Jim Blandy <jimb@redhat.com> * m32c.cpu, m32c.opc: Machine description for the Renesas M32C. gas/ChangeLog: 2005-07-14 Jim Blandy <jimb@redhat.com> Add support for the Renesas M32C. * Makefile.am (CPU_TYPES): List m32c. (TARGET_CPU_CFILES): List config/tc-m32c.c. (TARGET_CPU_HFILES): List config/tc-m32c.h. * configure.in: Add case for m32c. * configure.tgt: Add cases for m32c and m32c-*-elf. * configure: Regenerated. * config/tc-m32c.c, config/tc-m32c.h: New files. * doc/Makefile.am (CPU_DOCS): Add c-m32c.texi. * doc/Makefile.in: Regenerated. * doc/all.texi: Set M32C. * doc/as.texinfo: Add text for the M32C-specific options and line comment characters, and refer to c-m32c.texi. * doc/c-m32c.texi: New file. include/ChangeLog: 2005-07-14 Jim Blandy <jimb@redhat.com> * dis-asm.h (print_insn_m32c): New declaration. include/elf/ChangeLog: 2005-07-14 Jim Blandy <jimb@redhat.com> Add support for Renesas M32C and M16C. * common.h (EM_M32C): New machine number. * m32c.h: New file. ld/ChangeLog: 2005-07-14 Jim Blandy <jimb@redhat.com> Add support for the Renesas M32C and M16C. * Makefile.am (ALL_EMULATIONS): Add eelf32m32c.o. (eelf32m32c.c): New target. * Makefile.in: Regenerated. * configure.tgt: Add case for m32c-*-elf. * emulparams/elf32m32c.sh: New file. opcodes/ChangeLog: 2005-07-14 Jim Blandy <jimb@redhat.com> Add support for the Renesas M32C and M16C. * m32c-asm.c, m32c-desc.c, m32c-dis.c, m32c-ibld.c, m32c-opc.c: New. * m32c-desc.h, m32c-opc.h: New. * Makefile.am (HFILES): List m32c-desc.h and m32c-opc.h. (CFILES): List m32c-asm.c, m32c-desc.c, m32c-dis.c, m32c-ibld.c, m32c-opc.c. (ALL_MACHINES): List m32c-asm.lo, m32c-desc.lo, m32c-dis.lo, m32c-ibld.lo, m32c-opc.lo. (CLEANFILES): List stamp-m32c. (M32C_DEPS): List stamp-m32c, if CGEN_MAINT. (CGEN_CPUS): Add m32c. (m32c-asm.c, m32c-desc.c, m32c-dis.c, m32c-ibld.c, m32c-opc.c) (m32c-desc.h, m32c-opc.h): Depend on M32C_DEPS. (m32c_opc_h): New variable. (stamp-m32c, m32c-asm.lo, m32c-desc.lo, m32c-dis.lo, m32c-ibld.lo) (m32c-opc.lo): New rules. * Makefile.in: Regenerated. * configure.in: Add case for bfd_m32c_arch. * configure: Regenerated. * disassemble.c (ARCH_m32c): New. [ARCH_m32c]: #include "m32c-desc.h". (disassembler) [ARCH_m32c]: Add case for bfd_arch_m32c. (disassemble_init_for_target) [ARCH_m32c]: Same. * cgen-ops.h, cgen-types.h: New files. * Makefile.am (HFILES): List them. * Makefile.in: Regenerated.
2005-07-07Kaveh Ghazi's printf format attribute checking patch.Jim Wilson28-134/+146
bfd: * elf32-xtensa.c (vsprint_msg): Add format attribute. Fix format bugs. * vms.h (_bfd_vms_debug): Add format attribute. (_bfd_vms_debug, _bfd_hexdump): Fix typos. binutils: * bucomm.h (report): Add format attribute. * dlltool.c (inform): Likewise. * dllwrap.c (display, inform, warn): Likewise. * objdump.c (objdump_sprintf): Likewise. * readelf.c (error, warn): Likewise. Fix format bugs. gas: * config/tc-tic30.c (debug): Add format attribute. Fix format bugs. include: * dis-asm.h (fprintf_ftype): Add format attribute. opcodes: * arc-dis.c, arm-dis.c, cris-dis.c, crx-dis.c, d10v-dis.c, d30v-dis.c, fr30-dis.c, h8300-dis.c, h8500-dis.c, i860-dis.c, ia64-dis.c, ip2k-dis.c, m10200-dis.c, m10300-dis.c, m88k-dis.c, mcore-dis.c, mips-dis.c, ms1-dis.c, or32-dis.c, ppc-dis.c, sh64-dis.c, sparc-dis.c, tic4x-dis.c, tic80-dis.c, v850-dis.c: Fix format bugs. * ia64-gen.c (fail, warn): Add format attribute. * or32-opc.c (debug): Likewise.
2005-07-07arm-dis.c (opcode32 arm_opcodes): Fix ARM VFP fadds instruction disassemblyNick Clifton2-1/+6
pattern. vfp1xD.d: Adjust expected fadds disassemblies now that the dissassembler has been fixed.
2005-07-06 * Makefile.am (stamp-m32r): Fix path to cpu files.Alan Modra5-21/+57
(stamp-m32r, stamp-iq2000): Likewise. * Makefile.in: Regenerate. * m32r-asm.c: Regenerate. * po/POTFILES.in: Remove arm-opc.h. Add ms1-asm.c, ms1-desc.c, ms1-desc.h, ms1-dis.c, ms1-ibld.c, ms1-opc.c, ms1-opc.h.
2005-07-05Fix compile time warnings from a GCC 4.0 compilerNick Clifton3-22/+18
2005-07-05gas/Jan Beulich2-3/+81
2005-07-05 Jan Beulich <jbeulich@novell.com> * config/tc-i386.h (CpuSVME): New. (CpuUnknownFlags): Include CpuSVME. * config/tc-i386.c (cpu_arch): Add .pacifica and .svme. Add opteron as alias of sledgehammer. (md_assemble): Include invlpga in the check for insns with two source operands. (process_operands): Include SVME insns in the check for ignored segment overrides. Adjust diagnostic. (i386_index_check): Special-case SVME insns with memory operands. gas/testsuite/ 2005-07-05 Jan Beulich <jbeulich@novell.com> * gas/i386/svme.d: New. * gas/i386/svme.s: New. * gas/i386/svme64.d: New. * gas/i386/i386.exp: Run new tests. include/opcode/ 2005-07-05 Jan Beulich <jbeulich@novell.com> * i386.h (i386_optab): Add new insns. opcodes/ 2005-07-05 Jan Beulich <jbeulich@novell.com> * i386-dis.c (SVME_Fixup): New. (grps): Use it for the lidt entry. (PNI_Fixup): Call OP_M rather than OP_E. (INVLPG_Fixup): Likewise.
2005-07-042005-07-04 H.J. Lu <hongjiu.lu@intel.com>H.J. Lu2-0/+11
* tic30-dis.c (cnvt_tmsfloat_ieee): Use HUGE_VALF if defined.
2005-07-01Update function declarations to ISO C90 formattingNick Clifton93-9412/+7693
2005-06-23 * m68k-dis.c: Use ISC C90.Ben Elliston3-54/+32
* m68k-opc.c: Formatting fixes.
2005-06-16* mips16-opc.c (mips16_opcodes): Add the following MIPS16eDavid Ung2-0/+12
instructions to the table; seb/seh/sew/zeb/zeh/zew.
2005-06-152005-06-15 Dave Brolley <brolley@redhat.com>Dave Brolley13-8/+5973
Contribute Morpho ms1 on behalf of Red Hat * ms1-asm.c, ms1-desc.c, ms1-dis.c, ms1-ibld.c, ms1-opc.c, ms1-opc.h: New files, Morpho ms1 target. 2004-05-14 Stan Cox <scox@redhat.com> * disassemble.c (ARCH_ms1): Define. (disassembler): Handle bfd_arch_ms1 2004-05-13 Michael Snyder <msnyder@redhat.com> * Makefile.am, Makefile.in: Add ms1 target. * configure.in: Ditto.
2005-06-08opcodes:Zack Weinberg5-134/+91
* arm-opc.h: Delete; fold contents into ... * arm-dis.c: ... here. Move includes of internal COFF headers next to includes of internal ELF headers. (streq, WORD_ADDRESS, BDISP, BDISP23): Delete, unused. (struct arm_opcode): Rename struct opcode32. Make 'assembler' const. (struct thumb_opcode): Rename struct opcode16. Make 'assembler' const. (arm_conditional, arm_fp_const, arm_shift, arm_regname, regnames) (iwmmxt_wwnames, iwmmxt_wwssnames): Make const. (regnames): Remove iWMMXt coprocessor register sets. (iwmmxt_regnames, iwmmxt_cregnames): New statics. (get_arm_regnames): Adjust fourth argument to match above changes. (set_iwmmxt_regnames): Delete. (print_insn_arm): Constify 'c'. Use ISO syntax for function pointer calls. Expand sole use of BDISP. Use iwmmxt_regnames and iwmmxt_cregnames, not set_iwmmxt_regnames. (print_insn_thumb16, print_insn_thumb32): Constify 'c'. Use ISO syntax for function pointer calls. include: * dis-asm.h (get_arm_regnames): Update prototype.
2005-06-07 * arm-dis.c: Split up the comments describing the format codes, soZack Weinberg2-139/+118
that the ARM and 16-bit Thumb opcode tables each have comments preceding them that describe all the codes, and only the codes, valid in those tables. (32-bit Thumb table is already like this.) Reorder the lists in all three comments to match the order in which the codes are implemented. Remove all forward declarations of static functions. Convert all function definitions to ISO C format. (print_insn_arm, print_insn_thumb16, print_insn_thumb32): Return nothing. (print_insn_thumb16): Remove unused case 'I'. (print_insn): Update for changed calling convention of subroutines.
2005-05-25gas/testsuite/Jan Beulich2-17/+56
2005-05-25 Jan Beulich <jbeulich@novell.com> * gas/i386/intelok.d: Account for 32-bit displacements being shown in hex. opcodes/ 2005-05-25 Jan Beulich <jbeulich@novell.com> * i386-dis.c (OP_E): In Intel mode, display 32-bit displacements in hex (but retain it being displayed as signed). Remove redundant checks. Add handling of displacements for 16-bit addressing in Intel mode.
2005-05-25opcodes/Jan Beulich2-10/+11
2005-05-25 Jan Beulich <jbeulich@novell.com> * i386-dis.c (prefix_name): Remove pointless mode_64bit check. (OP_E): Remove redundant REX_EXTZ handling. Remove pointless masking of 'rm' in 16-bit memory address handling.
2005-05-19 * ppc-dis.c (powerpc_dialect): Handle "-Mpower5".Alan Modra3-5/+35
(print_ppc_disassembler_options): Document it. * ppc-opc.c (SCV_LEV): Define. (LEV): Allow optional operand. (POWER5): Define. (powerpc_opcodes): Extend "sc". Adjust "svc" and "svcl". Add "hrfid", "popcntb", "fsqrtes", "fsqrtes.", "fre" and "fre.".
2005-05-192005-05-19 Kelley Cook <kcook@gcc.gnu.org>Kelley Cook2-1/+4
* Makefile.in: Regenerate.
2005-05-18include/elf:Zack Weinberg2-339/+986
* arm.h: Import complete list of official relocation names and numbers from AAELF. Define FAKE_RELOCs for old names. Remove a few old names no longer used anywhere. bfd: * elf32-arm.c: Wherever possible, use official reloc names from AAELF. (elf32_arm_howto_table, elf32_arm_tls_gd32_howto) (elf32_arm_tls_ldo32_howto, elf32_arm_tls_ldm32_howto) (elf32_arm_tls_le32_howto, elf32_arm_tls_ie32_howto) (elf32_arm_vtinherit_howto, elf32_arm_vtentry_howto) (elf32_arm_pc11_howto, elf32_arm_thm_pc9_howto, elf32_arm_got_prel) (elf32_arm_r_howto): Replace with elf32_arm_howto_table_1, elf32_arm_howto_table_2, and elf32_arm_howto_table_3. Add many new relocations from AAELF. (elf32_arm_howto_from_type): Update to match. (elf32_arm_reloc_map): Add entries for R_ARM_THM_JUMP24, R_ARM_THM_JUMP11, R_ARM_THM_JUMP19, R_ARM_THM_JUMP8, R_ARM_THM_JUMP6, R_ARM_GNU_VTINHERIT, and R_ARM_GNU_VTENTRY. (elf32_arm_reloc_type_lookup): Use elf32_arm_howto_from_type. (elf32_arm_final_link_relocate): Add support for R_ARM_THM_JUMP24, R_ARM_THM_JUMP19, R_ARM_THM_JUMP6. Remove case entries redundant with default. * reloc.c: Reorganize ARM relocations. Add Thumb assembler-internal relocations BFD_RELOC_ARM_T32_OFFSET_U8, BFD_RELOC_ARM_T32_OFFSET_IMM, BFD_RELOC_ARM_T32_IMMEDIATE. Add visible relocations BFD_RELOC_THUMB_PCREL_BRANCH7, BFD_RELOC_THUMB_BRANCH20, BFD_RELOC_THUMB_BRANCH25. Delete unused relocations BFD_RELOC_ARM_GOT12, BFD_RELOC_ARM_COPY. * bfd-in2.h, libbfd.h: Regenerate. opcodes: * arm-dis.c (thumb_opcodes): Add disassembly for V6T2 16-bit instructions. Adjust disassembly of some opcodes to match unified syntax. (thumb32_opcodes): New table. (print_insn_thumb): Rename print_insn_thumb16; don't handle two-halfword branches here. (print_insn_thumb32): New function. (print_insn): Choose among print_insn_arm, print_insn_thumb16, and print_insn_thumb32. Be consistent about order of halfwords when printing 32-bit instructions. gas: * hash.c (hash_lookup): Add len parameter. All callers changed. (hash_find_n): New interface. * hash.h: Prototype hash_find_n. * sb.c: Include as.h. (scrub_from_sb, sb_to_scrub, scrub_position): New statics. (sb_scrub_and_add_sb): New interface. * sb.h: Prototype sb_scrub_and_add_sb. * input-scrub.c (input_scrub_include_sb): Use sb_scrub_and_add_sb. * config/tc-arm.h (TC_FORCE_RELOCATION_LOCAL): Remove reference to BFD_RELOC_ARM_GOT12 which is never generated. * config/tc-arm.c: Rewrite, adding Thumb-2 support. gas/testsuite: * gas/arm/arm.exp: Convert all existing "gas_test" tests to "run_dump_test" tests. Run more tests unconditionally. Run new tests. * gas/arm/arch4t.s, gas/arm/arch6zk.s, gas/arm/arm3.s, gas/arm/arm6.s * gas/arm/arm7dm.s, gas/arm/bignum1.s, gas/arm/float.s * gas/arm/immed.s, gas/arm/iwmmxt.s, gas/arm/offset.s, gas/arm/thumb.s: Adjust to work as a dump test. * gas/arm/arch4t.d, gas/arm/arch6zk.d, gas/arm/arm3.d, gas/arm/arm6.d * gas/arm/arm7dm.d, gas/arm/bignum1.d, gas/arm/float.d * gas/arm/immed.d, gas/arm/iwmmxt.d, gas/arm/offset.d, gas/arm/thumb.d: New files. * gas/arm/armv1-bad.l, gas/arm/armv1-bad.s: Remove tests for diagnostics that don't happen in the first pass anymore. * gas/arm/iwmmxt-bad.l, gas/arm/r15-bad.l, gas/arm/req.l * gas/arm/vfp-bad.l: Update expected diagnostics. * gas/arm/pic.d: Update expected reloc name. * gas/arm/thumbv6.d: CPY no longer appears in disassembly. * gas/arm/r15-bad.s: Avoid two-argument mul. * gas/arm/req.s: Adjust comments. * gas/arm/maverick.d, gas/arm/maverick.s: Avoid inappropriate use of PC. * gas/arm/macro-1.d, gas/arm/macro1.s * gas/arm/t16-bad.l, gas/arm/t16-bad.s * gas/arm/tcompat.d, gas/arm/tcompat.s * gas/arm/tcompat2.d, gas/arm/tcompat2.s * gas/arm/thumb32.d, gas/arm/thumb32.s New test pair. ld/testsuite: * ld-arm/mixed-app.d: Adjust expected disassembly a little.
2005-05-07gas/testsuite/H.J. Lu2-1/+22
2005-05-07 H.J. Lu <hongjiu.lu@intel.com> PR 843 * gas/i386/i386.exp: Add x86-64-branch. * gas/i386/x86-64-branch.d: New. * gas/i386/x86-64-branch.s: New. opcodes/ 2005-05-07 H.J. Lu <hongjiu.lu@intel.com> PR 843 * i386-dis.c (branch_v_mode): New. (indirEv): Use branch_v_mode instead of v_mode. (OP_E): Handle branch_v_mode.
2005-05-072005-05-07 H.J. Lu <hongjiu.lu@intel.com>H.J. Lu2-1/+6
* d10v-dis.c (dis_2_short): Support 64bit host.
2005-05-07Update Dutch translationNick Clifton2-153/+178
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