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2018-04-04i386: Clear vex instead of vex.evexH.J. Lu2-6/+8
"vex" has many fields to control how to decode an instruction. Clear all fields in "vex" before decoding an instruction to avoid using values left from the previous instruction. gas/ PR binutils/23025 * testsuite/gas/i386/prefix.s: Add tests for vcvtpd2dq with VEX and EVEX prefixes. * testsuite/gas/i386/prefix.d: Updated. opcodes/ PR binutils/23025 * i386-dis.c (get_valid_dis386): Don't set vex.prefix nor vex.w to 0. (print_insn): Clear vex instead of vex.evex.
2018-04-04Update Spanish translations for ld/ opcodes/ and gold/ sub-directoriesNick Clifton2-381/+1048
2018-03-28x86: drop VecESizeJan Beulich5-7936/+7936
It again can be inferred from other information. The vpopcntd templates all need to have Dword added to their memory operands; the lack thereof was actually a bug preventing certain Intel syntax code to assemble, so test cases get extended.
2018-03-28x86: convert broadcast insn attribute to booleanJan Beulich4-1981/+1979
The (only) valid broadcast type for an insn can be inferred from other information.
2018-03-28x86: fold to-scalar-int conversion insnsJan Beulich3-487/+83
2018-03-28x86: don't show suffixes for to-scalar-int conversion insnsJan Beulich2-24/+20
In the course of folding their patterns (possible now that the pointless and partly even bogus VecESize are no longer in the way) I've noticed that vcvt*2usi, other than their vcvt*2si counterparts, don't allow for any suffixes. As that is supposedly intentional, make the disassembler consistently omit suffixes for all to-scalar-int conversion insns.
2018-03-28Enhance the AARCH64 assembler to support LDFF1xx instructions which use ↵Nick Clifton6-571/+646
REG+REG addressing with an assumed offset register. PR 22988 opcode * opcode/aarch64.h (enum aarch64_opnd): Add AARCH64_OPND_SVE_ADDR_R. opcodes * aarch64-tbl.h (aarch64_opcode_table): Add entries for LDFF1xx instructions with only a base address register. * aarch64-opc.c (operand_general_constraint_met_p): Add code to handle AARHC64_OPND_SVE_ADDR_R. (aarch64_print_operand): Likewise. * aarch64-asm-2.c: Regenerate. * aarch64_dis-2.c: Regenerate. * aarch64-opc-2.c: Regenerate. gas * config/tc-aarch64.c (parse_operands): Add code to handle AARCH64_OPN_SVE_ADDR_R. * testsuite/gas/aarch64/sve.s: Add tests for LDFF1xx instructions with an assumed XZR offset address register. * testsuite/gas/aarch64/sve.d: Update expected disassembly.
2018-03-22x86: drop pointless VecESizeJan Beulich3-952/+958
The attribute is meaningful only in templates allowing embedded broadcast. Drop them everywhere else.
2018-03-22x86: drop remaining redundant DispNJan Beulich2-75/+81
A few of them were missed in commit 7ac2002247 ("x86: derive DispN from BaseIndex") and also couldn't be removed by subsequent commits touching certain templates anyway.
2018-03-22x86: fix swapped operand handling for BNDMOVJan Beulich4-7/+23
The wrong placement of the Load attribute in the templates prevented this from working. The disassembler also didn't handle this consistently with other similar dual-encoding insns.
2018-03-22x86/Intel: fix fallout from earlier template foldingJan Beulich3-25/+122
While many templates allowing multiple suitably matching XMM/YMM/ZMM operand sizes can be folded, a few need to be split in order to not wrongly accept "xmmword ptr" operands when only XMM registers are permitted (and memory operands are more narrow). Add a test case validating this.
2018-03-22x86: fold a few XOP templatesJan Beulich3-236/+50
Also add a new test case verifying that mixed operands of SIMD insns with a size-less memory operand in the middle are properly rejected.
2018-03-14RISC-V: Add .insn support.Jim Wilson2-0/+78
gas/ChangeLog 2018-03-07 Kito Cheng <kito.cheng@gmail.com> * config/tc-riscv.c (opcode_name_list): New. (opcode_names_hash): Likewise. (init_opcode_names_hash): Likewise. (opcode_name_lookup): Likewise. (validate_riscv_insn): New argument length, and add new format which used in .insn directive. (md_begin): Refine hash table initialization logic into init_opcode_hash. (init_opcode_hash): New. (my_getOpcodeExpression): Parse opcode name for .insn. (riscv_ip): New argument hash, able to handle .insn directive. (s_riscv_insn): Handler for .insn directive. (riscv_pseudo_table): New entry for .insn. * doc/c-riscv.texi: Add documentation for .insn directive. * testsuite/gas/riscv/insn.d: Add testcase for .insn directive. * testsuite/gas/riscv/insn.s: Likewise. include/ChangeLog 2018-03-07 Kito Cheng <kito.cheng@gmail.com> * opcode/riscv.h (OP_MASK_FUNCT3): New. (OP_SH_FUNCT3): Likewise. (OP_MASK_FUNCT7): Likewise. (OP_SH_FUNCT7): Likewise. (OP_MASK_OP2): Likewise. (OP_SH_OP2): Likewise. (OP_MASK_CFUNCT4): Likewise. (OP_SH_CFUNCT4): Likewise. (OP_MASK_CFUNCT3): Likewise. (OP_SH_CFUNCT3): Likewise. (riscv_insn_types): Likewise. opcodes/ChangeLog 2018-03-07 Kito Cheng <kito.cheng@gmail.com> * riscv-opc.c (riscv_insn_types): New.
2018-03-13Updated Russian and Brazilian Portuguese translations.Nick Clifton2-3/+7
ld * po/pt_BR.po: Updated Brazilian Portuguese translation. opcodes * po/pt_BR.po: Updated Brazilian Portuguese translation. gas * po/ru.po: Updated Russian translation.
2018-03-08x86-64: Also optimize "clr reg64"H.J. Lu3-2/+7
"clr reg" is an alias of "xor reg, reg". We can encode "clr reg64" as "xor reg32, reg32". gas/ * config/tc-i386.c (optimize_encoding): Also encode "clr reg64" as "xor reg32, reg32". * testsuite/gas/i386/x86-64-optimize-1.s: Add "clr reg64" tests. * testsuite/gas/i386/x86-64-optimize-1.d: Updated. opcodes/ * i386-opc.tbl: Add Optimize to clr. * i386-tbl.h: Regenerated.
2018-03-08x86: Remove support for old (<= 2.8.1) versions of gccH.J. Lu5-5237/+5098
Old (<= 2.8.1) versions of gcc generate broken fsubp, fsubrp, fdivp and fdivrp instructions. Assembler translates them to correct ones with a warning: [hjl@gnu-cfl-1 gas]$ cat x.s fsubp %st(3),%st [hjl@gnu-cfl-1 gas]$ gcc -c x.s x.s: Assembler messages: x.s:1: Warning: translating to `fsubp %st,%st(3)' [hjl@gnu-cfl-1 gas]$ This patch removes support for old (<= 2.8.1) versions of gcc: [hjl@gnu-cfl-1 gas]$ ./as-new -o x.o x.s x.s: Assembler messages: x.s:1: Error: operand type mismatch for `fsubp' [hjl@gnu-cfl-1 gas]$ gas/ * NEWS: Mention -mold-gcc removal. * config/tc-i386.c (i386_error): Remove old_gcc_only. (old_gcc): Removed. (match_template): Remove old gcc support. (OPTION_MOLD_GCC): Removed. (OPTION_MRELAX_RELOCATIONS): Updated. (md_longopts): Remove OPTION_MOLD_GCC. (md_parse_option): Likewise. (md_show_usage): Remove -mold-gcc. * testsuite/gas/i386/general.s: Convert fsub/fdiv tests for old (<= 2.8.1) versions of gcc. * testsuite/gas/i386/intel.s: Likewise. * testsuite/gas/i386/general.l: Updated. * testsuite/gas/i386/intel-intel.d: Likewise. * testsuite/gas/i386/intel.d: Likewise. * testsuite/gas/i386/intel.e: Likewise. * testsuite/gas/i386/i386.exp: Don't pass -mold-gcc to general. include/ * opcode/i386 (OLDGCC_COMPAT): Removed. opcodes/ * i386-gen.c (opcode_modifiers): Remove OldGcc. * i386-opc.h (OldGcc): Removed. (i386_opcode_modifier): Remove oldgcc. * i386-opc.tbl: Remove fsubp, fsubrp, fdivp and fdivrp instructions for old (<= 2.8.1) versions of gcc. * i386-tbl.h: Regenerated.
2018-03-08x86: fold several AVX512VL templatesJan Beulich4-2052/+357
The differences between some of the register and memory forms of the same insn often don't really require the templates to be separate. For example, Disp8MemShift is simply irrelevant to register forms. Fold these as far as possible, and also fold register-only forms. Further folding is possible, but needs other prereq work done first. A note regarding EVEXDYN: This is intended to be used only when no other properties of the template would make is_evex_encoding() return true. In all "normal" cases I think it is preferable to omit this indicator, to keep the table half way readable.
2018-03-08x86: fold certain AVX512 rotate and shift templatesJan Beulich3-954/+142
Their memory forms were bogusly using VexLWP instead of VexNDD. Adjust VexNDD handling to cope with these, allowing their register and memory forms to be folded.
2018-03-08x86: fold VEX-encoded GFNI templatesJan Beulich3-86/+21
2018-03-08x86: fold a few AVX512F templatesJan Beulich3-240/+31
The differences between some of the register and memory forms of the same insn often don't really require the templates to be separate. For example, Disp8MemShift is simply irrelevant to register forms. Fold them as far as possible. Further folding is possible, but needs other prereq work done first.
2018-03-08x86: fold LWP templatesJan Beulich3-86/+20
Also drop the no longer necessary explicit Disp<N> from them.
2018-03-08x86: fold FMA and FMA4 templatesJan Beulich3-1656/+330
2018-03-08x86: drop {X,Y,Z}MMWORD_MNEM_SUFFIXJan Beulich3-2/+7
They aren't really useful (anymore?): The conflicting operand size check isn't applicable to any insn validly using respective memory operand sizes (and if they're used wrongly, another error would result), and the logic in process_suffix() can be easily changed to work without them. While re-structuring conditionals in process_suffix() also drop the CMPXCHG8B special case in favor of a NoRex64 attribute in the opcode table.
2018-03-08x86: drop bogus NoAVXJan Beulich3-14/+20
These are meaningful only for insns with CpuSSE* (and a few other Cpu*) attribute.
2018-03-08x86: avoid SSE check for LDMXCSR/STMXCSRJan Beulich3-4/+9
Neither touches any XMM register, so the check is pointless. It is imo even questionable whether in SSE2AVX mode the two should be converted to their AVX counterparts.
2018-03-08x86: drop FloatDJan Beulich5-19738/+19743
It can be expressed by D, when making the consumer look at operand size to tell apart both uses.
2018-03-08x86/Intel: correct disassembly of fsub*/fdiv*Jan Beulich2-8/+12
fsub/fsubr/fsubp/fsubrp as well as fdiv/fdivr/fdivp/fdivrp disassembly should match (a) the Intel SDM and (b) respective input fed to gas (both of course with the exception of when we intentionally convert bogus insns, accompanied by a warning).
2018-03-08x86: bogus VMOVD with 64-bit operands should only allow for registersJan Beulich3-6/+11
These templates exist solely to satisfy gcc's needs, and gcc only produces these with register operands.
2018-03-08x86: fold AVX vcvtpd2ps memory formsJan Beulich3-20/+8
This requires a change to ModR/M handling: Recording of displacement types must not discard operand size information. Change the respective code to alter only .disp<N>.
2018-03-07XCOFF disassemblerAlan Modra4-20/+19
xcoff (32-bit) objdump accepted but ignored -M options unless -mpowerpc was also given. This patch fixes that, leaving the default as -Mpwr for xcoff. I've also enabled more tests for xcoff targets. binutils/ * configure.ac: Add objdump_private_desc_xcoff for rs6000. * configure: Regenerate. gas/ * testsuite/gas/ppc/aix.exp: Run for rs6000 too. * testsuite/gas/ppc/ppc.exp: Run more tests for non-ELF targets. * testsuite/gas/ppc/machine.d: Don't run for PE targets. opcodes/ * disassemble.c (disassembler): Use bfd_arch_powerpc entry for bfd_arch_rs6000. * disassemble.h (print_insn_rs6000): Delete. * ppc-dis.c (powerpc_init_dialect): Handle rs6000. (disassemble_init_powerpc): Call powerpc_init_dialect for rs6000. (print_insn_rs6000): Delete.
2018-03-03opcodes error messagesAlan Modra78-867/+1218
Another patch aimed at making binutils comply with the GNU coding standard. The generated files require https://sourceware.org/ml/cgen/2018-q1/msg00004.html cpu/ * frv.opc: Include opintl.h. (add_next_to_vliw): Use opcodes_error_handler to print error. Standardize error message. (fr500_check_insn_major_constraints, frv_vliw_add_insn): Likewise. opcodes/ * sysdep.h (opcodes_error_handler): Define. (_bfd_error_handler): Declare. * Makefile.am: Remove stray #. * opc2c.c (main): Remove bogus -l arg handling. Print "DO NOT EDIT" comment. * aarch64-dis.c, * arc-dis.c, * arm-dis.c, * avr-dis.c, * d30v-dis.c, * h8300-dis.c, * mmix-dis.c, * ppc-dis.c, * riscv-dis.c, * s390-dis.c, * sparc-dis.c, * v850-dis.c: Use opcodes_error_handler to print errors. Standardize error messages. * msp430-decode.opc, * nios2-dis.c, * rl78-decode.opc: Likewise, and include opintl.h. * nds32-asm.c: Likewise, and include sysdep.h and opintl.h. * i386-gen.c: Standardize error messages. * msp430-decode.c, * rl78-decode.c, rx-decode.c: Regenerate. * Makefile.in: Regenerate. * epiphany-asm.c, * epiphany-desc.c, * epiphany-dis.c, * epiphany-ibld.c, * fr30-asm.c, * fr30-desc.c, * fr30-dis.c, * fr30-ibld.c, * frv-asm.c, * frv-desc.c, * frv-dis.c, * frv-ibld.c, * frv-opc.c, * ip2k-asm.c, * ip2k-desc.c, * ip2k-dis.c, * ip2k-ibld.c, * iq2000-asm.c, * iq2000-desc.c, * iq2000-dis.c, * iq2000-ibld.c, * lm32-asm.c, * lm32-desc.c, * lm32-dis.c, * lm32-ibld.c, * m32c-asm.c, * m32c-desc.c, * m32c-dis.c, * m32c-ibld.c, * m32r-asm.c, * m32r-desc.c, * m32r-dis.c, * m32r-ibld.c, * mep-asm.c, * mep-desc.c, * mep-dis.c, * mep-ibld.c, * mt-asm.c, * mt-desc.c, * mt-dis.c, * mt-ibld.c, * or1k-asm.c, * or1k-desc.c, * or1k-dis.c, * or1k-ibld.c, * xc16x-asm.c, * xc16x-desc.c, * xc16x-dis.c, * xc16x-ibld.c, * xstormy16-asm.c, * xstormy16-desc.c, * xstormy16-dis.c, * xstormy16-ibld.c: Regenerate.
2018-03-01x86: Encode AVX256/AVX512 vpsub[bwdq] with VEX128/EVEX128H.J. Lu3-24/+30
When 2 source registers are identical, AVX256 and AVX512 vpsub[bwdq] instructions can be encoded with VEX128 or EVEX128 encodings. gas/ * config/tc-i386.c (optimize_encoding): Optimize AVX256 and AVX512 vpsub[bwdq] instructions. * testsuite/gas/i386/optimize-1.s: Add tests for AVX256 and AVX512 vpsub[bwdq] instructions. * testsuite/gas/i386/x86-64-optimize-2.s: Likewise. * testsuite/gas/i386/optimize-1.d: Updated. * testsuite/gas/i386/x86-64-optimize-2.d: Likewise. opcodes/ * * i386-opc.tbl: Add "Optimize" to AVX256 and AVX512 vpsub[bwdq] instructions. * i386-tbl.h: Regenerated.
2018-03-01Add missing translations to ALL_LINGUASAlan Modra3-2/+7
binutils/ * configure.ac (ALL_LINGUAS): Add sr. Sort. * configure: Regenerate. gas/ * configure.ac (ALL_LINGUAS): Add uk. Sort. * configure: Regenerate. gprof/ * configure.ac (ALL_LINGUAS): Add it, ro, ru, uk. Sort. * configure: Regenerate. ld/ * configure.ac (ALL_LINGUAS): Add ja. Sort. * configure: Regenerate. opcodes/ * configure.ac (ALL_LINGUAS): Sort. * configure: Regenerate.
2018-02-27[ARM] Remove ARM_FEATURE_COPY macroThomas Preud'homme2-2/+7
Among the macros to manipulate an arm_feature_set structure is the ARM_FEATURE_COPY which copy the value of a feature set into another. This can be achieved with a simple assignement which most of the existing code does. This patch removes the last 2 uses of that macro and remove the macro altogether. 2018-02-27 Thomas Preud'homme <thomas.preudhomme@arm.com> include/ * opcode/arm.h (ARM_FEATURE_COPY): Remove macro definition. 2018-02-27 Thomas Preud'homme <thomas.preudhomme@arm.com> opcodes/ * arm-dis.c (print_insn_coprocessor): Replace uses of ARM_FEATURE_COPY macro by assignements.
2018-02-27x86: Add -O[2|s] assembler command-line optionsH.J. Lu5-5354/+5388
On x86, some instructions have alternate shorter encodings: 1. When the upper 32 bits of destination registers of andq $imm31, %r64 testq $imm31, %r64 xorq %r64, %r64 subq %r64, %r64 known to be zero, we can encode them without the REX_W bit: andl $imm31, %r32 testl $imm31, %r32 xorl %r32, %r32 subl %r32, %r32 This optimization is enabled with -O, -O2 and -Os. 2. Since 0xb0 mov with 32-bit destination registers zero-extends 32-bit immediate to 64-bit destination register, we can use it to encode 64-bit mov with 32-bit immediates. This optimization is enabled with -O, -O2 and -Os. 3. Since the upper bits of destination registers of VEX128 and EVEX128 instructions are extended to zero, if all bits of destination registers of AVX256 or AVX512 instructions are zero, we can use VEX128 or EVEX128 encoding to encode AVX256 or AVX512 instructions. When 2 source registers are identical, AVX256 and AVX512 andn and xor instructions: VOP %reg, %reg, %dest_reg can be encoded with VOP128 %reg, %reg, %dest_reg This optimization is enabled with -O2 and -Os. 4. 16-bit, 32-bit and 64-bit register tests with immediate may be encoded as 8-bit register test with immediate. This optimization is enabled with -Os. This patch does: 1. Add {nooptimize} pseudo prefix to disable instruction size optimization. 2. Add optimize to i386_opcode_modifier to tell assembler that encoding of an instruction may be optimized. gas/ PR gas/22871 * NEWS: Mention -O[2|s]. * config/tc-i386.c (_i386_insn): Add no_optimize. (optimize): New. (optimize_for_space): Likewise. (fits_in_imm7): New function. (fits_in_imm31): Likewise. (optimize_encoding): Likewise. (md_assemble): Call optimize_encoding to optimize encoding. (parse_insn): Handle {nooptimize}. (md_shortopts): Append "O::". (md_parse_option): Handle -On. * doc/c-i386.texi: Document -O0, -O, -O1, -O2 and -Os as well as {nooptimize}. * testsuite/gas/cfi/cfi-x86_64.d: Pass -O0 to assembler. * testsuite/gas/i386/ilp32/cfi/cfi-x86_64.d: Likewise. * testsuite/gas/i386/i386.exp: Run optimize-1, optimize-2, optimize-3, x86-64-optimize-1, x86-64-optimize-2, x86-64-optimize-3 and x86-64-optimize-4. * testsuite/gas/i386/optimize-1.d: New file. * testsuite/gas/i386/optimize-1.s: Likewise. * testsuite/gas/i386/optimize-2.d: Likewise. * testsuite/gas/i386/optimize-2.s: Likewise. * testsuite/gas/i386/optimize-3.d: Likewise. * testsuite/gas/i386/optimize-3.s: Likewise. * testsuite/gas/i386/x86-64-optimize-1.s: Likewise. * testsuite/gas/i386/x86-64-optimize-1.d: Likewise. * testsuite/gas/i386/x86-64-optimize-2.d: Likewise. * testsuite/gas/i386/x86-64-optimize-2.s: Likewise. * testsuite/gas/i386/x86-64-optimize-3.d: Likewise. * testsuite/gas/i386/x86-64-optimize-3.s: Likewise. * testsuite/gas/i386/x86-64-optimize-4.d: Likewise. * testsuite/gas/i386/x86-64-optimize-4.s: Likewise. opcodes/ PR gas/22871 * i386-gen.c (opcode_modifiers): Add Optimize. * i386-opc.h (Optimize): New enum. (i386_opcode_modifier): Add optimize. * i386-opc.tbl: Add "Optimize" to "mov $imm, reg", "sub reg, reg/mem", "test $imm, acc", "test $imm, reg/mem", "and $imm, acc", "and $imm, reg/mem", "xor reg, reg/mem", "movq $imm, reg" and AVX256 and AVX512 versions of vandnps, vandnpd, vpandn, vpandnd, vpandnq, vxorps, vxorpd, vpxor, vpxord and vpxorq. * i386-tbl.h: Regenerated.
2018-02-26crx string overflow warningAlan Modra2-1/+6
gcc8 complains wrongly about the buffer not being large enough, at least at -Og optimization. * crx-dis.c (getregliststring): Allocate a large enough buffer to silence false positive gcc8 warning.
2018-02-22RISC-V: Make disassebler work for --enable-targets=all config.Jim Wilson2-0/+5
opcodes/ * disassemble.c (ARCH_riscv): Define if ARCH_all.
2018-02-22x86: Add {rex} pseudo prefixH.J. Lu3-0/+20
Add {rex} pseudo prefix to generate a REX byte for integer and legacy vector instructions if possible. Note that this differs from the rex prefix which generates REX prefix unconditionally. gas/ * config/tc-i386.c (_i386_insn): Add rex_encoding. (md_assemble): When i.rex_encoding is true, generate a REX byte if possible. (parse_insn): Set i.rex_encoding for {rex}. * doc/c-i386.texi: Document {rex}. * testsuite/gas/i386/x86-64-pseudos.s: Add {rex} tests. * testsuite/gas/i386/x86-64-pseudos.d: Updated. opcodes/ * i386-opc.tbl: Add {rex}, * i386-tbl.h: Regenerated.
2018-02-20MIPS16/opcodes: Free up `M' operand codeMaciej W. Rozycki2-2/+6
The `M' and `m' MIPS16 operand codes are functionally the same, denoting a 7-bit register list that is encoded the same way for both SAVE and RESTORE. Use `m' for both instructions then, making `M' available for a different use. opcodes/ * mips16-opc.c (decode_mips16_operand) <'M'>: Remove case. (mips16_opcodes): Replace `M' with `m' for "restore". include/ * opcode/mips.h: Remove `M' operand code.
2018-02-19[ARM] Fix bxns maskThomas Preud'homme2-1/+5
Bit 7 of BXNS is a fixed bit which distinguish it from BLXNS. Yet it is not set in the disassembler entry mask. This commit fixes that. 2018-02-19 Thomas Preud'homme <thomas.preudhomme@arm.com> opcodes/ * arm-dis.c (thumb_opcodes): Fix BXNS mask.
2018-02-13Fix compile time warning messages from gcc version 8 about cast between ↵Nick Clifton2-3/+13
incompatible function types. PR 22823 bfd Fix compile time warnings generated by gcc version 8. * libbfd-in.h: Remove extraneous text from prototypes. Add prototypes for bfd_false_any, bfd_true_any, bfd_nullvoidptr_any, bfd_0_any, bfd_0u_any, bfd_0l_any, bfd_n1_any, bfd_void_any. (_bfd_generic_bfd_copy_private_bfd_data): Use vararg based dummy function. (_bfd_generic_bfd_merge_private_bfd_data): Likewise. (_bfd_generic_bfd_set_private_flags): Likewise. (_bfd_generic_bfd_copy_private_section_data): Likewise. (_bfd_generic_bfd_copy_private_symbol_data): Likewise. (_bfd_generic_bfd_copy_private_header_data): Likewise. (_bfd_generic_bfd_print_private_bfd_data): Likewise. (_bfd_noarchive_construct_extended_name_table): Likewise. (_bfd_noarchive_truncate_arname): Likewise. (_bfd_noarchive_write_ar_hdr): Likewise. (_bfd_noarchive_get_elt_at_index): Likewise. (_bfd_nosymbols_canonicalize_symtab): Likewise. (_bfd_nosymbols_print_symbol): Likewise. (_bfd_nosymbols_get_symbol_info): Likewise. (_bfd_nosymbols_get_symbol_version_string): Likewise. (_bfd_nosymbols_bfd_is_local_label_name): Likewise. (_bfd_nosymbols_bfd_is_target_special_symbol): Likewise. (_bfd_nosymbols_get_lineno): Likewise. (_bfd_nosymbols_find_nearest_line): Likewise. (_bfd_nosymbols_find_line): Likewise. (_bfd_nosymbols_find_inliner_info): Likewise. (_bfd_nosymbols_bfd_make_debug_symbol): Likewise. (_bfd_nosymbols_read_minisymbols): Likewise. (_bfd_nosymbols_minisymbol_to_symbol): Likewise. (_bfd_norelocs_bfd_reloc_type_lookup): Likewise. (_bfd_norelocs_bfd_reloc_name_lookup): Likewise. (_bfd_nowrite_set_arch_mach): Likewise. (_bfd_nowrite_set_section_contents): Likewise. (_bfd_nolink_sizeof_headers): Likewise. (_bfd_nolink_bfd_get_relocated_section_contents): Likewise. (_bfd_nolink_bfd_relax_section): Likewise. (_bfd_nolink_bfd_gc_sections): Likewise. (_bfd_nolink_bfd_lookup_section_flags): Likewise. (_bfd_nolink_bfd_merge_sections): Likewise. (_bfd_nolink_bfd_is_group_section): Likewise. (_bfd_nolink_bfd_discard_group): Likewise. (_bfd_nolink_bfd_link_hash_table_create): Likewise. (_bfd_nolink_bfd_link_add_symbols): Likewise. (_bfd_nolink_bfd_link_just_syms): Likewise. (_bfd_nolink_bfd_copy_link_hash_symbol_type): Likewise. (_bfd_nolink_bfd_final_link): Likewise. (_bfd_nolink_bfd_link_split_section): Likewise. (_bfd_nolink_section_already_linked): Likewise. (_bfd_nolink_bfd_define_common_symbol): Likewise. (_bfd_nolink_bfd_define_start_stop): Likewise. (_bfd_nodynamic_canonicalize_dynamic_symtab): Likewise. (_bfd_nodynamic_get_synthetic_symtab): Likewise. (_bfd_nodynamic_get_dynamic_reloc_upper_bound _bfd_): Likewise. (_bfd_nodynamic_canonicalize_dynamic_reloc): Likewise. * libbfd.c (bfd_false_any): New function. Like bfd_false but accepts one or more arguments. (bfd_true_any): Likewise. (bfd_nullvoidptr_any): Likewise. (bfd_0_any): Likewise. (bfd_0u_any): Likewise. (bfd_0l_any): Likewise. (_bfd_n1_any): Likewise. (bfd_void_any): Likewise. * libbfd.h (extern): Regenerate * aout-target.h (MY_bfd_is_target_special_symbol): Use vararg based dummy function. * aout-tic30.c (tic30_aout_set_arch_mach): Likewise. * binary.c (binary_get_symbol_info): Likewise. * coff-alpha.c (alpha_ecoff_backend_data): Likewise. * coff-mips.c (mips_ecoff_backend_data): Likewise. * coffcode.h (coff_set_alignment_hook): Likewise. (symname_in_debug_hook): Likewise. (bfd_coff_backend_data bigobj_swap_table): Likewise. * elf-m10300.c (elf_backend_omit_section_dynsym): Likewise. * elf32-cr16.c (elf_backend_omit_section_dynsym): Likewise. * elf32-lm32.c (elf_backend_omit_section_dynsym): Likewise. * elf32-m32r.c (elf_backend_omit_section_dynsym): Likewise. * elf32-metag.c (elf_backend_omit_section_dynsym): Likewise. * elf32-score.c (elf_backend_omit_section_dynsym): Likewise. * elf32-score7.c (elf_backend_omit_section_dynsym): Likewise. * elf32-xstormy16.c (elf_backend_omit_section_dynsym): Likewise. * elf32-xtensa.c (elf_backend_omit_section_dynsym): Likewise. * elf64-alpha.c (elf_backend_omit_section_dynsym): Likewise. * elf64-hppa.c (elf_backend_omit_section_dynsym): Likewise. * elf64-ia64-vms.c (elf_backend_omit_section_dynsym): Likewise. * elf64-mmix.c (elf_backend_omit_section_dynsym): Likewise. * elf64-sh64.c (elf_backend_omit_section_dynsym): Likewise. * elfnn-ia64.c (elf_backend_omit_section_dynsym): Likewise. * elfxx-target.h (bfd_elfNN_bfd_debug_info_accumulate): Likewise. (bfd_elfNN_bfd_make_debug_symbol): Likewise. (bfd_elfNN_bfd_merge_private_bfd_data): Likewise. (bfd_elfNN_bfd_set_private_flags): Likewise. (bfd_elfNN_bfd_is_target_special_symbol): Likewise. (elf_backend_init_index_section): Likewise. (elf_backend_allow_non_load_phdr): Likewise. * elfxx-x86.h (elf_backend_omit_section_dynsym): Likewise. * i386msdos.c (msdos_bfd_is_target_special_symbol): Likewise. * ieee.c (ieee_construct_extended_name_table): Likewise. (ieee_write_armap): Likewise. (ieee_write_ar_hdr): Likewise. (ieee_bfd_is_target_special_symbol): Likewise. * ihex.c (ihex_canonicalize_symtab): Likewise. (ihex_bfd_is_target_special_symbol): Likewise. * libaout.h (aout_32_bfd_is_target_special_symbol): Likewise. * libecoff.h (_bfd_ecoff_bfd_is_target_special_symbol): Likewise. (_bfd_ecoff_set_alignment_hook): Likewise. * mach-o-target.c (bfd_mach_o_bfd_is_target_special_symbol): Likewise. * mmo.c (mmo_bfd_is_target_special_symbol): Likewise. * nlm-target.h (nlm_bfd_is_target_special_symbol): Likewise. * oasys.c (oasys_construct_extended_name_table): Likewise. (oasys_write_armap): Likewise. (oasys_write_ar_hdr): Likewise. (oasys_bfd_is_target_special_symbol): Likewise. * pef.c (bfd_pef_bfd_is_target_special_symbol): Likewise. * plugin.c (bfd_plugin_bfd_is_target_special_symbol): Likewise. * ppcboot.c (ppcboot_bfd_is_target_special_symbol): Likewise. * som.c (som_bfd_is_target_special_symbol): Likewise. * srec.c (srec_bfd_is_target_special_symbol): Likewise. * tekhex.c (tekhex_bfd_is_target_special_symbol): Likewise. * verilog.c (verilog_bfd_is_target_special_symbol): Likewise. * versados.c (versados_bfd_is_target_special_symbol): Likewise. (versados_bfd_reloc_name_lookup): Likewise. * vms-alpha.c (vms_bfd_is_target_special_symbol): Likewise. (vms_bfd_define_start_stop): Likewise. (alpha_vms_bfd_is_target_special_symbol): Likewise. * wasm-module.c (wasm_bfd_is_target_special_symbol): Likewise. * xsym.c (bfd_sym_bfd_is_target_special_symbol): Likewise. * elf32-arc.c (get_replace_function): Assign replacement function to func pointer. * elf32-i370.c (i370_noop): Update prototype. gas * config/obj-elf.c (elf_pseudo_table): Remove now redundant casts. (obj_elf_vtable_inherit): Rename to obj_elf_get_vtable_inherit. (obj_elf_vtable_inherit): New stub function that calls obj_elf_get_vtable_inherit. (obj_elf_vtable_entry): Rename to obj_elf_get_vtable_entry. (obj_elf_vtable_entry): New stub function that calls obj_elf_get_vtable_entry. * config/obj-elf.h (obj_elf_vtable_inherit): Update prototype. (obj_elf_vtable_entry) Likewise. (obj_elf_get_vtable_inherit) Likewise. (obj_elf_get_vtable_entry) Likewise. * config/tc-arm.c (md_pseudo_table): Remove now redundant cast. * config/tc-i386c (md_pseudo_table): Likewise. * config/tc-hppa.c (pa_vtable_entry): Call obj_elf_get_vtable_entry. (pa_vtable_inherit): Call obj_elf_get_vtable_inherit. * config/tc-mips.c (s_mips_file): Replace call to dwarf2_get_file with call to dwarf2_get_filename. * dwarf2dbg.c (dwarf2_directive_file): Rename to dwarf2_directive_filename. (dwarf2_directive_file): New stub function that calls dwarf2_directive_filename. * dwarf2dbg.h: Prototype dwarf2_directive_filename. opcodes * metag-dis.c (print_fmmov): Double buffer size to avoid warning about truncation of printing.
2018-02-13WebAssembly: Correct an `index' global shadowing error for pre-4.8 GCCMaciej W. Rozycki2-3/+8
Remove `-Wshadow' compilation errors: cc1: warnings being treated as errors .../bfd/wasm-module.c: In function 'wasm_scan_name_function_section': .../bfd/wasm-module.c:312: error: declaration of 'index' shadows a global declaration /usr/include/string.h:303: error: shadowed declaration is here .../bfd/wasm-module.c: In function 'wasm_register_section': .../bfd/wasm-module.c:494: error: declaration of 'index' shadows a global declaration /usr/include/string.h:303: error: shadowed declaration is here .../bfd/wasm-module.c: In function 'wasm_compute_custom_section_file_position': .../bfd/wasm-module.c:523: error: declaration of 'index' shadows a global declaration /usr/include/string.h:303: error: shadowed declaration is here and: cc1: warnings being treated as errors .../opcodes/wasm32-dis.c: In function 'print_insn_wasm32': .../opcodes/wasm32-dis.c:272: error: declaration of 'index' shadows a global declaration /usr/include/string.h:303: error: shadowed declaration is here make[4]: *** [wasm32-dis.lo] Error 1 which for versions of GCC before 4.8 prevent support for the WebAssembly target from being built. See also GCC PR c/53066. bfd/ * wasm-module.c (wasm_scan_name_function_section): Rename `index' local variable to `idx'. opcodes/ * wasm32-dis.c (print_insn_wasm32): Rename `index' local variable to `function_index'.
2018-02-12MIPS: Fix encoding for MIPSr6 sigrie instruction.Henry Wong2-1/+5
The instruction encoding for the MIPS r6 sigrie instruction seems to be incorrect. It's currently 0x4170xxxx (which overlaps with ei, di, evp, and dvp), but should be 0x0417xxxx. See ISA reference[1][2]. References: [1] "MIPS Architecture for Programmers Volume II-A: The MIPS32 Instruction Set Manual", Imagination Technologies, Inc., Document Number: MD00086, Revision 6.06, December 15, 2016, Table A.4 "MIPS32 REGIMM Encoding of rt Field", p. 452 [2] "MIPS Architecture For Programmers Volume II-A: The MIPS64 Instruction Set Reference Manual", Imagination Technologies, Inc., Document Number: MD00087, Revision 6.06, December 15, 2016, Table A.4 "MIPS64 REGIMM Encoding of rt Field", p. 581 opcodes/ * mips-opc.c (mips_builtin_opcodes): Correct "sigrie" encoding. gas/ * testsuite/gas/mips/r6.d: Update for "sigrie" encoding fix. * testsuite/gas/mips/r6-n32.d: Likewise. * testsuite/gas/mips/r6-n64.d: Likewise.
2018-02-05Updated Brazillian portuguese and Russian translationNick Clifton2-2/+6
2018-01-23Enable Intel PCONFIG instruction.Igor Tsimbalist7-5483/+5529
Intel has disclosed a set of new instructions for Icelake processor. The spec is https://software.intel.com/sites/default/files/managed/c5/15/architecture-instruction-set-extensions-programming-reference.pdf This patch enables Intel PCONFIG instruction. gas/ * config/tc-i386.c (cpu_arch): Add .pconfig. * doc/c-i386.texi: Document .pconfig. * testsuite/gas/i386/i386.exp: Add PCONFIG tests. * testsuite/gas/i386/pconfig-intel.d: New test. * testsuite/gas/i386/pconfig.d: Likewise. * testsuite/gas/i386/pconfig.s: Likewise. * testsuite/gas/i386/x86-64-pconfig-intel.d: Likewise. * testsuite/gas/i386/x86-64-pconfig.d: Likewise. * testsuite/gas/i386/x86-64-pconfig.s: Likewise. opcodes/ * i386-dis.c (enum): Add pconfig. * i386-gen.c (cpu_flag_init): Add CPU_PCONFIG_FLAGS. (cpu_flags): Add CpuPCONFIG. * i386-opc.h (enum): Add CpuPCONFIG. (i386_cpu_flags): Add cpupconfig. * i386-opc.tbl: Add PCONFIG instruction. * i386-init.h: Regenerate. * i386-tbl.h: Likewise.
2018-01-23Enable Intel WBNOINVD instruction.Igor Tsimbalist7-5483/+5535
Intel has disclosed a set of new instructions for Icelake processor. The spec is https://software.intel.com/sites/default/files/managed/c5/15/architecture-instruction-set-extensions-programming-reference.pdf This patch enables Intel WBNOINVD instruction. gas/ * config/tc-i386.c (cpu_arch): Add .wbnoinvd. * doc/c-i386.texi: Document .wbnoinvd. * testsuite/gas/i386/i386.exp: Add WBNOINVD tests. * testsuite/gas/i386/wbnoinvd-intel.d: New test. * testsuite/gas/i386/wbnoinvd.d: Likewise. * testsuite/gas/i386/wbnoinvd.s: Likewise. * testsuite/gas/i386/x86-64-wbnoinvd-intel.d: Likewise. * testsuite/gas/i386/x86-64-wbnoinvd.d: Likewise. * testsuite/gas/i386/x86-64-wbnoinvd.s: Likewise. opcodes/ * i386-dis.c (enum): Add PREFIX_0F09. * i386-gen.c (cpu_flag_init): Add CPU_WBNOINVD_FLAGS. (cpu_flags): Add CpuWBNOINVD. * i386-opc.h (enum): Add CpuWBNOINVD. (i386_cpu_flags): Add cpuwbnoinvd. * i386-opc.tbl: Add WBNOINVD instruction. * i386-init.h: Regenerate. * i386-tbl.h: Likewise.
2018-01-17RISC-V: Fix bug in prior addi/c.nop patch.Jim Wilson2-1/+5
gas/ * config/tc-riscv.c (validate_riscv_insn) <'z'>: New. (riscv_ip) <'z'>: New. opcodes/ * riscv-opc.c (riscv_opcodes) <addi>: Use z instead of 0.
2018-01-17Replace CET bit with IBT and SHSTK bits.Igor Tsimbalist6-5557/+5602
The latest specification for Intel CET technology defined two new bits instead of previously used CET bit. These are IBT and SHSTK bits. The patch replaces CET bit with IBT and SHSTK bits. gas/ * config/tc-i386.c (cpu_arch): Delete .cet. Add .ibt, .shstk. (cpu_noarch): Add noibt, noshstk. (parse_insn): Change cpucet to cpuibt. * doc/c-i386.texi: Delete .cet. Add .ibt, .shstk. * testsuite/gas/i386/cet-ibt-inval.l: New test. * testsuite/gas/i386/cet-ibt-inval.s: Likewise. * testsuite/gas/i386/cet-shstk-inval.l: Likewise. * testsuite/gas/i386/cet-shstk-inval.s: Likewise. * testsuite/gas/i386/x86-64-cet-ibt-inval.l: Likewise. * testsuite/gas/i386/x86-64-cet-ibt-inval.s: Likewise. * testsuite/gas/i386/x86-64-cet-shstk-inval.l: Likewise. * testsuite/gas/i386/x86-64-cet-shstk-inval.s: Likewise. opcodes/ * i386-gen.c (cpu_flag_init): Delete CPU_CET_FLAGS, CpuCET. Add CPU_IBT_FLAGS, CPU_SHSTK_FLAGS, CPY_ANY_IBT_FLAGS, CPU_ANY_SHSTK_FLAGS, CpuIBT, CpuSHSTK. (cpu_flags): Add CpuIBT, CpuSHSTK. * i386-opc.h (enum): Add CpuIBT, CpuSHSTK. (i386_cpu_flags): Add cpuibt, cpushstk. * i386-opc.tbl: Change CpuCET to CpuSHSTK and CpuIBT. * i386-init.h: Regenerate. * i386-tbl.h: Likewise.
2018-01-16Update translations for various binutils components.Nick Clifton3-596/+2117
ld * po/pt_BR.po: Updated Brazilian Portugese translation. opcodes * po/pt_BR.po: Updated Brazilian Portugese translation. * po/de.po: Updated German translation. gas * po/fr.po: Updated French translation. binutils* po/fr.po: Updated French translation.
2018-01-15RISC-V: Add support for addi that compresses to c.nop.Jim Wilson2-0/+13
gas/ * testsuite/gas/riscv/c-zero-imm.s: Test addi that compresses to c.nop. * testsuite/gas/riscv/c-zero-imm.d: Likewise. opcodes/ * riscv-opc.c (match_c_nop): New. (riscv_opcodes) <addi>: Handle an addi that compresses to c.nop.
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