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2005-11-15 * ppc-opc.c (powerpc_opcodes): Add frin,friz,frip,frim. CorrectAlan Modra2-2/+16
frsqrtes.
2005-11-14 * mips.h: Assign 'm'/'M' codes to MIPS16e save/restoreThiemo Seufer3-0/+94
instructions. Define MIPS16_ALL_ARGS and MIPS16_ALL_STATICS for save/restore encoding of the args field. * mips16-opc.c: Add MIPS16e save/restore opcodes. * mips-dis.c (print_mips16_insn_arg): Handle printing of 'm'/'M' codes for save/restore. * config/tc-mips.c (mips16_ip): Add handling of 'm' and 'M' codes for the MIPS16e save/restore instructions. * gas/mips/mips.exp: Run new save/restore tests. * gas/testsuite/gas/mips/mips16e-save.s: New test for generating different styles of save/restore instructions. * gas/testsuite/gas/mips/mips16e-save.d: New.
2005-11-10 * m68k-dis.c (print_insn_m68k): Only match FPU insns withAndreas Schwab2-0/+19
coprocessor ID 1.
2005-11-08* m32c-desc.c: Regenerated.Nick Clifton2-5/+9
2005-11-08bfd:Nathan Sidwell8-46/+410
Add ms2. * archures.c (bfd_mach_ms2): Define. * cpu-ms1.c (arch_info_struct): Add ms2 stanza. * elf32-ms1.c (elf32_ms1_machine): Add ms2 case. (ms1_elf_merge_private_bfd_data): Remove unused variables. Add correct merging logic, with workaround. (ms1_elf_print_private_bfd_data): Add ms2 case. * reloc.c (BFD_RELOC_MS1_PCINSN8): Add ms2 specific reloc. * libbfd.h: Regenerated. * bfd-in2.h: Regenerated. cpu: Add ms2 * ms1.cpu (ms2, ms2bf): New architecture variant, cpu, machine and model. (f-uu8, f-uu1, f-imm16l, f-loopo, f-cb1sel, f-cb2sel, f-cb1incr, f-cb2incr, f-rc3): New fields. (LOOP): New instruction. (JAL-HAZARD): New hazard. (imm16o, loopsize, imm16l, rc3, cb1sel, cb2sel, cb1incr, cb2incr): New operands. (mul, muli, dbnz, iflush): Enable for ms2 (jal, reti): Has JAL-HAZARD. (ldctxt, ldfb, stfb): Only ms1. (fbcb): Only ms1,ms1-003. (wfbinc, mefbinc, wfbincr, mwfbincr, fbcbincs, mfbcbincs, fbcbincrs, mfbcbincrs): Enable for ms2. (loop, loopu, dfbc, dwfb, fbwfb, dfbr): New ms2 insns. * ms1.opc (parse_loopsize): New. (parse_imm16): hi16/lo16 relocs are applicable to IMM16L. (print_pcrel): New. gas: Add ms2. * config/tc-ms1.c (ms1_mach_bitmask): Initialize to MS1. (ms1_architectures): Add ms2. (md_parse_option): Add ms2. (md_show_usage): Add ms2. (md_assemble): Add JAL_HAZARD detection logic. (md_cgen_lookup_reloc): Add MS1_OPERAND_LOOPSIZE case. * doc/c-ms1.texi: New. * doc/all.texi: Add MS1. * doc/Makefile.am (CPU_DOCS): Add c-ms1.texi. * doc/Makefile.in: Rebuilt. * doc/Makefile: Rebuilt. gas/testsuite: Add ms2. * gas/ms1/allinsn.d: Adjust pcrel disassembly. * gas/ms1/errors.exp: Fix target triplet. * gas/ms1/ms1-16-003.d: Adjust pcrel disassembly. * gas/ms1/ms1-16-003.s: Tweak label. * gas/ms1/ms1.exp: Adjust target triplet. Add ms2 test. * gas/ms1/ms2.d, gas/ms1/ms2.s: New. * gas/ms1/relocs.d: Adjust expected machine name and pcrel disassembly. * gas/ms1/relocs.exp: Adjust target triplet. include: Add ms2. * elf/ms1.h (EF_MS1_CPU_MS2): New. opcodes: Add ms2. * ms1-asm.c, ms1-desc.c, ms1-desc.h, ms1-dis.c, ms1-ibld.c, ms1-opc.c, ms1-opc.h: Regenerated.
2005-11-07 * configure: Regenerate after modifying bfd/warning.m4.Steve Ellcey2-6/+16
2005-11-07 * i386-dis.c (ckprefix): Handle rex on fwait. Don't printAlan Modra2-14/+22
ignored rex prefixes here. (print_insn): Instead, handle them similarly to fwait followed by non-fp insns.
2005-11-022005-11-02 H.J. Lu <hongjiu.lu@intel.com>H.J. Lu5-530/+594
* iq2000-desc.c: Regenerated. * iq2000-desc.h: Likewise. * iq2000-dis.c: Likewise. * iq2000-opc.c: Likewise.
2005-11-022005-11-02 Paul Brook <paul@codesourcery.com>Paul Brook2-1/+10
* arm-dis.c (print_insn_thumb32): Word align blx target address.
2005-10-31 * arm-dis.c (print_insn): Warning fix.Alan Modra2-5/+9
2005-10-30ld/H.J. Lu4-416/+534
binutils/ opcodes/ 2005-10-30 H.J. Lu <hongjiu.lu@intel.com> * Makefile.am: Run "make dep-am". * Makefile.in: Regenerated. * dep-in.sed: Replace " ./" with " ".
2005-10-282005-10-28 Dave Brolley <brolley@redhat.com>Dave Brolley37-16720/+17361
* All CGEN-generated sources: Regenerate. Contribute the following changes: 2005-09-19 Dave Brolley <brolley@redhat.com> * disassemble.c (disassemble_init_for_target): Add 'break' to case for bfd_arch_tic4x. Use cgen_bitset_create and cgen_bitset_set for bfd_arch_m32c case. 2005-02-16 Dave Brolley <brolley@redhat.com> * cgen-dis.in: Rename CGEN_ISA_MASK to CGEN_BITSET. Rename cgen_isa_mask_* to cgen_bitset_*. * cgen-opc.c: Likewise. 2003-11-28 Richard Sandiford <rsandifo@redhat.com> * cgen-dis.in (print_insn_@arch@): Fix comparison with cached isas. * *-dis.c: Regenerate. 2003-06-05 DJ Delorie <dj@redhat.com> * cgen-dis.in (print_insn_@arch@): Copy prev_isas, don't assign it, as it may point to a reused buffer. Set prev_isas when we change cpus. 2002-12-13 Dave Brolley <brolley@redhat.com> * cgen-opc.c (cgen_isa_mask_create): New support function for CGEN_ISA_MASK. (cgen_isa_mask_init): Ditto. (cgen_isa_mask_clear): Ditto. (cgen_isa_mask_add): Ditto. (cgen_isa_mask_set): Ditto. (cgen_isa_supported): Ditto. (cgen_isa_mask_compare): Ditto. (cgen_isa_mask_intersection): Ditto. (cgen_isa_mask_copy): Ditto. (cgen_isa_mask_combine): Ditto. * cgen-dis.in (libiberty.h): #include it. (isas): Renamed from 'isa' and now (CGEN_ISA_MASK *). (print_insn_@arch@): Use CGEN_ISA_MASK and support functions. * Makefile.am (CGENDEPS): Add utils-cgen.scm and attrs.scm. * Makefile.in: Regenerated.
2005-10-27* m32c.cpu (Imm-8-s4n, Imm-12-s4n): New.DJ Delorie8-2756/+3093
(arith-jnz16-imm4-dst-defn, arith-jnz32-imm4-dst-defn, arith-jnz-imm4-dst-mach, arith-jnz-imm4-dst): Keep track of which imm operand is needed. (adjnz, sbjnz): Pass the right operands. (unary-insn-defn, unary16-defn, unary32-defn, unary-insn-mach, unary-insn): Add -g variants for opcodes that need to support :G. (not.BW:G, push.BW:G): Call it. (stzx16-imm8-imm8-dsp8sb, stzx16-imm8-imm8-dsp8fb, stzx16-imm8-imm8-abs16): Fix operand typos. * m32c.opc (m32c_asm_hash): Support bnCND. (parse_signed4n, print_signed4n): New. * m32c-asm.c: Regenerate. * m32c-desc.c: Regenerate. * m32c-desc.h: Regenerate. * m32c-dis.c: Regenerate. * m32c-ibld.c: Regenerate. * m32c-opc.c: Regenerate. * m32c-opc.h: Regenerate.
2005-10-26* m32c.cpu (f-dsp-8-s24, Dsp-8-s24): New.DJ Delorie8-1511/+1580
(mov-dspsp-dst-defn, mov-src-dspsp-defn, mov16-dspsp-dst-defn, mov16-src-dspsp-defn, mov32-dspsp-dst-defn, mov32-src-dspsp-defn): dsp8[sp] is signed. (mov.WL:S #imm,A0/A1): dsp24 is signed (i.e. -0x800000..0xffffff). (mov.BW:S r0,r1): Fix typo r1l->r1. (tst): Allow :G suffix. * m32c.opc (parse_signed24): New, for -0x800000..0xffffff. * m32c-asm.c: Regenerate. * m32c-desc.c: Regenerate. * m32c-desc.h: Regenerate. * m32c-dis.c: Regenerate. * m32c-ibld.c: Regenerate. * m32c-opc.c: Regenerate. * m32c-opc.h: Regenerate.
2005-10-262005-10-26 Paul Brook <paul@codesourcery.com>Paul Brook2-1/+5
gas/ * config/tc-arm.c (insns): Correct "sel" entry. gas/testsuite/ * gas/arm/archv6.d: Adjust expected output. opcodes/ * arm-dis.c (arm_opcodes): Correct "sel" entry.
2005-10-26 * m32r.opc (parse_hi16): Do not assume a 32-bit host word size.Alan Modra2-2/+10
2005-10-25* m32c.cpu (add16-bQ-sp,add16-wQ-sp): Fix to allow either width byDJ Delorie8-257/+235
making one a macro of the other. * m32c-asm.c: Regenerate. * m32c-desc.c: Regenerate. * m32c-desc.h: Regenerate. * m32c-dis.c: Regenerate. * m32c-ibld.c: Regenerate. * m32c-opc.c: Regenerate. * m32c-opc.h: Regenerate.
2005-10-25Add support for the Z80 processor familyNick Clifton7-0/+644
2005-10-25RegenerateAlan Modra3-53/+82
2005-10-24include/opcode/Jan Beulich2-82/+86
2005-10-24 Jan Beulich <jbeulich@novell.com> * ia64.h (enum ia64_opnd): Move memory operand out of set of indirect operands. bfd/ 2005-10-24 Jan Beulich <jbeulich@novell.com> * cpu-ia64-opc.c (elf64_ia64_operands): Move memory operand out of set of indirect operands. gas/ 2005-10-24 Jan Beulich <jbeulich@novell.com> * config/tc-ia64.c (enum reg_symbol): Delete IND_MEM. (dot_rot): Change type of num_* variables. Check for positive count. (ia64_optimize_expr): Re-structure. (md_operand): Check for general register. gas/testsuite/ 2005-10-24 Jan Beulich <jbeulich@novell.com> * gas/ia64/index.[sl]: New. * gas/ia64/rotX.[sl]: New. * gas/ia64/ia64.exp: Run new tests. opcodes/ 2005-10-24 Jan Beulich <jbeulich@novell.com> * ia64-asmtab.c: Regenerate.
2005-10-22[cpu]DJ Delorie8-625/+1492
* m32c.cpu (lde, ste): Add dsp[a0] and [a1a] addressing. (indexb, indexbd, indexbs, indexw, indexwd, indexws, indexl, indexld, indexls): .w variants have `1' bit. (rot32.b): QI, not SI. (rot32.w): HI, not SI. (xchg16): HI for .w variant. [opcodes] * m32c-asm.c: Regenerate. * m32c-desc.c: Regenerate. * m32c-desc.h: Regenerate. * m32c-dis.c: Regenerate. * m32c-ibld.c: Regenerate. * m32c-opc.c: Regenerate. * m32c-opc.h: Regenerate.
2005-10-21bfin-dis.c: Tidy up code, removing redundant constructs.Nick Clifton2-1763/+501
2005-10-19 * s390-opc.txt: Add unnormalized hfp multiply and multiply-and-addMartin Schwidefsky2-0/+18
instructions.
2005-10-19* m32r.opc (parse_slo16): Fix bad application of previous patch.Nick Clifton2-5/+5
2005-10-18 * bfin-dis.c (print_insn_bfin): Do proper endian transform whenJie Zhang2-3/+13
reading instruction from memory.
2005-10-18m32r.opc (parse_slo16): Better version of previous patch.Nick Clifton2-2/+6
2005-10-14m32r.opc (parse_slo16): Do not assume a 32-bit host word size.Nick Clifton2-1/+5
2005-10-082005-10-08 James Lemke <jim@wasabisystems.com>Richard Earnshaw2-6/+11
* arm-dis.c (coprocessor_opcodes): Fix mask for various Maverick CDP operations.
2005-10-06bfd/Daniel Jacobowitz2-8/+9
* elf32-arm.c (elf32_arm_check_relocs): Avoid aliasing warnings from GCC. (elf32_arm_size_dynamic_sections): Likewise. * ecofflink.c (bfd_ecoff_debug_one_external): Likewise. * elf32-hppa.c (elf32_hppa_check_relocs): Likewise. * elf32-m32r.c (m32r_elf_check_relocs): Likewise. * elf32-m68k.c (elf_m68k_check_relocs): Likewise. * elf32-ppc.c (ppc_elf_check_relocs): Likewise. * elf32-s390.c (elf_s390_check_relocs): Likewise. (elf_s390_size_dynamic_sections): Likewise. * elf32-sh.c (sh_elf_check_relocs): Likewise. * elf64-ppc.c (ppc64_elf_check_relocs, dec_dynrel_count) (ppc64_elf_size_dynamic_sections): Likewise. * elf64-s390.c (elf_s390_check_relocs): Likewise. (elf_s390_size_dynamic_sections): Likewise. * elfxx-mips.c (_bfd_mips_elf_finish_dynamic_sections): Likewise. * elfxx-sparc.c (_bfd_sparc_elf_check_relocs): Likewise. (_bfd_sparc_elf_size_dynamic_sections): Likewise. * ieee.c (ieee_slurp_section_data): Likewise. * oasys.c (oasys_slurp_section_data): Likewise. opcodes/ * ppc-dis.c (struct dis_private): Remove. (powerpc_dialect): Avoid aliasing warnings. (print_insn_big_powerpc, print_insn_little_powerpc): Likewise.
2005-10-03oops - delayed commit for addtion of Irish translation for gprof and opcodesNick Clifton4-2/+819
2005-09-302005-09-30 H.J. Lu <hongjiu.lu@intel.com>H.J. Lu4-890/+871
* Makefile.am: Run "make dep-am". * Makefile.in: Regenerated. * aclocal.m4: Likewise. * configure: Likewise.
2005-09-30 * Makefile.am: Bfin support.Catherine Moore8-138/+6139
* Makefile.in: Regenerated. * aclocal.m4: Regenerated. * bfin-dis.c: New file. * configure.in: Bfin support. * configure: Regenerated. * disassemble.c (ARCH_bfin): Define. (disassembler): Add case for bfd_arch_bfin.
2005-09-28gas/testsuite/Jan Beulich2-46/+74
2005-09-28 Jan Beulich <jbeulich@novell.com> * gas/i386/x86-64-stack.s, gas/i386/x86-64-stack.d, gas/i386/x86-64-stack-suffix.d, gas/i386/x86-64-stack-intel.d: New. * gas/i386/i386.exp: Run new tests. ld/testsuite/ 2005-09-28 Jan Beulich <jbeulich@novell.com> * ld-x86-64/tlspic.dd: Adjust. opcodes/ 2005-09-28 Jan Beulich <jbeulich@novell.com> * i386-dis.c (stack_v_mode): Renamed from branch_v_mode. (indirEv): Use it. (stackEv): New. (Ob64, Ov64): Rename to Ob, Ov. Delete unused original definitions. (dis386): Document and use new 'V' meta character. Use it for single-byte push/pop opcode forms. Use stackEv for mod-r/m push/pop opcode forms. Correct typo in 'pop ss'. Replace Ob64/Ov64 by Ob/Ov. (putop): 'q' suffix for 'T' and 'U' meta depends on DFLAG. Mark data prefix as used whenever DFLAG was examined. Handle 'V'. (intel_operand_size): Use stack_v_mode. (OP_E): Use stack_v_mode, but handle only the special case of 64-bit mode without operand size override here; fall through to v_mode case otherwise. (OP_REG): Special case rAX_reg ... rDI_reg only when 64-bit mode and no operand size override is present. (OP_J): Use get32s for obtaining the displacement also when rex64 is present.
2005-09-082005-09-08 Paul Brook <paul@codesourcery.com>Paul Brook2-2/+6
bfd/ * reloc.c: Rename BFD_RELOC_ARM_SMI to BFD_RELOC_ARM_SMC. * bfd-in2.h: Regenerate. * libbfd.h: Regenerate. opcodes/ * arm-dis.c (arm_opcodes, thumb32_opcodes): Rename smi to smc. gas/ * config/tc-arm.c (do_smi, do_t_smi): Rename ... (do_smc, do_t_smc): ... to this. (insns): Remane smi to smc. (md_apply_fix, tc_gen_reloc): Rename BFD_RELOC_ARM_SMI to BFD_RELOC_ARM_SMC. gas/testsuite/ * gas/arm/arch6zk.d: Rename smi to smc. * gas/arm/arch6zk.s: Ditto. * gas/arm/thumb32.d: Ditto. * gas/arm/thumb32.s: Ditto.
2005-09-06* mips-opc.c (MT32): New define.Chao-ying Fu3-5/+127
(mips_builtin_opcodes): Move "bc0f", "bc0fl", "bc0t", "bc0tl" to the bottom to avoid opcode collision with "mftr" and "mttr". Add MT instructions. * mips-dis.c (mips_arch_choices): Enable INSN_MT for mips32r2. (print_insn_args): Add supports for +t, +T, !, $, *, &, g operand formats.
2005-09-022005-09-02 Paul Brook <paul@codesourcery.com>Paul Brook2-1/+5
* arm-dis.c (coprocessor_opcodes): Add null terminator.
2005-09-022005-09-02 Paul Brook <paul@codesourcery.com>Paul Brook2-539/+743
bfd/ * libbdf.h: Regenerate. * bfd-in2.h: Regenerate. * reloc.c: Add BFD_RELOC_ARM_T32_CP_OFF_IMM and BFD_RELOC_ARM_T32_CP_OFF_IMM_S2. gas/ * config/tc-arm.c (encode_arm_cp_address): Use BFD_RELOC_ARM_T32_CP_OFF_IMM in thumb mode. (do_iwmmxt_wldstbh): Use BFD_RELOC_ARM_T32_CP_OFF_IMM_S2 in thumb mode. (md_assemble): Only allow coprocessor instructions when Thumb-2 is available. (cCE, cC3): Define. (insns): Use them for coprocessor instructions. (md_pcrel_from_section): Handle BFD_RELOC_ARM_T32_CP_OFF_IMM. (get_thumb32_insn): New function. (put_thumb32_insn): New function. (md_apply_fix): Handle BFD_RELOC_ARM_T32_CP_OFF_IMM and BFD_RELOC_ARM_T32_CP_OFF_IMM_S2. gas/testsuite/ * gas/arm/vfp-bad_t2.d, gas/arm/vfp-bad_t2.l, arm/vfp-bad_t2.s, gas/arm/vfp1_t2.d, gas/arm/vfp1_t2.s, gas/arm/vfp1xD_t2.d, gas/arm/vfp1xD_t2.s, gas/arm/vfp2_t2.d, gas/arm/vfp2_t2.s): New files. opcodes/ * arm-dis.c (coprocessor_opcodes): New. (arm_opcodes, thumb32_opcodes): Remove coprocessor insns. (print_insn_coprocessor): New function. (print_insn_arm): Use print_insn_coprocessor. Remove coprocessor format characters. (print_insn_thumb32): Use print_insn_coprocessor.
2005-08-302005-08-30 Paul Brook <paul@codesourcery.com>Paul Brook2-2/+6
opcodes/ * arm-dis.c (thumb_opcodes): Disassemble sub(3) as subs. gas/testsuite/ * gas/arm/thumb.d: Change "sub rn, rn, rn" to "subs rn, rn, rn". * gas/arm/thumb32.d: Ditto.
2005-08-26opcodes/Jan Beulich2-89/+89
2005-08-26 Jan Beulich <jbeulich@novell.com> * i386-dis.c (intel_operand_size): New, broken out from OP_E for re-use. (OP_E): Call intel_operand_size, move call site out of mode dependent code. (OP_OFF): Call intel_operand_size if suffix_always. Remove ATTRIBUTE_UNUSED from parameters. (OP_OFF64): Likewise. (OP_ESreg): Call intel_operand_size. (OP_DSreg): Likewise. (OP_DIR): Use colon rather than semicolon as separator of far jump/call operands. gas/testsuite/ 2005-08-26 Jan Beulich <jbeulich@novell.com> * gas/i386/intelok.d: Adjust.
2005-08-25* mips-opc.c (WR_a, RD_a, MOD_a, DSP_VOLA, D32): New define.Chao-ying Fu3-4/+211
(mips_builtin_opcodes): Add DSP instructions. * mips-dis.c (mips_arch_choices): Enable INSN_DSP for mips32, mips32r2, mips64, mips64r2. (print_insn_args): Add supports for 3, 4, 5, 6, 7, 8, 9, 0, :, ', @ operand formats.
2005-08-23* mips16-opc.c (mips16_opcodes): Add the MIPS16e jalrc/jrcDavid Ung2-0/+9
instructions to the table.
2005-08-18Remove a29k files.Alan Modra2-358/+1
2005-08-18Remove a29k support.Alan Modra7-22/+9
2005-08-15gas/Daniel Jacobowitz3-1/+13
* config/tc-ppc.c (parse_cpu): Add -me300 support. (md_show_usage): Likewise. * doc/c-ppc.texi (PowerPC-Opts): Document it. include/opcode/ * ppc.h (PPC_OPCODE_E300): Define. opcodes/ * ppc-dis.c (powerpc_dialect): Handle e300. (print_ppc_disassembler_options): Likewise. * ppc-opc.c (PPCE300): Define. (powerpc_opcodes): Mark icbt as available for the e300. binutils/ * doc/binutils.texi (objdump): Document -M e300.
2005-08-14 * hppa-dis.c (print_insn_hppa): Don't print '%' before register names.Dave Anglin2-4/+9
Use "rp" instead of "%r2" in "b,l" insns.
2005-08-12 * s390-dis.c (print_insn_s390): Print unsigned operands with %u.Martin Schwidefsky5-12/+109
* s390-mkopc.c (s390_opcode_cpu_val): Add support for cpu type z9-109. (main): Likewise. * s390-opc.c (I32_16, U32_16, M_16): Add defines 32 bit immediates and 4 bit optional masks. (INSTR_RIL_RI, INSTR_RIL_RU, INSTR_RRF_M0RR, INSTR_RSE_CCRD, INSTR_RSY_CCRD, INSTR_SSF_RRDRD): Add new instruction formats. (MASK_RIL_RI, MASK_RIL_RU, MASK_RRF_M0RR, MASK_RSE_CCRD, MASK_RSY_CCRD, MASK_SSF_RRDRD): Likewise. (s390_opformats): Likewise. * s390-opc.txt: Add new instructions for cpu type z9-109.
2005-08-05 * hppa-dis.c (print_insn_hppa): Prefix 21-bit values with "L%".Dave Anglin2-0/+5
2005-07-292005-07-29 Paul Brook <paul@codesourcery.com>Paul Brook2-4/+8
bfd/ * reloc.c: Add BFD_RELOC_ARM_T32_ADD_PC12. * bfd-in2.h: Regenerate. * libbfd.h: Regenerate. gas/ * config/tc-arm.c (T16_32_TAB): Add "addr". Fix encoding of push and pop. (do_t_addr): Implement 32-bit variant. (do_t_push_pop): Make some errors warnings. Handle single register 32-bit case. (insns): Use tCE for adr. (md_pcrel_from_section): Handle BFD_RELOC_ARM_T32_ADD_PC12. (md_apply_fix): Ditto. gas/testsuite/ * gas/arm/thumb32.d: Fix expected output for writeback addressing modes. Add single high reg push/pop test. * gas/asm/thumb32.s: Add single high reg push/pop test. opcodes/ * arm-dis.c: Fix disassebly of thumb2 writeback addressing modes.
2005-07-292005-07-29 Paul Brook <paul@codesourcery.com>Paul Brook2-2/+7
bfd/ * reloc.c (BFD_RELOC_ARM_T32_IMM12): Add. * bfd-in2.h: Regeenrate. * libbfd.h: Regenerate. gas/ * config/tc-arm.c (parse_tb): New function. (enum operand_parse_code): Add OP_TB. (parse_operands): Handle OP_TB. (do_t_add_sub_w, do_t_tb): New functions. (insns): Add entries for addw, subw, tbb and tbh. (md_apply_fix): Handle BFD_RELOC_ARM_T32_IMM12. gas/testsuite/ * gas/arm/thumb32.s: Add tests for addw, subw, tbb and tbh. * gas/arm/thumb32.d: Ditto. opcodes/ * arm-dis.c (thumb32_opc): Fix addressing mode for tbh. (print_insn_thumb32): Fix decoding of thumb2 'I' operands.
2005-07-26missed from 2005-07-18 commitAlan Modra1-2/+2
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