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AgeCommit message (Expand)AuthorFilesLines
2018-07-30Add support for the C_SKY series of processors.Andrew Jenner9-0/+9228
2018-07-27Re: PowerPC Improve support for Gekko & BroadwayAlan Modra2-6/+12
2018-07-26PowerPC Improve support for Gekko & BroadwayAlex Chadwick3-5/+89
2018-07-25x86: Expand Broadcast to 3 bitsH.J. Lu4-398/+479
2018-07-24PR23430, Indices misspelledAlan Modra2-1/+6
2018-07-24x86-64: correct AVX512F vcvtsi2s{d,s} handlingJan Beulich4-40/+48
2018-07-23[ARC] Fix decoding of w6 signed short immediate.Claudiu Zissulescu2-1/+9
2018-07-23[ARC] Allow vewt instruction for ARC EM family.Claudiu Zissulescu2-2/+9
2018-07-23power9 mfupmc/mtupmcAlan Modra2-0/+24
2018-07-20MIPS/GAS: Split Loongson MMI Instructions from loongson2f/3aChenghua Xu3-82/+106
2018-07-19S/390: Set the htm flag on PPAAndreas Krebbel1-1/+1
2018-07-19x86: fold narrowing VCVT* templatesJan Beulich3-286/+114
2018-07-19x86: fold VFPCLASSP{D,S} templatesJan Beulich3-105/+29
2018-07-19x86: fold various AVX512* templatesJan Beulich3-1721/+218
2018-07-19x86: fold various AVX512DQ templatesJan Beulich3-881/+115
2018-07-19x86: fold various AVX512BW templatesJan Beulich3-4663/+554
2018-07-19x86: fold various AVX512CD templatesJan Beulich3-172/+28
2018-07-19x86: fold various AVX512VL templates into their AVX512F counterpartsJan Beulich4-14498/+1716
2018-07-19x86: pre-process opcodes table before parsingJan Beulich5-10/+49
2018-07-18x86: Split vcvtps2{,u}qq and vcvttps2{,u}qqH.J. Lu4-21/+109
2018-07-12This patch adds support for the SSBB and PSSBB speculation barrier instructio...Nick Clifton5-1006/+1024
2018-07-12Add remainder of Em16 restrictions for AArch64 gas.Tamar Christina2-26/+34
2018-07-11Adds the speculation barrier instructions to the ARM assembler and disassembler.Sudakshina Das2-6/+16
2018-07-11x86: adjust monitor/mwait templatesJan Beulich3-57/+67
2018-07-11x86: drop {,reg16_}inoutportreg variablesJan Beulich3-14/+7
2018-07-11x86/Intel: accept memory operand size specifiers for CET insnsJan Beulich3-8/+14
2018-07-11x86: replace off-by-one OTMaxJan Beulich2-4/+10
2018-07-09S12Z/opcodes: Correct a `reg' global shadowing error for pre-4.8 GCCMaciej W. Rozycki2-14/+22
2018-07-06Fix SBO bit in disassembly mask for ldrah on AArch64.Tamar Christina2-1/+6
2018-07-06Fix the read/write flag for these registers on AArch64Tamar Christina2-5/+11
2018-07-02GDB PR tdep/8282: MIPS: Wire in `set disassembler-options'Maciej W. Rozycki5-68/+205
2018-07-02[ARM] Update bfd's Tag_CPU_arch knowledgeThomas Preud'homme2-21/+58
2018-06-29Fix AArch64 encodings for by element instructions.Tamar Christina7-165/+194
2018-06-26Updated translations.Nick Clifton4-865/+1945
2018-06-26Fix spelling mistakes.Nick Clifton2-1/+5
2018-06-24Regenerate configure and pot files with updated binutils version number.Nick Clifton3-97/+140
2018-06-24Add 2.30 branch notes to ChangeLogs and NEWS files.Nick Clifton1-0/+4
2018-06-22Correct negs aliasing on AArch64.Tamar Christina4-5/+11
2018-06-21MIPS/opcodes: Fix a typo in `-M ginv' option descriptionMaciej W. Rozycki2-1/+6
2018-06-20RISC-V: Accept constant operands in la and llaSebastian Huber2-2/+8
2018-06-19Bump to autoconf 2.69 and automake 1.15.1Simon Marchi6-995/+1563
2018-06-14MIPS: Add Global INValidate ASE supportFaraz Shahbazker3-2/+30
2018-06-13MIPS: Add CRC ASE supportScott Egerton3-2/+26
2018-06-08Prevent undefined FMOV instructions being accepted by the AArch64 assembler.Egeyar Bagcioglu2-2/+22
2018-06-06Fix xtensa "clobbered by longjmp" warningsAlan Modra2-6/+12
2018-06-04xtensa: use property tables for correct disassemblyMax Filippov2-22/+206
2018-06-01Bump version number to 2.30.52H.J. Lu2-10/+14
2018-06-01x86: fold MOV to/from segment register templatesJan Beulich3-119/+16
2018-06-01x86: don't emit REX.W for SLDT and STRJan Beulich3-4/+9
2018-06-01x86/Intel: accept "oword ptr" for INVPCIDJan Beulich3-6/+11
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