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forced.
The disassembler for Arm has some aborts in it in places it assumes can never
be reached. Under normal circumstances they indeed cannot be reached because
the right options are selected from the ARM attributes in the ELF file.
However when disassembling with -b binary then if you do not get the options
right the disassembler just aborts. This changes it so it just prints how it
was trying to interpret the instruction and prints UNKNOWN instructions next to it.
This way the user has an idea of what's going.
gas/ChangeLog:
* testsuite/gas/arm/undefined-insn-arm.d: New test.
* testsuite/gas/arm/undefined-insn-thumb.d: New test.
* testsuite/gas/arm/undefined-insn.s: New test.
opcodes/ChangeLog:
* arm-dis.c (UNKNOWN_INSTRUCTION_32BIT): Format specifier for arm mode.
(UNKNOWN_INSTRUCTION_16BIT): Format specifier for thumb mode.
(print_insn_arm, print_insn_thumb16, print_insn_thumb32): Use them.
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Committed on behalf of Matthew Malcomson:
The SIMD UDOT instruction assembly has an unusual operand that selects a single
32 bit element with the mnemonic 4B.
This unusual mnemonic is handled by a special operand qualifier and associated
qualifier data in `aarch64_opnd_qualifiers`.
The current qualifier data describes 4 1-byte elements with the structure
{1, 4, 0x0, "4b", OQK_OPD_VARIANT}
This makes sense, as the instruction does work on 4 1-byte elements, however
some logic in the `operand_general_constraint_met_p` makes assumptions about
the range of index allowed when selecting a SIMD_ELEMENT depending on element
size.
That function reasons that e.g. in order to select a byte-sized element in a 16
byte V register an index must allow selection of one of the 16 elements and
hence its range will be in [0,15].
This reasoning breaks with the above description of a 4 part selection of 1
byte elements and allows an index outside the valid [0,3] range, triggering an
assert later on in the program in `aarch64_ins_reglane`.
vshcmd: > echo 'udot v0.2s, v1.8b, v2.4b[4]' | ../src/binutils-build/gas/as-new -march=armv8.4-a
as-new: ../../binutils-gdb/opcodes/aarch64-asm.c:134: aarch64_ins_reglane: Assertion `reglane_index < 4' failed.
{standard input}: Assembler messages:
{standard input}:1: Internal error (Aborted).
Please report this bug.
This patch changes the operand qualifier data so that it describes a single
32 bit element.
{4, 1, 0x0, "4b", OQK_OPD_VARIANT}
Hence the calculation in `operand_general_constraint_met_p` provides the
correct answer and the usual error checking machinery is used.
vshcmd: > echo 'udot v0.2s, v1.8b, v2.4b[4]' | ../src/binutils-build/gas/as-new -march=armv8.4-a
{standard input}: Assembler messages:
{standard input}:1: Error: register element index out of range 0 to 3 at operand 3 -- `udot v0.2s,v1.8b,v2.4b[4]'
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Only one of them can be set at a time, which means they can be expressed
by a single 2-bit field instead of three 1-bit ones.
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This patch is part of the patch series to add support for ARMv8.5-A
extensions.
(https://developer.arm.com/products/architecture/cpu-architecture/a-profile/exploration-tools)
The encodings can be found in the System Register XML.
This patch adds support for the mitigation for Spectre Variant 4 by
adding the PSTATE bit SSBS which are accessible using MSR and MRS
instructions. Although this is a mandatory addition to the ARMv8.5-A,
it is permitted to be added to any version of the ARMv8 architecture.
This is enabled using the command line option of +ssbs for older
versions.
*** include/ChangeLog ***
2018-10-09 Sudakshina Das <sudi.das@arm.com>
* opcode/aarch64.h (AARCH64_FEATURE_SSBS): New.
(AARCH64_ARCH_V8_5): Add AARCH64_FEATURE_SSBS by default.
*** opcodes/ChangeLog ***
2018-10-09 Sudakshina Das <sudi.das@arm.com>
* aarch64-opc.c (operand_general_constraint_met_p): Add
SSBS in the check for one-bit immediate.
(aarch64_sys_regs): New entry for SSBS.
(aarch64_sys_reg_supported_p): New check for above.
(aarch64_pstatefields): New entry for SSBS.
(aarch64_pstatefield_supported_p): New check for above.
*** gas/ChangeLog ***
2018-10-09 Sudakshina Das <sudi.das@arm.com>
* config/tc-aarch64.c (aarch64_features): Add new "ssbs".
* doc/c-aarch64.texi: Document the same.
* testsuite/gas/aarch64/ssbs-illegal1.d: New test.
* testsuite/gas/aarch64/ssbs-illegal1.l: New test.
* testsuite/gas/aarch64/ssbs-illegal2.d: New test.
* testsuite/gas/aarch64/ssbs-illegal2.l: New test.
* testsuite/gas/aarch64/ssbs.s: New test.
* testsuite/gas/aarch64/ssbs1.d: Test with +ssbs
* testsuite/gas/aarch64/ssbs2.d: Test with armv8.5-a.
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This patch is part of the patch series to add support for ARMv8.5-A
extensions.
(https://developer.arm.com/products/architecture/cpu-architecture/a-profile/exploration-tools)
The encodings can be found in the System Register XML.
This patch adds the new system registers SCXTNUM_ELx and ID_PFR2_EL1.
*** include/ChangeLog ***
2018-10-09 Sudakshina Das <sudi.das@arm.com>
* opcode/aarch64.h (AARCH64_FEATURE_SCXTNUM): New.
(AARCH64_FEATURE_ID_PFR2): New.
(AARCH64_ARCH_V8_5): Add both by default.
*** opcodes/ChangeLog ***
2018-10-09 Sudakshina Das <sudi.das@arm.com>
* aarch64-opc.c (aarch64_sys_regs): New entries for
scxtnum_el[0,1,2,3,12] and id_pfr2_el1.
(aarch64_sys_reg_supported_p): New checks for above.
*** gas/ChangeLog ***
2018-10-09 Sudakshina Das <sudi.das@arm.com>
* testsuite/gas/aarch64/sysreg-4.s: Test registers
scxtnum_el[0,1,2,3,12] and id_pfr2_el1.
* testsuite/gas/aarch64/sysreg-4.d: Likewise.
* testsuite/gas/aarch64/illegal-sysreg-4.l: Likewise.
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This patch is part of the patch series to add support for ARMv8.5-A
extensions.
(https://developer.arm.com/products/architecture/cpu-architecture/a-profile/docs/ddi0596/a/a64-base-instructions-alphabetic-order/bti-branch-target-identification)
The Branch Target Identification instructions (BTI) are allocated to
existing HINT space, using HINT numbers 32, 34, 36, 38, such that
bits[7:6] of the instruction identify the compatibility of the BTI
instruction to different branches.
BTI {<targets>}
where <targets> one of the following, specifying which type of
indirection is allowed:
j : Can be a target of any BR Xn isntruction.
c : Can be a target of any BLR Xn and BR {X16|X17}.
jc: Can be a target of any free branch.
A BTI instruction without any <targets> is the strictest of all and
can not be a target of nay free branch.
*** include/ChangeLog ***
2018-10-09 Sudakshina Das <sudi.das@arm.com>
* opcode/aarch64.h (AARCH64_FEATURE_BTI): New.
(AARCH64_ARCH_V8_5): Add AARCH64_FEATURE_BTI by default.
(aarch64_opnd): Add AARCH64_OPND_BTI_TARGET.
(HINT_OPD_CSYNC, HINT_OPD_C, HINT_OPD_J): New macros to
define HINT #imm values.
(HINT_OPD_JC, HINT_OPD_NULL): Likewise.
*** opcodes/ChangeLog ***
2018-10-09 Sudakshina Das <sudi.das@arm.com>
* aarch64-opc.h (HINT_OPD_NOPRINT, HINT_ENCODE): New.
(HINT_FLAG, HINT_VALUE): New macros to encode NO_PRINT flag
with the hint immediate.
* aarch64-opc.c (aarch64_hint_options): New entries for
c, j, jc and default (with HINT_OPD_F_NOPRINT flag) for BTI.
(aarch64_print_operand): Add case for AARCH64_OPND_BTI_TARGET
while checking for HINT_OPD_F_NOPRINT flag.
* aarch64-dis.c (aarch64_ext_hint): Use new HINT_VALUE to
extract value.
* aarch64-tbl.h (aarch64_feature_bti, BTI, BTI_INSN): New.
(aarch64_opcode_table): Add entry for BTI.
(AARCH64_OPERANDS): Add new description for BTI targets.
* aarch64-asm-2.c: Regenerate.
* aarch64-dis-2.c: Regenerate.
* aarch64-opc-2.c: Regenerate.
*** gas/ChangeLog ***
2018-10-09 Sudakshina Das <sudi.das@arm.com>
* config/tc-aarch64.c (parse_bti_operand): New.
(process_omitted_operand): Add case for AARCH64_OPND_BTI_TARGET.
(parse_operands): Likewise.
* testsuite/gas/aarch64/system.d: Update for BTI.
* testsuite/gas/aarch64/bti.s: New.
* testsuite/gas/aarch64/bti.d: New.
* testsuite/gas/aarch64/illegal-bti.d: New.
* testsuite/gas/aarch64/illegal-bti.l: New.
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This patch is part of the patch series to add support for ARMv8.5-A
extensions.
(https://developer.arm.com/products/architecture/cpu-architecture/a-profile/exploration-tools)
The encodings can be found in the System Register XML.
This patch adds the following:
MSR Xn, RNDR
MSR Xn, RNDRRS
These are optional instructions in ARMv8.5-A and hence the new
+rng is added.
*** include/ChangeLog ***
2018-10-09 Sudakshina Das <sudi.das@arm.com>
* opcode/aarch64.h (AARCH64_FEATURE_RNG): New.
*** opcodes/ChangeLog ***
2018-10-09 Sudakshina Das <sudi.das@arm.com>
* aarch64-opc.c (aarch64_sys_regs): New entries for
rndr and rndrrs.
(aarch64_sys_reg_supported_p): New check for above.
*** gas/ChangeLog ***
2018-10-09 Sudakshina Das <sudi.das@arm.com>
* config/tc-aarch64.c (aarch64_features): New "rng" option.
* doc/c-aarch64.texi: Document the same.
* testsuite/gas/aarch64/sysreg-4.s: Test both instructions.
* testsuite/gas/aarch64/sysreg-4.d: Likewise.
* testsuite/gas/aarch64/illegal-sysreg-4.l: Likewise.
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This patch is part of the patch series to add support for ARMv8.5-A
extensions.
(https://developer.arm.com/products/architecture/cpu-architecture/a-profile/docs/ddi0596/a/a64-base-instructions-alphabetic-order/dc-data-cache-operation-an-alias-of-sys)
This patch adds the DC CVADP instruction. Since this has a separate
identification mechanism a new feature bit is added.
*** include/ChangeLog ***
2018-10-09 Sudakshina Das <sudi.das@arm.com>
* opcode/aarch64.h (AARCH64_FEATURE_CVADP): New.
*** opcodes/ChangeLog ***
2018-10-09 Sudakshina Das <sudi.das@arm.com>
* aarch64-opc.c (aarch64_sys_regs_dc): New entry for cvadp.
(aarch64_sys_ins_reg_supported_p): New check for above.
*** gas/ChangeLog ***
2018-10-09 Sudakshina Das <sudi.das@arm.com>
* testsuite/gas/aarch64/sysreg-4.s: Test instruction.
* testsuite/gas/aarch64/sysreg-4.d: Likewise.
* testsuite/gas/aarch64/illegal-sysreg-4.l: Likewise.
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This patch is part of the patch series to add support for ARMv8.5-A
extensions.
(https://developer.arm.com/products/architecture/cpu-architecture/a-profile/docs/ddi0596/a/a64-base-instructions-alphabetic-order)
This patch adds the prediction restriction instructions (that is, cfp,
dvp, cpp). These instructions are retrospectively made optional for
all versions of the architecture from ARMv8.0 to ARMv8.4 and is
mandatory from ARMv8.5. Hence adding a new +predres which can be used
by the older architectures.
*** include/ChangeLog ***
2018-10-09 Sudakshina Das <sudi.das@arm.com>
* opcode/aarch64.h (AARCH64_FEATURE_PREDRES): New.
(AARCH64_ARCH_V8_5): Add AARCH64_FEATURE_PREDRES by default.
(aarch64_opnd): Add AARCH64_OPND_SYSREG_SR.
(aarch64_sys_regs_sr): Declare new table.
*** opcodes/ChangeLog ***
2018-10-09 Sudakshina Das <sudi.das@arm.com>
* aarch64-dis.c (aarch64_ext_sysins_op): Add case for
AARCH64_OPND_SYSREG_SR.
* aarch64-opc.c (aarch64_print_operand): Likewise.
(aarch64_sys_regs_sr): Define table.
(aarch64_sys_ins_reg_supported_p): Check for RCTX with
AARCH64_FEATURE_PREDRES.
* aarch64-tbl.h (aarch64_feature_predres): New.
(PREDRES, PREDRES_INSN): New.
(aarch64_opcode_table): Add entries for cfp, dvp and cpp.
(AARCH64_OPERANDS): Add new description for SYSREG_SR.
* aarch64-asm-2.c: Regenerate.
* aarch64-dis-2.c: Regenerate.
* aarch64-opc-2.c: Regenerate.
*** gas/ChangeLog ***
2018-10-09 Sudakshina Das <sudi.das@arm.com>
* config/tc-aarch64.c (aarch64_sys_regs_sr_hsh): New.
(parse_operands): Add entry for AARCH64_OPND_SYSREG_SR.
(md_begin): Allocate and initialize aarch64_sys_regs_sr_hsh
with aarch64_sys_regs_sr.
(aarch64_features): Add new "predres" option for older
architectures.
* doc/c-aarch64.texi: Document the same.
* testsuite/gas/aarch64/sysreg-4.s: New.
* testsuite/gas/aarch64/sysreg-4.d: New.
* testsuite/gas/aarch64/illegal-sysreg-4.d: New.
* testsuite/gas/aarch64/illegal-sysreg-4.l: New.
* testsuite/gas/aarch64/predres.s: New.
* testsuite/gas/aarch64/predres.d: New.
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This patch is part of the patch series to add support for ARMv8.5-A
extensions.
(https://developer.arm.com/products/architecture/cpu-architecture/a-profile/docs/ddi0596/a/a64-base-instructions-alphabetic-order)
This instruction is retrospectively made optional for all versions of
the architecture from ARMv8.0 to ARMv8.4 and is mandatory from
ARMv8.5. Hence a new command line option of "+sb" is added for older
architectures.
*** include/ChangeLog ***
2018-10-09 Sudakshina Das <sudi.das@arm.com>
* opcode/aarch64.h (AARCH64_FEATURE_SB): New.
(AARCH64_ARCH_V8_5): Add AARCH64_FEATURE_SB by default.
*** opcodes/ChangeLog ***
2018-10-09 Sudakshina Das <sudi.das@arm.com>
* aarch64-tbl.h (aarch64_feature_sb): New.
(SB, SB_INSN): New.
(aarch64_opcode_table): Add entry for sb.
* aarch64-asm-2.c: Regenerate.
* aarch64-dis-2.c: Regenerate.
* aarch64-opc-2.c: Regenerate.
*** gas/ChangeLog ***
2018-10-09 Sudakshina Das <sudi.das@arm.com>
* config/tc-aarch64.c (aarch64_features): Add new "sb" option
for older architectures.
* doc/c-aarch64.texi: Document the same.
* testsuite/gas/aarch64/sb.s: New.
* testsuite/gas/aarch64/sb.d: New.
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This patch is part of the patch series to add support for ARMv8.5-A
extensions.
(https://developer.arm.com/products/architecture/cpu-architecture/a-profile/docs/ddi0596/a/a64-base-instructions-alphabetic-order)
This patch adds the data processing instructions that are new to
ARMv8.5-A.
1) There are 2 instructions: xaflag, axflag, that are added to
manipulate the states of the flag and are used to convert between the
Arm representation and the fcmp representation.
2) The other instructions are rounding instructions which have 8
versions based on whether the floating-point number is a
Single-Precision or Double-Precision number, whether the target
integer is a 32-bit or 64-bit integer and whether the rounding mode is
the ambient rounding mode or to zero. Each of these instruction is
available in both Scalar and Vector forms.
Since both 1) and 2) have separate identification mechanism and it is
permissible that a ARMv8.4 compliant implementation may include any
arbitrary subset of the ARMv8.5 features unless otherwise specified,
new feature bits are added.
*** include/ChangeLog ***
2018-10-09 Sudakshina Das <sudi.das@arm.com>
* opcode/aarch64.h (AARCH64_FEATURE_FLAGMANIP): New.
(AARCH64_FEATURE_FRINTTS): New.
(AARCH64_ARCH_V8_5): Add both by default.
*** opcodes/ChangeLog ***
2018-10-09 Sudakshina Das <sudi.das@arm.com>
* aarch64-tbl.h (aarch64_feature_flagmanip): New.
(aarch64_feature_frintts): New.
(FLAGMANIP, FRINTTS): New.
(aarch64_opcode_table): Add entries for xaflag, axflag
and frint[32,64][x,z] instructions.
* aarch64-asm-2.c: Regenerate.
* aarch64-dis-2.c: Regenerate.
* aarch64-opc-2.c: Regenerate.
*** gas/ChangeLog ***
2018-10-09 Sudakshina Das <sudi.das@arm.com>
* testsuite/gas/aarch64/armv8_5-a-dp.s: New.
* testsuite/gas/aarch64/armv8_5-a-dp.d: New.
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feature macros
This patch is part of the patch series to add support for ARMv8.5-A
extensions.
(https://developer.arm.com/products/architecture/cpu-architecture/a-profile/exploration-tools)
This is the first of the patch series and adds -march=armv8.5-a and
other internal feature marcos needed for it.
2018-10-09 Sudakshina Das <sudi.das@arm.com>
* config/tc-aarch64.c (aarch64_archs): New entry for armv8.5-a.
* doc/c-aarch64.texi: Add documentation for the same.
*** include/ChnageLog ***
2018-10-09 Sudakshina Das <sudi.das@arm.com>
* opcode/aarch64.h (AARCH64_FEATURE_V8_5): New.
(AARCH64_ARCH_V8_5): New.
*** opcodes/ChangeLog ***
2018-10-09 Sudakshina Das <sudi.das@arm.com>
* aarch64-tbl.h (aarch64_feature_set aarch64_feature_v8_5): New.
(ARMV8_5, V8_5_INSN): New.
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Clang doesn't accept {0} as a valid C struct initializer under their implementation
of -Wmissing-field-initializers. This makes using C initializers a bit tricky.
Instead I'm changing the code to use memset instead, which at least GCC inlines and
generates the same code for. This also seems to be the idiom used in binutils for
most targets.
opcodes/
* aarch64-opc.c (verify_constraints): Use memset instead of {0}.
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gas/
* testsuite/gas/i386/se1.s: Add enclv.
* testsuite/gas/i386/x86-64-se1.s: Likewise.
* testsuite/gas/i386/se1.d: Updated.
* testsuite/gas/i386/x86-64-se1.d: Likewise.
opcodes/
* i386-dis.c (rm_table): Add enclv.
* i386-opc.tbl: Add enclv.
* i386-tbl.h: Regenerated.
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This patch is part of the patch series to add support for ARMv8.5-A
extensions.
(https://developer.arm.com/products/architecture/cpu-architecture/a-profile/exploration-tools)
This patch adds the instruction SB. This instruction is
retrospectively made optional for all versions of the architecture
from ARMv8.0 to ARMv8.4 and is mandatory from ARMv8.5. Hence adding a
new "+sb" for older archtectures.
*** include/ChangeLog ***
2018-10-05 Sudakshina Das <sudi.das@arm.com>
* opcode/arm.h (ARM_EXT2_SB): New.
(ARM_ARCH_V8_5A): Add ARM_EXT2_SB by default.
*** opcodes/ChangeLog ***
2018-10-05 Sudakshina Das <sudi.das@arm.com>
* arm-dis.c (arm_opcodes): Add sb.
(thumb32_opcodes): Likewise.
*** gas/ChangeLog ***
2018-10-05 Sudakshina Das <sudi.das@arm.com>
* config/tc-arm.c (arm_ext_sb): New.
(insns): Add new sb instruction.
(arm_extensions): Add "sb".
* doc/c-arm.texi: Document the above.
* testsuite/gas/arm/sb-bad.d: New test.
* testsuite/gas/arm/sb-bad.l: New test.
* testsuite/gas/arm/sb-thumb1.d: New test.
* testsuite/gas/arm/sb-thumb2.d: New test.
* testsuite/gas/arm/sb.s: New test.
* testsuite/gas/arm/sb1.d: New test.
* testsuite/gas/arm/sb2.d: New test.
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Also fix the incorrect definitions of multiply and divide carry and
overflow float.
Changes to the instructions are made in the .cpu file, then we
regenerate the binutils and sim files.
The changes also required a few fixups for tests and additional sim helpers.
cpu/ChangeLog:
yyyy-mm-dd Richard Henderson <rth@twiddle.net>
Stafford Horne <shorne@gmail.com>
* or1korbis.cpu (insn-opcode-mac): Add opcodes for MACU and MSBU.
(insn-opcode-alu-regreg): Add opcodes for MULD and MULDU.
(l-mul): Fix overflow support and indentation.
(l-mulu): Fix overflow support and indentation.
(l-muld, l-muldu, l-msbu, l-macu): New instructions.
(l-div); Remove incorrect carry behavior.
(l-divu): Fix carry and overflow behavior.
(l-mac): Add overflow support.
(l-msb, l-msbu): Add carry and overflow support.
opcodes/ChangeLog:
yyyy-mm-dd Richard Henderson <rth@twiddle.net>
Stafford Horne <shorne@gmail.com>
* or1k-desc.c: Regenerate.
* or1k-desc.h: Regenerate.
* or1k-opc.c: Regenerate.
* or1k-opc.h: Regenerate.
* or1k-opinst.c: Regenerate.
sim/common/ChangeLog:
yyyy-mm-dd Stafford Horne <shorne@gmail.com>
* cgen-ops.h (ADDCFDI): New function, add carry flag DI variant.
(ADDOFDI): New function, add overflow flag DI variant.
(SUBCFDI): New function, subtract carry flag DI variant.
(SUBOFDI): New function, subtract overflow flag DI variant.
sim/ChangeLog:
yyyy-mm-dd Stafford Horne <shorne@gmail.com>
* or1k/cpu.h: Regenerate.
* or1k/decode.c: Regenerate.
* or1k/decode.h: Regenerate.
* or1k/model.c: Regenerate.
* or1k/sem-switch.c: Regenerate.
* or1k/sem.c: Regenerate:
sim/testsuite/sim/or1k/ChangeLog:
yyyy-mm-dd Stafford Horne <shorne@gmail.com>
* div.S: Fix tests to match correct overflow/carry semantics.
* mul.S: Likewise.
gas/ChangeLog:
yyyy-mm-dd Stafford Horne <shorne@gmail.com>
* testsuite/gas/or1k/allinsn.s: Add instruction tests for
l.muld, l.muldu, l.macu, l.msb, l.msbu.
* testsuite/gas/or1k/allinsn.d: Add test results for new
instructions.
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This patch adds the new instruction and relocation as per proposal:
https://openrisc.io/proposals/ladrp
This is to be added to the spec in an upcoming revision. The new instruction
l.adrp loads the page offset of the current instruction offset by
a 21-bit immediate shifted left 13-bits. This is meant to be used with
a 13-bit lower bit page offset. This allows us to free up the got
register r16.
l.adrp r3, foo
l.ori r4, r3, po(foo)
l.lbz r5, po(foo)(r3)
l.sb po(foo)(r3), r6
The relocations we add are:
- BFD_RELOC_OR1K_PLTA26 For PLT jump relocation with PLT entry
asm: plta() implemented using l.ardp, meaning
no need for r16 (the GOT reg)
- BFD_RELOC_OR1K_GOT_PG21 Upper 21-bit Page offset got address
asm: got()
- BFD_RELOC_OR1K_TLS_GD_PG21 Upper 21-bit Page offset with TLS General
asm: tlsgd() Dynamic calculation
- BFD_RELOC_OR1K_TLS_LDM_PG21 Upper 21-bit Page offset with TLS local
asm: tlsldm() dynamic calculation
- BFD_RELOC_OR1K_TLS_IE_PG21 Upper 21-bit Page offset with TLS Initial
asm: gottp() Executable calculation
- BFD_RELOC_OR1K_PCREL_PG21 Default relocation for disp21 (l.adrp
instructions)
- BFD_RELOC_OR1K_LO13 low 13-bit page offset relocation
asm: po() i.e. mem loads, addi etc
- BFD_RELOC_OR1K_SLO13 low 13-bit page offset relocation
asm: po() i.e. mem stores, with split immediate
- BFD_RELOC_OR1K_GOT_LO13, low 13-bit page offset with GOT calcs
asm: gotpo()
- BFD_RELOC_OR1K_TLS_GD_LO13 Lower 13-bit offset with TLS GD calcs
asm: tlsgdpo()
- BFD_RELOC_OR1K_TLS_LDM_LO13 Lower 13-bit offset with TLS LD calcs
asm: tlsldmpo()
- BFD_RELOC_OR1K_TLS_IE_LO13 Lower 13-bit offset with TLS IE calcs
asm: gottppo()
bfd/ChangeLog:
yyyy-mm-dd Richard Henderson <rth@twiddle.net>
* bfd-in2.h: Regenerated.
* elf32-or1k.c: (or1k_elf_howto_table): Fix formatting for
R_OR1K_PLT26, Add R_OR1K_PCREL_PG21, R_OR1K_GOT_PG21,
R_OR1K_TLS_GD_PG21, R_OR1K_TLS_LDM_PG21, R_OR1K_TLS_IE_PG21,
R_OR1K_LO13, R_OR1K_GOT_LO13, R_OR1K_TLS_GD_LO13, R_OR1K_TLS_LDM_LO13,
R_OR1K_TLS_IE_LO13, R_OR1K_SLO13, R_OR1K_PLTA26.
(or1k_reloc_map): Add BFD_RELOC_OR1K_PCREL_PG21,
BFD_RELOC_OR1K_GOT_PG21, BFD_RELOC_OR1K_TLS_GD_PG21,
BFD_RELOC_OR1K_TLS_LDM_PG21, BFD_RELOC_OR1K_TLS_IE_PG21,
BFD_RELOC_OR1K_LO13, BFD_RELOC_OR1K_GOT_LO13,
BFD_RELOC_OR1K_TLS_GD_LO13, BFD_RELOC_OR1K_TLS_GD_LO13,
BFD_RELOC_OR1K_TLS_LDM_LO13, BFD_RELOC_OR1K_TLS_IE_LO13,
BFD_RELOC_OR1K_SLO13, BFD_RELOC_OR1K_PLTA26.
(elf_or1k_link_hash_table): Add field saw_plta.
(or1k_final_link_relocate): Add value calculations for new relocations.
(or1k_elf_relocate_section): Add section relocations for new
relocations.
(or1k_write_plt_entry): New function.
(or1k_elf_finish_dynamic_sections): Add support for PLTA relocations
using new l.adrp instruction. Cleanup PLT relocation code generation.
* libbfd.h: Regenerated.
* reloc.c: Add BFD_RELOC_OR1K_PCREL_PG21, BFD_RELOC_OR1K_LO13,
BFD_RELOC_OR1K_SLO13, BFD_RELOC_OR1K_GOT_PG21, BFD_RELOC_OR1K_GOT_LO13,
BFD_RELOC_OR1K_PLTA26, BFD_RELOC_OR1K_TLS_GD_PG21,
BFD_RELOC_OR1K_TLS_GD_LO13, BFD_RELOC_OR1K_TLS_LDM_PG21,
BFD_RELOC_OR1K_TLS_LDM_LO13, BFD_RELOC_OR1K_TLS_IE_PG21,
BFD_RELOC_OR1K_TLS_IE_LO13.
cpu/ChangeLog:
yyyy-mm-dd Richard Henderson <rth@twiddle.net>
* or1k.opc (parse_disp26): Add support for plta() relocations.
(parse_disp21): New function.
(or1k_rclass): New enum.
(or1k_rtype): New enum.
(or1k_imm16_relocs): Define new PO and SPO relocation mappings.
(parse_reloc): Add new po(), gotpo() and gottppo() for LO13 relocations.
(parse_imm16): Add support for the new 21bit and 13bit relocations.
* or1korbis.cpu (f-disp26): Don't assume SI.
(f-disp21): New pc-relative 21-bit 13 shifted to right.
(insn-opcode): Add ADRP.
(l-adrp): New instruction.
gas/ChangeLog:
yyyy-mm-dd Richard Henderson <rth@twiddle.net>
* config/tc-or1k.c (or1k_apply_fix): Add BFD_RELOC_OR1K_TLS_GD_PG21,
BFD_RELOC_OR1K_TLS_GD_LO13, BFD_RELOC_OR1K_TLS_LDM_PG21,
BFD_RELOC_OR1K_TLS_LDM_LO13, BFD_RELOC_OR1K_TLS_IE_PG21,
BFD_RELOC_OR1K_TLS_IE_LO13.
* testsuite/gas/or1k/allinsn.s: Add test for l.adrp.
* testsuite/gas/or1k/allinsn.d: Add test results for new
instructions.
* testsuite/gas/or1k/reloc-1.s: Add tests to generate
R_OR1K_PLTA26, R_OR1K_GOT_PG21, R_OR1K_TLS_GD_PG21, R_OR1K_TLS_LDM_PG21,
R_OR1K_TLS_IE_PG21, R_OR1K_LO13, R_OR1K_GOT_LO13, R_OR1K_TLS_GD_LO13,
R_OR1K_TLD_LDM_LO13, R_OR1K_TLS_IE_LO13, R_OR1K_LO13, R_OR1K_SLO13
relocations.
* testsuite/gas/or1k/reloc-1.d: Add relocation results for
tests.
* testsuite/gas/or1k/reloc-2.s: Add negative tests for store to
gotpo().
* testsuite/gas/or1k/reloc-2.l: Add expected error test results.
ld/ChangeLog:
yyyy-mm-dd Richard Henderson <rth@twiddle.net>
* testsuite/ld-or1k/or1k.exp: Add test cases for plt generation.
* testsuite/ld-or1k/plt1.dd: New file.
* testsuite/ld-or1k/plt1.s: New file.
* testsuite/ld-or1k/plt1.x.dd: New file.
* testsuite/ld-or1k/plta1.dd: New file.
* testsuite/ld-or1k/plta1.s: New file.
* testsuite/ld-or1k/pltlib.s: New file.
include/ChangeLog:
yyyy-mm-dd Richard Henderson <rth@twiddle.net>
* elf/or1k.h (elf_or1k_reloc_type): Add R_OR1K_PCREL_PG21,
R_OR1K_GOT_PG21, R_OR1K_TLS_GD_PG21, R_OR1K_TLS_LDM_PG21,
R_OR1K_TLS_IE_PG21, R_OR1K_LO13, R_OR1K_GOT_LO13,
R_OR1K_TLS_GD_LO13, R_OR1K_TLS_LDM_LO13, R_OR1K_TLS_IE_LO13,
R_OR1K_SLO13, R_OR1K_PLTA26.
opcodes/ChangeLog:
yyyy-mm-dd Richard Henderson <rth@twiddle.net>
* or1k-asm.c: Regenerated.
* or1k-desc.c: Regenerated.
* or1k-desc.h: Regenerated.
* or1k-dis.c: Regenerated.
* or1k-ibld.c: Regenerated.
* or1k-opc.c: Regenerated.
* or1k-opc.h: Regenerated.
* or1k-opinst.c: Regenerated.
|
|
This patch adds the following target relocations:
- BFD_RELOC_HI16_S High 16-bit relocation, for used with signed
asm: ha() lower.
- BFD_RELOC_HI16_S_GOTOFF High 16-bit GOT offset relocation for local
asm: gotoffha() symbols, for use with signed lower.
- BFD_RELOC_OR1K_TLS_IE_AHI16 High 16-bit TLS relocation with initial
asm: gottpoffha() executable calculation, for use with signed
lower.
- BFD_RELOC_OR1K_TLS_LE_AHI16 High 16-bit TLS relocation for local executable
asm: tpoffha() variables, for use with signed lower.
- BFD_RELOC_OR1K_SLO16 Split lower 16-bit relocation, used with
asm: lo() OpenRISC store instructions.
- BFD_RELOC_OR1K_GOTOFF_SLO16 Split lower 16-bit GOT offset relocation for
asm: gotofflo() local symbols, used with OpenRISC store
instructions.
- BFD_RELOC_OR1K_TLS_LE_SLO16 Split lower 16-bit relocation for TLS local
asm: tpofflo() executable variables, used with OpenRISC store
instructions.
bfd/ChangeLog:
yyyy-mm-dd Richard Henderson <rth@twiddle.net>
Stafford Horne <shorne@gmail.com>
* bfd-in2.h: Regenerated.
* elf32-or1k.c (N_ONES): New macro.
(or1k_elf_howto_table): Fix R_OR1K_PLT26 to complain on overflow.
Add definitions for R_OR1K_TLS_TPOFF, R_OR1K_TLS_DTPOFF,
R_OR1K_TLS_DTPMOD, R_OR1K_AHI16, R_OR1K_GOTOFF_AHI16,
R_OR1K_TLS_IE_AHI16, R_OR1K_TLS_LE_AHI16, R_OR1K_SLO16,
R_OR1K_GOTOFF_SLO16, R_OR1K_TLS_LE_SLO16.
(or1k_reloc_map): Add entries for BFD_RELOC_HI16_S,
BFD_RELOC_LO16_GOTOFF, BFD_RELOC_HI16_GOTOFF, BFD_RELOC_HI16_S_GOTOFF,
BFD_RELOC_OR1K_TLS_IE_AHI16, BFD_RELOC_OR1K_TLS_LE_AHI16,
BFD_RELOC_OR1K_SLO16, BFD_RELOC_OR1K_GOTOFF_SLO16,
BFD_RELOC_OR1K_TLS_LE_SLO16.
(or1k_reloc_type_lookup): Change search loop to start ad index 0 and
also check results before returning.
(or1k_reloc_name_lookup): Simplify loop to use R_OR1K_max as index
limit.
(or1k_final_link_relocate): New function.
(or1k_elf_relocate_section): Add support for new AHI and SLO
relocations. Use or1k_final_link_relocate instead of generic
_bfd_final_link_relocate.
(or1k_elf_check_relocs): Add support for new AHI and SLO relocations.
* reloc.c: Add new enums for BFD_RELOC_OR1K_SLO16,
BFD_RELOC_OR1K_GOTOFF_SLO16, BFD_RELOC_OR1K_TLS_IE_AHI16,
BFD_RELOC_OR1K_TLS_IE_AHI16, BFD_RELOC_OR1K_TLS_LE_AHI16,
BFD_RELOC_OR1K_TLS_LE_SLO16. Remove unused BFD_RELOC_OR1K_GOTOFF_HI16
and BFD_RELOC_OR1K_GOTOFF_LO16.
* libbfd.h: Regenerated.
cpu/ChangeLog:
yyyy-mm-dd Richard Henderson <rth@twiddle.net>
* or1k.opc: Add RTYPE_ enum.
(INVALID_STORE_RELOC): New string.
(or1k_imm16_relocs): New array array.
(parse_reloc): New static function that just does the parsing.
(parse_imm16): New static function for generic parsing.
(parse_simm16): Change to just call parse_imm16.
(parse_simm16_split): New function.
(parse_uimm16): Change to call parse_imm16.
(parse_uimm16_split): New function.
* or1korbis.cpu (simm16-split): Change to use new simm16_split.
(uimm16-split): Change to use new uimm16_split.
gas/ChangeLog:
yyyy-mm-dd Richard Henderson <rth@twiddle.net>
* testsuite/gas/or1k/allinsn.d (l_ha): Add result for ha() relocation.
* testsuite/gas/or1k/allinsn.s (l_ha): Add test for ha() relocations.
* testsuite/gas/or1k/allinsn.exp: Renamed to or1k.exp.
* testsuite/gas/or1k/or1k.exp: Add reloc-2 list test.
* testsuite/gas/or1k/reloc-1.d: New file.
* testsuite/gas/or1k/reloc-1.s: New file.
* testsuite/gas/or1k/reloc-2.l: New file.
* testsuite/gas/or1k/reloc-2.s: New file.
include/ChangeLog:
yyyy-mm-dd Richard Henderson <rth@twiddle.net>
* elf/or1k.h (elf_or1k_reloc_type): Add R_OR1K_AHI16,
R_OR1K_GOTOFF_AHI16, R_OR1K_TLS_IE_AHI16, R_OR1K_TLS_LE_AHI16,
R_OR1K_SLO16, R_OR1K_GOTOFF_SLO16, R_OR1K_TLS_LE_SLO16.
ld/ChangeLog:
yyyy-mm-dd Richard Henderson <rth@twiddle.net>
* testsuite/ld-or1k/offsets1.d: New file.
* testsuite/ld-or1k/offsets1.s: New file.
* testsuite/ld-or1k/or1k.exp: New file.
opcodes/ChangeLog:
yyyy-mm-dd Richard Henderson <rth@twiddle.net>
* or1k-asm.c: Regenerate.
|
|
This patch wires in the new constraint verifiers into the assembler and
disassembler. Because of this the MOVPRFX tests have to be split out from the
generic SVE tests into their own tests so warnings can be ignored.
These tests are only intended to test the encoding correctness and not the
constraints.
gas/
* testsuite/gas/aarch64/sve-movprfx.d: New test.
* testsuite/gas/aarch64/sve-movprfx.s: New test.
* testsuite/gas/aarch64/sve.d: Refactor.
* testsuite/gas/aarch64/sve.s: Refactor.
* testsuite/gas/aarch64/sysreg-diagnostic.d: Update.
opcodes/
* aarch64-asm.c (aarch64_opcode_encode): Apply constraint verifier.
* aarch64-dis.c (print_operands): Refactor to take notes.
(print_verifier_notes): New.
(print_aarch64_insn): Apply constraint verifier.
(print_insn_aarch64_word): Update call to print_aarch64_insn.
* aarch64-opc.c (aarch64_print_operand): Remove attribute, update notes format.
|
|
This patch adds the verification rules for move prefix constraints.
The Arm SVE instruction MOVPRFX introduces[1] constraints on the instruction at
PC+4. Particularly the following constraints are handled by this patch
* MOVPRFX must be followed by an instruction.
* MOVPRFX can only be followed by non-layout altering directives.
* MOVPRFX destination register MUST be used as the destination register in the
instruction at PC+4, and is not allowed to be used in any other position other than
destructive input. This includes registers that architecturally overlap. e.g. x1
should be treated as z1.
* MOVPRFX must be followed by a restricted set of SVE instructions.
* The size of the destination register of MOVPRFX must be equal to that of
the operation at PC+4.
* The predicate register and operation of MOVPRFX must match that of the instruction
at PC+4
* The predicated instruction at PC+4 must use the merging predicate.
* Architectural aliases and pseudo-instructions need to be supported as well.
* MOVPRFX cannot be the last instruction in a sequence
Any failure to adhere to any of these constrains will emit an assembly warning
and a disassembly note.
[1] https://developer.arm.com/docs/ddi0584/latest/arm-architecture-reference-manual-supplement-the-scalable-vector-extension-sve-for-armv8-a
include/
* opcode/aarch64.h (aarch64_inst): Remove.
(enum err_type): Add ERR_VFI.
(aarch64_is_destructive_by_operands): New.
(init_insn_sequence): New.
(aarch64_decode_insn): Remove param name.
opcodes/
* aarch64-opc.c (init_insn_block): New.
(verify_constraints, aarch64_is_destructive_by_operands): New.
* aarch64-opc.h (verify_constraints): New.
gas/
* config/tc-aarch64.c (output_operand_error_report): Order warnings.
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|
The current verifiers only take an instruction description and encoded value as
arguments. This was enough when the verifiers only needed to do simple checking
but it's insufficient for the purposes of validating instruction sequences.
This patch adds the required arguments and also a flag to allow a verifier to
distinguish between whether it's being run during encoding or decoding. It also
allows for errors and warnings to be returned by a verifier instead of a simple
pass/fail.
include/
* opcode/aarch64.h (struct aarch64_opcode): Expand verifiers to take
more arguments.
opcodes/
* aarch64-dis.c (aarch64_opcode_decode): Update verifier call.
* aarch64-opc.c (verify_ldpsw): Update arguments.
|
|
Previously the ERR_ values were defined as different constants, to make this a
bit more type safe and so they can be more easily re-used I'm changing them into
an actual enum and updating any usages.
include/
* opcode/aarch64.h (enum err_type): New.
(aarch64_decode_insn): Use it.
opcodes/
* aarch64-dis.c (ERR_OK, ERR_UND, ERR_UNP, ERR_NYI): Remove.
(aarch64_decode_insn, print_insn_aarch64_word): Use err_type.
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|
This patch introduces aarch64_instr_sequence which is a structure similar to IT
blocks on Arm in order to track instructions that introduce a constraint or
dependency on instruction 1..N positions away from the instruction that opened
the block.
The struct is also wired through to the locations that require it.
gas/
* config/tc-aarch64.c (now_instr_sequence):
(*insn_sequence, now_instr_sequence): New.
(output_operand_error_record, do_encode): Add insn_sequence.
(md_assemble): Update insn_sequence.
(try_to_encode_as_unscaled_ldst, fix_mov_imm_insn, fix_insn):
Pass insn_sequence.
* config/tc-aarch64.h (struct aarch64_segment_info_type):
Add insn_sequence.
include/
* opcode/aarch64.h (struct aarch64_instr_sequence): New.
(aarch64_opcode_encode): Use it.
opcodes/
* aarch64-asm.c (aarch64_opcode_encode): Add insn_sequence.
* aarch64-dis.c (insn_sequence): New.
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|
This patch series is to allow certain instructions such as the SVE MOVPRFX
instruction to apply a constraint/dependency on the instruction at PC+4.
This patch starts this off by marking which instructions impose the constraint
and which instructions must adhere to the constraint. This is done in a
generic way by extending the verifiers.
* The constraint F_SCAN indicates that an instruction opens a sequence and imposes
a constraint on an instructions following it. The length of the sequence depends
on the instruction itself and it handled in the verifier code.
* The C_SCAN_MOVPRFX flag is used to indicate which constrain the instruction is
checked against. An instruction with both F_SCAN and C_SCAN_MOVPRFX starts a
block for the C_SCAN_MOVPRFX instruction, and one with only C_SCAN_MOVPRFX must
adhere to a previous block constraint is applicable.
The SVE instructions in this list have been marked according to the SVE
specification[1].
[1] https://developer.arm.com/docs/ddi0584/latest/arm-architecture-reference-manual-supplement-the-scalable-vector-extension-sve-for-armv8-a
include/
* opcode/aarch64.h (struct aarch64_opcode): Add constraints,
extend flags field size.
(F_SCAN, C_SCAN_MOVPRFX, C_MAX_ELEM): New.
opcodes/
* aarch64-tbl.h (CORE_INSN, __FP_INSN, SIMD_INSN, CRYP_INSN, _CRC_INSN,
_LSE_INSN, _LOR_INSN, RDMA_INSN, FF16_INSN, SF16_INSN, V8_2_INSN,
_SVE_INSN, V8_3_INSN, CNUM_INSN, RCPC_INSN, SHA2_INSN, AES_INSN,
V8_4_INSN, SHA3_INSN, SM4_INSN, FP16_V8_2_INSN, DOT_INSN): Initialize
constraints.
(_SVE_INSNC): New.
(struct aarch64_opcode): (fjcvtzs, ldpsw, ldpsw, esb, psb): Initialize
constraints.
(movprfx): Change _SVE_INSN into _SVE_INSNC, add C_SCAN_MOVPRFX and
F_SCAN flags.
(msb, mul, neg, not, orr, rbit, revb, revh, revw, sabd, scvtf,
sdiv, sdivr, sdot, smax, smin, smulh, splice, sqadd, sqdecd, sqdech,
sqdecp, sqdecw, sqincd, sqinch, sqincp, sqincw, sqsub, sub, subr, sxtb,
sxth, sxtw, uabd, ucvtf, udiv, udivr, udot, umax, umin, umulh, uqadd,
uqdecd, uqdech, uqdecp, uqdecw, uqincd, uqinch, uqincp, uqincw, uqsub,
uxtb, uxth, uxtw, bic, eon, orn, mov, fmov): Change _SVE_INSN into _SVE_INSNC and add
C_SCAN_MOVPRFX and C_MAX_ELEM constraints.
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|
The RISC-V memory model has been ratified, and it includes an additional
fence: "fence.tso". This pseudo instruction extends one of the
previously reserved full fence patterns to be less restrictive, and
therefor will execute correctly on all existing microarchitectures.
Thus there is no reason to allow this instruction to be disabled (or
unconverted to a full fence), so it's just unconditionally allowed.
I've added a test case for GAS to check that "fence.tso" correctly
assembles on rv32i-based targets. I checked to see that "fence.tso"
appears in "gas.log", but that's the only testing I've done.
gas/ChangeLog
2018-10-02 Palmer Dabbelt <palmer@sifive.com>
* testsuite/gas/riscv/fence-tso.d: New file.
* testsuite/gas/riscv/fence-tso.s: Likewise.
include/ChangeLog
2018-10-02 Palmer Dabbelt <palmer@sifive.com>
* opcode/riscv-opc.h (MATCH_FENCE_TSO): New define.
(MASK_FENCE_TSO): Likewise.
opcodes/ChangeLog
2018-10-02 Palmer Dabbelt <palmer@sifive.com>
* riscv-opc.c (riscv_opcodes) <fence.tso>: New opcode.
|
|
2018-09-23 Sandra Loosemore <sandra@codesourcery.com>
opcodes/
* nios2-dis.c (nios2_print_insn_arg): Make sure signed conversions
are used when extracting signed fields and converting them to
potentially 64-bit types.
|
|
clang gives these errors:
In file included from /Users/simark/src/binutils-gdb/opcodes/csky-dis.c:30:
/Users/simark/src/binutils-gdb/opcodes/csky-opc.h:2330:8: error: missing field 'transfer' initializer [-Werror,-Wmissing-field-initializers]
{NULL}
^
/Users/simark/src/binutils-gdb/opcodes/csky-opc.h:8126:10: error: missing field 'transfer' initializer [-Werror,-Wmissing-field-initializers]
{NULL}
^
They go away when we Initialize all fields. I noticed there used to be some
files built with -Wno-missing-field-initializers, but it's not the case
anymore, since commit e7ae278d0474ab84ba3b1ee932a19e83616ddacc. There is still
a NO_WMISSING_FIELD_INITIALIZERS variable defined in the Makefile, but it's
unused, so I removed it to avoid further confusion.
opcodes/ChangeLog:
* Makefile.am: Remove NO_WMISSING_FIELD_INITIALIZERS.
* Makefile.in: Re-generate.
* aclocal.m4: Re-generate.
* configure: Re-generate.
* configure.ac: Remove check for -Wno-missing-field-initializers.
* csky-opc.h (csky_v1_opcodes): Initialize all fields of last element.
(csky_v2_opcodes): Likewise.
|
|
Fix build errors:
cc1: warnings being treated as errors
In file included from .../opcodes/arc-opc.c:2630:
.../opcodes/arc-nps400-tbl.h:38: warning: integer constant is too large for 'long' type
.../opcodes/arc-nps400-tbl.h:38: warning: integer constant is too large for 'long' type
.../opcodes/arc-nps400-tbl.h:41: warning: integer constant is too large for 'long' type
.../opcodes/arc-nps400-tbl.h:41: warning: integer constant is too large for 'long' type
[...]
.../opcodes/arc-nps400-tbl.h:712: warning: integer constant is too large for 'long' type
.../opcodes/arc-nps400-tbl.h:712: warning: integer constant is too large for 'long' type
.../opcodes/arc-nps400-tbl.h:715: warning: integer constant is too large for 'long' type
.../opcodes/arc-nps400-tbl.h:715: warning: integer constant is too large for 'long' type
make[4]: *** [arc-opc.lo] Error 1
and:
cc1: warnings being treated as errors
.../gas/config/tc-arc.c: In function 'md_number_to_chars_midend':
.../gas/config/tc-arc.c:802: warning: integer constant is too large for 'long' type
.../gas/config/tc-arc.c:810: warning: integer constant is too large for 'long' type
make[4]: *** [config/tc-arc.o] Error 1
observed with GCC 4.1.2 and presumably other C89 compilers with the
`arc-elf' and `arc-linux-gnu' targets, caused by the use of constants
the values of which are outside the range of the `int' type (or the
`long' type if it is of the same with). In the C89 language standard
such constants are not implicitly converted to a wider type and an
explicit suffix is required for such constants.
Add a `ull' suffix then as with such constants used in other ports.
gas/
* config/tc-arc.c (md_number_to_chars_midend): Append `ull' to
large constants.
opcodes/
* arc-nps400-tbl.h: Append `ull' to large constants throughout.
|
|
binutils on upstream!
We have not only removed all unsupported and obsolete code, but also supported lost of new features,
including better link-time relaxations and TLS implementations. Besides, the files generated by the
newly assembler and linker usually get higher performance and more optimized code size.
ld * emultempl/nds32elf.em (hyper_relax): New variable.
(nds32_elf_create_output_section_statements):
the parameters of bfd_elf32_nds32_set_target_option
(PARSE_AND_LIST_PROLOGUE, PARSE_AND_LIST_OPTIONS,
PARSE_AND_LIST_ARGS_CASES): Add new option --mhyper-relax.
* emultempl/nds32elf.em (nds32_elf_after_open): Updated.
* emultempl/nds32elf.em (tls_desc_trampoline): New variable.
* (nds32_elf_create_output_section_statements): Updated.
* (nds32_elf_after_parse): Disable relaxations when PIC is enable.
* (PARSE_AND_LIST_PROLOGUE, PARSE_AND_LIST_OPTIONS,
PARSE_AND_LIST_ARGS_CASES): Add new option --m[no-]tlsdesc-trampoline.
include * elf/nds32.h: Remove the unused target features.
* dis-asm.h (disassemble_init_nds32): Declared.
* elf/nds32.h (E_NDS32_NULL): Removed.
(E_NDS32_HAS_DSP_INST, E_NDS32_HAS_ZOL): New.
* opcode/nds32.h: Ident.
(N32_SUB6, INSN_LW): New macros.
(enum n32_opcodes): Updated.
* elf/nds32.h: Doc fixes.
* elf/nds32.h: Add R_NDS32_LSI.
* elf/nds32.h: Add new relocations for TLS.
gas * config/tc-nds32.c: Remove the unused target features.
(nds32_relax_relocs, md_pseudo_table, nds32_elf_record_fixup_exp,
nds32_set_elf_flags_by_insn, nds32_insert_relax_entry,
nds32_apply_fix): Likewise.
(nds32_no_ex9_begin): Removed.
* config/tc-nds32.c (add_mapping_symbol_for_align,
make_mapping_symbol, add_mapping_symbol): New functions.
* config/tc-nds32.h (enum mstate): New.
(nds32_segment_info_type): Likewise.
* configure.ac (--enable-dsp-ext, --enable-zol-ext): New options.
* config.in: Regenerated.
* configure: Regenerated.
* config/tc-nds32.c (nds32_dx_regs):
Set the value according to the configuration.
(nds32_perf_ext, nds32_perf_ext2, nds32_string_ext, nds32_audio_ext):
Likewise.
(nds32_dsp_ext): New variable. Set the value according to the
configuration.
(nds32_zol_ext): Likewise.
(asm_desc, nds32_pseudo_opcode_table): Make them static.
(nds32_set_elf_flags_by_insn): Updated.
(nds32_check_insn_available): Updated.
(nds32_str_tolower): New function.
* config/tc-nds32.c (relax_table): Updated.
(md_begin): Updated.
(md_assemble): Use XNEW macro to allocate space for `insn.info',
and then remember to free it.
(md_section_align): Cast (-1) to ValueT.
(nds32_get_align): Cast (~0U) to addressT.
(nds32_relax_branch_instructions): Updated.
(md_convert_frag): Add new local variable `final_r_type'.
(invalid_prev_frag): Add new bfd_boolean parameter `relax'.
All callers changed.
* config/tc-nds32.c (struct nds32_relocs_pattern): Add `insn' field.
(struct nds32_hint_map): Add `option_list' field.
(struct suffix_name, suffix_table): Remove the unused `pic' field.
(do_pseudo_b, do_pseudo_bal): Remove the suffix checking.
(do_pseudo_la_internal, do_pseudo_pushpopm): Indent.
(relax_hint_bias, relax_hint_id_current): New static variables.
(reset_bias, relax_hint_begin): New variables.
(nds_itoa): New function.
(CLEAN_REG, GET_OPCODE): New macros.
(struct relax_hint_id): New.
(nds32_relax_hint): For .relax_hint directive, we can use `begin'
and `end' to mark the relax pattern without giving exactly id number.
(nds32_elf_append_relax_relocs): Handle the case that the .relax_hint
directives are attached to pseudo instruction.
(nds32_elf_save_pseudo_pattern): Change the second parameter from
instruction's opcode to byte code.
(nds32_elf_build_relax_relation): Add new bfd_boolean parameter
`pseudo_hint'.
(nds32_lookup_pseudo_opcode): Fix the overflow issue.
(enum nds32_insn_type): Add N32_RELAX_ALU1 and N32_RELAX_16BIT.
(nds32_elf_record_fixup_exp, relax_ls_table, hint_map,
nds32_find_reloc_table, nds32_match_hint_insn, nds32_parse_name):
Updated.
* config/tc-nds32.h (MAX_RELAX_NUM): Extend it to 6.
(enum nds32_relax_hint_type): Merge NDS32_RELAX_HINT_LA and
NDS32_RELAX_HINT_LS into NDS32_RELAX_HINT_LALS. Add
NDS32_RELAX_HINT_LA_PLT, NDS32_RELAX_HINT_LA_GOT and
NDS32_RELAX_HINT_LA_GOTOFF.
* config/tc-nds32.h (relax_ls_table): Add floating load/store
to gp relax pattern.
(hint_map, nds32_find_reloc_table): Likewise.
* configure.ac: Define NDS32_LINUX_TOOLCHAIN.
* configure: Regenerated.
* config.in: Regenerated.
* config/tc-nds32.h (enum nds32_ramp): Updated.
(enum nds32_relax_hint_type): Likewise.
* config/tc-nds32.c: Include "errno.h" and "limits.h".
(relax_ls_table): Add TLS relax patterns.
(nds32_elf_append_relax_relocs): Attach BFD_RELOC_NDS32_GROUP on
each instructions of TLS patterns.
(nds32_elf_record_fixup_exp): Updated.
(nds32_apply_fix): Likewise.
(suffix_table): Add TLSDESC suffix.
binutils* testsuite/binutils-all/objcopy.exp: Set the unsupported reloc number
from 215 to 255 for NDS32.
bfd * elf32-nds32.c (nds32_elf_relax_loadstore):
Remove the unused target features.
(bfd_elf32_nds32_set_target_option): Remove the unused parameters.
(nds32_elf_relax_piclo12, nds32_elf_relax_letlslo12,
nds32_elf_relax_letlsadd, nds32_elf_relax_letlsls,
nds32_elf_relax_pltgot_suff, nds32_elf_relax_got_suff
nds32_elf_relax_gotoff_suff, calculate_plt_memory_address,
calculate_plt_offset, calculate_got_memory_address,
nds32_elf_check_dup_relocs): Removed.
All callers changed.
* elf32-nds32.h: Remove the unused macros and defines.
(elf_nds32_link_hash_table): Remove the unused variable.
(bfd_elf32_nds32_set_target_option): Update prototype.
(nds32_elf_ex9_init): Removed.
* elf32-nds32.c (nds32_convert_32_to_16): Updated.
* elf32-nds32.c (HOWTO2, HOWTO3): Define new HOWTO macros
to initialize array nds32_elf_howto_table in any order
without lots of EMPTY_HOWTO.
(nds32_reloc_map): Updated.
* reloc.c: Add BFD_RELOC_NDS32_LSI.
* bfd-in2.h: Regenerated.
* bfd/libbfd.h: Regenerated.
* elf32-nds32.c (nds32_elf_relax_howto_table): Add R_NDS32_LSI.
(nds32_reloc_map): Likewise.
(nds32_elf_relax_flsi): New function.
(nds32_elf_relax_section): Support floating load/store relaxation.
* elf32-nds32.c (NDS32_GUARD_SEC_P, elf32_nds32_local_gp_offset):
New macro.
(struct elf_nds32_link_hash_entry): New `offset_to_gp' field.
(struct elf_nds32_obj_tdata): New `offset_to_gp' and `hdr_size' fields.
(elf32_nds32_allocate_local_sym_info, nds32_elf_relax_guard,
nds32_elf_is_target_special_symbol, nds32_elf_maybe_function_sym):
New functions.
(nds32_info_to_howto_rel): Add BFD_ASSERT.
(bfd_elf32_bfd_reloc_type_table_lookup, nds32_elf_link_hash_newfunc,
nds32_elf_link_hash_table_create, nds32_elf_relocate_section,
nds32_elf_relax_loadstore, nds32_elf_relax_lo12, nds32_relax_adjust_label,
bfd_elf32_nds32_set_target_option, nds32_fag_mark_relax): Updated.
(nds32_elf_final_sda_base): Improve it to find the better gp value.
(insert_nds32_elf_blank): Must consider `len' when inserting blanks.
* elf32-nds32.h (bfd_elf32_nds32_set_target_option): Update prototype.
(struct elf_nds32_link_hash_table): Add new variable `hyper_relax'.
* elf32-nds32.c (elf32_nds32_allocate_dynrelocs): New function.
(create_got_section): Likewise.
(allocate_dynrelocs, nds32_elf_size_dynamic_sections,
nds32_elf_relocate_section, nds32_elf_finish_dynamic_symbol): Updated.
(nds32_elf_check_relocs): Fix the issue that the shared library may
has TEXTREL entry in the dynamic section.
(nds32_elf_create_dynamic_sections): Enable to call readonly_dynrelocs
since the TEXTREL issue is fixed in the nds32_elf_check_relocs.
(nds32_elf_finish_dynamic_sections): Update and add DT_RELASZ
dynamic entry.
(calculate_offset): Remove the unused parameter `pic_ext_target' and
related codes.
All callers changed.
(elf_backend_dtrel_excludes_plt): Disable it temporarily since it
will cause some errors for our test cases.
* elf32-nds32.c (nds32_elf_merge_private_bfd_data): Allow to link the
generic object.
* reloc.c: Add TLS relocations.
* libbfd.h: Regenerated.
* bfd-in2.h: Regenerated.
* elf32-nds32.h (struct section_id_list_t): New.
(elf32_nds32_lookup_section_id, elf32_nds32_check_relax_group,
elf32_nds32_unify_relax_group, nds32_elf_unify_tls_model):
New prototypes.
(elf32_nds32_compute_jump_table_size, elf32_nds32_local_tlsdesc_gotent):
New macro.
(nds32_insertion_sort, bfd_elf32_nds32_set_target_option,
elf_nds32_link_hash_table): Updated.
* elf32-nds32.c (enum elf_nds32_tls_type): New.
(struct elf32_nds32_relax_group_t, struct relax_group_list_t): New.
(elf32_nds32_add_dynreloc, patch_tls_desc_to_ie, get_tls_type,
fls, ones32, list_insert, list_insert_sibling, dump_chain,
elf32_nds32_check_relax_group, elf32_nds32_lookup_section_id,
elf32_nds32_unify_relax_group, nds32_elf_unify_tls_model): New functions.
(elf_nds32_obj_tdata): Add new fields.
(elf32_nds32_relax_group_ptr, nds32_elf_local_tlsdesc_gotent): New macros.
(nds32_elf_howto_table): Add TLS relocations.
(nds32_reloc_map): Likewise.
(nds32_elf_copy_indirect_symbol, nds32_elf_size_dynamic_sections,
nds32_elf_finish_dynamic_symbol, elf32_nds32_allocate_local_sym_info,
nds32_elf_relocate_section, bfd_elf32_nds32_set_target_option,
nds32_elf_check_relocs, allocate_dynrelocs): Updated.
(nds32_elf_relax_section): Call nds32_elf_unify_tls_model.
(dtpoff_base): Rename it to `gottpof' and then update it.
opcodes * nds32-asm.c (operand_fields): Remove the unused fields.
(nds32_opcodes): Remove the unused instructions.
* nds32-dis.c (nds32_ex9_info): Removed.
(nds32_parse_opcode): Updated.
(print_insn_nds32): Likewise.
* nds32-asm.c (config.h, stdlib.h, string.h): New includes.
(LEX_SET_FIELD, LEX_GET_FIELD): Update defines.
(nds32_asm_init, build_operand_hash_table, build_keyword_hash_table,
build_opcode_hash_table): New functions.
(nds32_keyword_table, nds32_keyword_count_table, nds32_field_table,
nds32_opcode_table): New.
(hw_ktabs): Declare it to a pointer rather than an array.
(build_hash_table): Removed.
* nds32-asm.h (enum): Add SYN_INPUT, SYN_OUTPUT, SYN_LOPT,
SYN_ROPT and upadte HW_GPR and HW_INT.
* nds32-dis.c (keywords): Remove const.
(match_field): New function.
(nds32_parse_opcode): Updated.
* disassemble.c (disassemble_init_for_target):
Add disassemble_init_nds32.
* nds32-dis.c (eum map_type): New.
(nds32_private_data): Likewise.
(get_mapping_symbol_type, is_mapping_symbol, nds32_symbol_is_valid,
nds32_add_opcode_hash_table, disassemble_init_nds32): New functions.
(print_insn_nds32): Updated.
* nds32-asm.c (parse_aext_reg): Add new parameter.
(parse_re, parse_re2, parse_aext_reg): Only reduced registers
are allowed to use.
All callers changed.
* nds32-asm.c (keyword_usr, keyword_sr): Updated.
(operand_fields): Add new fields.
(nds32_opcodes): Add new instructions.
(keyword_aridxi_mx): New keyword.
* nds32-asm.h (enum): Add NASM_ATTR_DSP_ISAEXT, HW_AEXT_ARIDXI_MX
and NASM_ATTR_ZOL.
(ALU2_1, ALU2_2, ALU2_3): New macros.
* nds32-dis.c (nds32_filter_unknown_insn): Updated.
|
|
2018-09-17 Kito Cheng <kito@andestech.com>
gas/
* testsuite/gas/riscv/bge.d: New.
* testsuite/gas/riscv/bge.s: Likewise.
opcodes/
* riscv-opc.c (riscv_opcodes): Adjust the order of ble and
bleu.
|
|
EVEX "VMOVD xmm1, r32/m32", "VMOVD r32/m32, xmm2", "VMOVQ xmm1, r64/m64",
"VMOVD r64/m64, xmm2", "VMOVQ xmm1, xmm2/m64" and "VMOVQ xmm1/m64, xmm2"
can only be encoded with EVEX.128. Set EVex=2 on EVEX.128 only vmovd and
vmovq.
gas/
PR gas/23670
* testsuite/gas/i386/evex-lig-2.d: New file.
* testsuite/gas/i386/evex-lig-2.s: Likewise.
* testsuite/gas/i386/x86-64-evex-lig-2.d: Likewise.
* testsuite/gas/i386/x86-64-evex-lig-2.s: Likewise.
* testsuite/gas/i386/i386.exp: Run evex-lig-2 and
x86-64-evex-lig-2.
opcodes/
PR gas/23670
* i386-dis-evex.h (evex_table): Use EVEX_LEN_0F6E_P_2,
EVEX_LEN_0F7E_P_1, EVEX_LEN_0F7E_P_2 and EVEX_LEN_0FD6_P_2.
(EVEX_LEN_0F6E_P_2): New EVEX_LEN_TABLE entry.
(EVEX_LEN_0F7E_P_1): Likewise.
(EVEX_LEN_0F7E_P_2): Likewise.
(EVEX_LEN_0FD6_P_2): Likewise.
* i386-dis.c (USE_EVEX_LEN_TABLE): New.
(EVEX_LEN_TABLE): Likewise.
(EVEX_LEN_0F6E_P_2): New enum.
(EVEX_LEN_0F7E_P_1): Likewise.
(EVEX_LEN_0F7E_P_2): Likewise.
(EVEX_LEN_0FD6_P_2): Likewise.
(evex_len_table): New.
(get_valid_dis386): Handle USE_EVEX_LEN_TABLE.
* i386-opc.tbl: Set EVex=2 on EVEX.128 only vmovd and vmovq.
* i386-tbl.h: Regenerated.
|
|
AVX "VMOVD xmm1, r32/m32", "VMOVD r32/m32, xmm2", "VMOVQ xmm1, r64/m64"
and "VMOVD r64/m64, xmm2" can only be encoded with VEX.128. Set Vex=1
on VEX.128 only vmovd and vmovq.
gas/
PR gas/23665
* testsuite/gas/i386/avx-scalar.s: Remove vmovq and vmovd tests.
* testsuite/gas/i386/x86-64-avx-scalar.s: Likewise.
* testsuite/gas/i386/avx-scalar-intel.d: Updated.
* testsuite/gas/i386/avx-scalar.d: Likewise.
* testsuite/gas/i386/x86-64-avx-scalar-intel.d: Likewise.
* testsuite/gas/i386/x86-64-avx-scalar.d: Likewise.
* testsuite/gas/i386/i386.exp: Run avx-scalar2 and
x86-64-avx-scalar2.
* testsuite/gas/i386/avx-scalar-2.d: New file.
* testsuite/gas/i386/avx-scalar-2.s: Likewise.
* testsuite/gas/i386/x86-64-avx-scalar-2.d: Likewise.
* testsuite/gas/i386/x86-64-avx-scalar-2.s: Likewise.
opcodes/
PR gas/23665
* i386-dis.c (vex_len_table): Update VEX_LEN_0F6E_P_2 and
VEX_LEN_0F7E_P_2 entries.
* i386-opc.tbl: Set Vex=1 on VEX.128 only vmovd and vmovq.
* i386-tbl.h: Regenerated.
|
|
The VEX.W bit is ignored by some VEX instructions, aka WIG instructions.
Update x86 disassembler to handle VEX WIG instructions.
* i386-dis.c (VZERO_Fixup): Removed.
(VZERO): Likewise.
(VEX_LEN_0F10_P_1): Likewise.
(VEX_LEN_0F10_P_3): Likewise.
(VEX_LEN_0F11_P_1): Likewise.
(VEX_LEN_0F11_P_3): Likewise.
(VEX_LEN_0F2E_P_0): Likewise.
(VEX_LEN_0F2E_P_2): Likewise.
(VEX_LEN_0F2F_P_0): Likewise.
(VEX_LEN_0F2F_P_2): Likewise.
(VEX_LEN_0F51_P_1): Likewise.
(VEX_LEN_0F51_P_3): Likewise.
(VEX_LEN_0F52_P_1): Likewise.
(VEX_LEN_0F53_P_1): Likewise.
(VEX_LEN_0F58_P_1): Likewise.
(VEX_LEN_0F58_P_3): Likewise.
(VEX_LEN_0F59_P_1): Likewise.
(VEX_LEN_0F59_P_3): Likewise.
(VEX_LEN_0F5A_P_1): Likewise.
(VEX_LEN_0F5A_P_3): Likewise.
(VEX_LEN_0F5C_P_1): Likewise.
(VEX_LEN_0F5C_P_3): Likewise.
(VEX_LEN_0F5D_P_1): Likewise.
(VEX_LEN_0F5D_P_3): Likewise.
(VEX_LEN_0F5E_P_1): Likewise.
(VEX_LEN_0F5E_P_3): Likewise.
(VEX_LEN_0F5F_P_1): Likewise.
(VEX_LEN_0F5F_P_3): Likewise.
(VEX_LEN_0FC2_P_1): Likewise.
(VEX_LEN_0FC2_P_3): Likewise.
(VEX_LEN_0F3A0A_P_2): Likewise.
(VEX_LEN_0F3A0B_P_2): Likewise.
(VEX_W_0F10_P_0): Likewise.
(VEX_W_0F10_P_1): Likewise.
(VEX_W_0F10_P_2): Likewise.
(VEX_W_0F10_P_3): Likewise.
(VEX_W_0F11_P_0): Likewise.
(VEX_W_0F11_P_1): Likewise.
(VEX_W_0F11_P_2): Likewise.
(VEX_W_0F11_P_3): Likewise.
(VEX_W_0F12_P_0_M_0): Likewise.
(VEX_W_0F12_P_0_M_1): Likewise.
(VEX_W_0F12_P_1): Likewise.
(VEX_W_0F12_P_2): Likewise.
(VEX_W_0F12_P_3): Likewise.
(VEX_W_0F13_M_0): Likewise.
(VEX_W_0F14): Likewise.
(VEX_W_0F15): Likewise.
(VEX_W_0F16_P_0_M_0): Likewise.
(VEX_W_0F16_P_0_M_1): Likewise.
(VEX_W_0F16_P_1): Likewise.
(VEX_W_0F16_P_2): Likewise.
(VEX_W_0F17_M_0): Likewise.
(VEX_W_0F28): Likewise.
(VEX_W_0F29): Likewise.
(VEX_W_0F2B_M_0): Likewise.
(VEX_W_0F2E_P_0): Likewise.
(VEX_W_0F2E_P_2): Likewise.
(VEX_W_0F2F_P_0): Likewise.
(VEX_W_0F2F_P_2): Likewise.
(VEX_W_0F50_M_0): Likewise.
(VEX_W_0F51_P_0): Likewise.
(VEX_W_0F51_P_1): Likewise.
(VEX_W_0F51_P_2): Likewise.
(VEX_W_0F51_P_3): Likewise.
(VEX_W_0F52_P_0): Likewise.
(VEX_W_0F52_P_1): Likewise.
(VEX_W_0F53_P_0): Likewise.
(VEX_W_0F53_P_1): Likewise.
(VEX_W_0F58_P_0): Likewise.
(VEX_W_0F58_P_1): Likewise.
(VEX_W_0F58_P_2): Likewise.
(VEX_W_0F58_P_3): Likewise.
(VEX_W_0F59_P_0): Likewise.
(VEX_W_0F59_P_1): Likewise.
(VEX_W_0F59_P_2): Likewise.
(VEX_W_0F59_P_3): Likewise.
(VEX_W_0F5A_P_0): Likewise.
(VEX_W_0F5A_P_1): Likewise.
(VEX_W_0F5A_P_3): Likewise.
(VEX_W_0F5B_P_0): Likewise.
(VEX_W_0F5B_P_1): Likewise.
(VEX_W_0F5B_P_2): Likewise.
(VEX_W_0F5C_P_0): Likewise.
(VEX_W_0F5C_P_1): Likewise.
(VEX_W_0F5C_P_2): Likewise.
(VEX_W_0F5C_P_3): Likewise.
(VEX_W_0F5D_P_0): Likewise.
(VEX_W_0F5D_P_1): Likewise.
(VEX_W_0F5D_P_2): Likewise.
(VEX_W_0F5D_P_3): Likewise.
(VEX_W_0F5E_P_0): Likewise.
(VEX_W_0F5E_P_1): Likewise.
(VEX_W_0F5E_P_2): Likewise.
(VEX_W_0F5E_P_3): Likewise.
(VEX_W_0F5F_P_0): Likewise.
(VEX_W_0F5F_P_1): Likewise.
(VEX_W_0F5F_P_2): Likewise.
(VEX_W_0F5F_P_3): Likewise.
(VEX_W_0F60_P_2): Likewise.
(VEX_W_0F61_P_2): Likewise.
(VEX_W_0F62_P_2): Likewise.
(VEX_W_0F63_P_2): Likewise.
(VEX_W_0F64_P_2): Likewise.
(VEX_W_0F65_P_2): Likewise.
(VEX_W_0F66_P_2): Likewise.
(VEX_W_0F67_P_2): Likewise.
(VEX_W_0F68_P_2): Likewise.
(VEX_W_0F69_P_2): Likewise.
(VEX_W_0F6A_P_2): Likewise.
(VEX_W_0F6B_P_2): Likewise.
(VEX_W_0F6C_P_2): Likewise.
(VEX_W_0F6D_P_2): Likewise.
(VEX_W_0F6F_P_1): Likewise.
(VEX_W_0F6F_P_2): Likewise.
(VEX_W_0F70_P_1): Likewise.
(VEX_W_0F70_P_2): Likewise.
(VEX_W_0F70_P_3): Likewise.
(VEX_W_0F71_R_2_P_2): Likewise.
(VEX_W_0F71_R_4_P_2): Likewise.
(VEX_W_0F71_R_6_P_2): Likewise.
(VEX_W_0F72_R_2_P_2): Likewise.
(VEX_W_0F72_R_4_P_2): Likewise.
(VEX_W_0F72_R_6_P_2): Likewise.
(VEX_W_0F73_R_2_P_2): Likewise.
(VEX_W_0F73_R_3_P_2): Likewise.
(VEX_W_0F73_R_6_P_2): Likewise.
(VEX_W_0F73_R_7_P_2): Likewise.
(VEX_W_0F74_P_2): Likewise.
(VEX_W_0F75_P_2): Likewise.
(VEX_W_0F76_P_2): Likewise.
(VEX_W_0F77_P_0): Likewise.
(VEX_W_0F7C_P_2): Likewise.
(VEX_W_0F7C_P_3): Likewise.
(VEX_W_0F7D_P_2): Likewise.
(VEX_W_0F7D_P_3): Likewise.
(VEX_W_0F7E_P_1): Likewise.
(VEX_W_0F7F_P_1): Likewise.
(VEX_W_0F7F_P_2): Likewise.
(VEX_W_0FAE_R_2_M_0): Likewise.
(VEX_W_0FAE_R_3_M_0): Likewise.
(VEX_W_0FC2_P_0): Likewise.
(VEX_W_0FC2_P_1): Likewise.
(VEX_W_0FC2_P_2): Likewise.
(VEX_W_0FC2_P_3): Likewise.
(VEX_W_0FD0_P_2): Likewise.
(VEX_W_0FD0_P_3): Likewise.
(VEX_W_0FD1_P_2): Likewise.
(VEX_W_0FD2_P_2): Likewise.
(VEX_W_0FD3_P_2): Likewise.
(VEX_W_0FD4_P_2): Likewise.
(VEX_W_0FD5_P_2): Likewise.
(VEX_W_0FD6_P_2): Likewise.
(VEX_W_0FD7_P_2_M_1): Likewise.
(VEX_W_0FD8_P_2): Likewise.
(VEX_W_0FD9_P_2): Likewise.
(VEX_W_0FDA_P_2): Likewise.
(VEX_W_0FDB_P_2): Likewise.
(VEX_W_0FDC_P_2): Likewise.
(VEX_W_0FDD_P_2): Likewise.
(VEX_W_0FDE_P_2): Likewise.
(VEX_W_0FDF_P_2): Likewise.
(VEX_W_0FE0_P_2): Likewise.
(VEX_W_0FE1_P_2): Likewise.
(VEX_W_0FE2_P_2): Likewise.
(VEX_W_0FE3_P_2): Likewise.
(VEX_W_0FE4_P_2): Likewise.
(VEX_W_0FE5_P_2): Likewise.
(VEX_W_0FE6_P_1): Likewise.
(VEX_W_0FE6_P_2): Likewise.
(VEX_W_0FE6_P_3): Likewise.
(VEX_W_0FE7_P_2_M_0): Likewise.
(VEX_W_0FE8_P_2): Likewise.
(VEX_W_0FE9_P_2): Likewise.
(VEX_W_0FEA_P_2): Likewise.
(VEX_W_0FEB_P_2): Likewise.
(VEX_W_0FEC_P_2): Likewise.
(VEX_W_0FED_P_2): Likewise.
(VEX_W_0FEE_P_2): Likewise.
(VEX_W_0FEF_P_2): Likewise.
(VEX_W_0FF0_P_3_M_0): Likewise.
(VEX_W_0FF1_P_2): Likewise.
(VEX_W_0FF2_P_2): Likewise.
(VEX_W_0FF3_P_2): Likewise.
(VEX_W_0FF4_P_2): Likewise.
(VEX_W_0FF5_P_2): Likewise.
(VEX_W_0FF6_P_2): Likewise.
(VEX_W_0FF7_P_2): Likewise.
(VEX_W_0FF8_P_2): Likewise.
(VEX_W_0FF9_P_2): Likewise.
(VEX_W_0FFA_P_2): Likewise.
(VEX_W_0FFB_P_2): Likewise.
(VEX_W_0FFC_P_2): Likewise.
(VEX_W_0FFD_P_2): Likewise.
(VEX_W_0FFE_P_2): Likewise.
(VEX_W_0F3800_P_2): Likewise.
(VEX_W_0F3801_P_2): Likewise.
(VEX_W_0F3802_P_2): Likewise.
(VEX_W_0F3803_P_2): Likewise.
(VEX_W_0F3804_P_2): Likewise.
(VEX_W_0F3805_P_2): Likewise.
(VEX_W_0F3806_P_2): Likewise.
(VEX_W_0F3807_P_2): Likewise.
(VEX_W_0F3808_P_2): Likewise.
(VEX_W_0F3809_P_2): Likewise.
(VEX_W_0F380A_P_2): Likewise.
(VEX_W_0F380B_P_2): Likewise.
(VEX_W_0F3817_P_2): Likewise.
(VEX_W_0F381C_P_2): Likewise.
(VEX_W_0F381D_P_2): Likewise.
(VEX_W_0F381E_P_2): Likewise.
(VEX_W_0F3820_P_2): Likewise.
(VEX_W_0F3821_P_2): Likewise.
(VEX_W_0F3822_P_2): Likewise.
(VEX_W_0F3823_P_2): Likewise.
(VEX_W_0F3824_P_2): Likewise.
(VEX_W_0F3825_P_2): Likewise.
(VEX_W_0F3828_P_2): Likewise.
(VEX_W_0F3829_P_2): Likewise.
(VEX_W_0F382A_P_2_M_0): Likewise.
(VEX_W_0F382B_P_2): Likewise.
(VEX_W_0F3830_P_2): Likewise.
(VEX_W_0F3831_P_2): Likewise.
(VEX_W_0F3832_P_2): Likewise.
(VEX_W_0F3833_P_2): Likewise.
(VEX_W_0F3834_P_2): Likewise.
(VEX_W_0F3835_P_2): Likewise.
(VEX_W_0F3837_P_2): Likewise.
(VEX_W_0F3838_P_2): Likewise.
(VEX_W_0F3839_P_2): Likewise.
(VEX_W_0F383A_P_2): Likewise.
(VEX_W_0F383B_P_2): Likewise.
(VEX_W_0F383C_P_2): Likewise.
(VEX_W_0F383D_P_2): Likewise.
(VEX_W_0F383E_P_2): Likewise.
(VEX_W_0F383F_P_2): Likewise.
(VEX_W_0F3840_P_2): Likewise.
(VEX_W_0F3841_P_2): Likewise.
(VEX_W_0F38DB_P_2): Likewise.
(VEX_W_0F3A08_P_2): Likewise.
(VEX_W_0F3A09_P_2): Likewise.
(VEX_W_0F3A0A_P_2): Likewise.
(VEX_W_0F3A0B_P_2): Likewise.
(VEX_W_0F3A0C_P_2): Likewise.
(VEX_W_0F3A0D_P_2): Likewise.
(VEX_W_0F3A0E_P_2): Likewise.
(VEX_W_0F3A0F_P_2): Likewise.
(VEX_W_0F3A21_P_2): Likewise.
(VEX_W_0F3A40_P_2): Likewise.
(VEX_W_0F3A41_P_2): Likewise.
(VEX_W_0F3A42_P_2): Likewise.
(VEX_W_0F3A62_P_2): Likewise.
(VEX_W_0F3A63_P_2): Likewise.
(VEX_W_0F3ADF_P_2): Likewise.
(VEX_LEN_0F77_P_0): New.
(prefix_table): Update PREFIX_VEX_0F10, PREFIX_VEX_0F11,
PREFIX_VEX_0F12, PREFIX_VEX_0F16, PREFIX_VEX_0F2E,
PREFIX_VEX_0F2F, PREFIX_VEX_0F51, PREFIX_VEX_0F52,
PREFIX_VEX_0F53, PREFIX_VEX_0F58, PREFIX_VEX_0F59,
PREFIX_VEX_0F5A, PREFIX_VEX_0F5B, PREFIX_VEX_0F5C,
PREFIX_VEX_0F5D, PREFIX_VEX_0F5E, PREFIX_VEX_0F5F,
PREFIX_VEX_0F60, PREFIX_VEX_0F61, PREFIX_VEX_0F62,
PREFIX_VEX_0F63, PREFIX_VEX_0F64, PREFIX_VEX_0F65,
PREFIX_VEX_0F66, PREFIX_VEX_0F67, PREFIX_VEX_0F68,
PREFIX_VEX_0F69, PREFIX_VEX_0F6A, PREFIX_VEX_0F6B,
PREFIX_VEX_0F6C, PREFIX_VEX_0F6D, PREFIX_VEX_0F6F,
PREFIX_VEX_0F70, PREFIX_VEX_0F71_REG_2, PREFIX_VEX_0F71_REG_4,
PREFIX_VEX_0F71_REG_6, PREFIX_VEX_0F72_REG_4,
PREFIX_VEX_0F72_REG_6, PREFIX_VEX_0F73_REG_2,
PREFIX_VEX_0F73_REG_3, PREFIX_VEX_0F73_REG_6,
PREFIX_VEX_0F73_REG_7, PREFIX_VEX_0F74, PREFIX_VEX_0F75,
PREFIX_VEX_0F76, PREFIX_VEX_0F77, PREFIX_VEX_0F7C,
PREFIX_VEX_0F7D, PREFIX_VEX_0F7F, PREFIX_VEX_0FC2,
PREFIX_VEX_0FD0, PREFIX_VEX_0FD1, PREFIX_VEX_0FD2,
PREFIX_VEX_0FD3, PREFIX_VEX_0FD4, PREFIX_VEX_0FD5,
PREFIX_VEX_0FD8, PREFIX_VEX_0FD9, PREFIX_VEX_0FDA,
PREFIX_VEX_0FDC, PREFIX_VEX_0FDD, PREFIX_VEX_0FDE,
PREFIX_VEX_0FDF, PREFIX_VEX_0FE0, PREFIX_VEX_0FE1,
PREFIX_VEX_0FE2, PREFIX_VEX_0FE3, PREFIX_VEX_0FE4,
PREFIX_VEX_0FE5, PREFIX_VEX_0FE6, PREFIX_VEX_0FE8,
PREFIX_VEX_0FE9, PREFIX_VEX_0FEA, PREFIX_VEX_0FEB,
PREFIX_VEX_0FEC, PREFIX_VEX_0FED, PREFIX_VEX_0FEE,
PREFIX_VEX_0FEF, PREFIX_VEX_0FF1. PREFIX_VEX_0FF2,
PREFIX_VEX_0FF3, PREFIX_VEX_0FF4, PREFIX_VEX_0FF5,
PREFIX_VEX_0FF6, PREFIX_VEX_0FF8, PREFIX_VEX_0FF9,
PREFIX_VEX_0FFA, PREFIX_VEX_0FFB, PREFIX_VEX_0FFC,
PREFIX_VEX_0FFD, PREFIX_VEX_0FFE, PREFIX_VEX_0F3800,
PREFIX_VEX_0F3801, PREFIX_VEX_0F3802, PREFIX_VEX_0F3803,
PREFIX_VEX_0F3804, PREFIX_VEX_0F3805, PREFIX_VEX_0F3806,
PREFIX_VEX_0F3807, PREFIX_VEX_0F3808, PREFIX_VEX_0F3809,
PREFIX_VEX_0F380A, PREFIX_VEX_0F380B, PREFIX_VEX_0F3817,
PREFIX_VEX_0F381C, PREFIX_VEX_0F381D, PREFIX_VEX_0F381E,
PREFIX_VEX_0F3820, PREFIX_VEX_0F3821, PREFIX_VEX_0F3822,
PREFIX_VEX_0F3823, PREFIX_VEX_0F3824, PREFIX_VEX_0F3825,
PREFIX_VEX_0F3828, PREFIX_VEX_0F3829, PREFIX_VEX_0F382B,
PREFIX_VEX_0F382C, PREFIX_VEX_0F3831, PREFIX_VEX_0F3832,
PREFIX_VEX_0F3833, PREFIX_VEX_0F3834, PREFIX_VEX_0F3835,
PREFIX_VEX_0F3837, PREFIX_VEX_0F3838, PREFIX_VEX_0F3839,
PREFIX_VEX_0F383A, PREFIX_VEX_0F383B, PREFIX_VEX_0F383C,
PREFIX_VEX_0F383D, PREFIX_VEX_0F383E, PREFIX_VEX_0F383F,
PREFIX_VEX_0F3840, PREFIX_VEX_0F3A08, PREFIX_VEX_0F3A09,
PREFIX_VEX_0F3A0A, PREFIX_VEX_0F3A0B, PREFIX_VEX_0F3A0C,
PREFIX_VEX_0F3A0D, PREFIX_VEX_0F3A0E, PREFIX_VEX_0F3A0F,
PREFIX_VEX_0F3A40 and PREFIX_VEX_0F3A42 entries.
(vex_table): Update VEX 0F28 and 0F29 entries.
(vex_len_table): Update VEX_LEN_0F10_P_1, VEX_LEN_0F10_P_3,
VEX_LEN_0F11_P_1, VEX_LEN_0F11_P_3, VEX_LEN_0F2E_P_0,
VEX_LEN_0F2E_P_2, VEX_LEN_0F2F_P_0, VEX_LEN_0F2F_P_2,
VEX_LEN_0F51_P_1, VEX_LEN_0F51_P_3, VEX_LEN_0F52_P_1,
VEX_LEN_0F53_P_1, VEX_LEN_0F58_P_1, VEX_LEN_0F58_P_3,
VEX_LEN_0F59_P_1, VEX_LEN_0F59_P_3, VEX_LEN_0F5A_P_1,
VEX_LEN_0F5A_P_3, VEX_LEN_0F5C_P_1, VEX_LEN_0F5C_P_3,
VEX_LEN_0F5D_P_1, VEX_LEN_0F5D_P_3, VEX_LEN_0F5E_P_1,
VEX_LEN_0F5E_P_3, VEX_LEN_0F5F_P_1, VEX_LEN_0F5F_P_3,
VEX_LEN_0FC2_P_1, VEX_LEN_0FC2_P_3, VEX_LEN_0F3A0A_P_2 and
VEX_LEN_0F3A0B_P_2 entries.
(vex_w_table): Remove VEX_W_0F10_P_0, VEX_W_0F10_P_1,
VEX_W_0F10_P_2, VEX_W_0F10_P_3, VEX_W_0F11_P_0, VEX_W_0F11_P_1,
VEX_W_0F11_P_2, VEX_W_0F11_P_3, VEX_W_0F12_P_0_M_0,
VEX_W_0F12_P_0_M_1, VEX_W_0F12_P_1, VEX_W_0F12_P_2,
VEX_W_0F12_P_3, VEX_W_0F13_M_0, VEX_W_0F14, VEX_W_0F15,
VEX_W_0F16_P_0_M_0, VEX_W_0F16_P_0_M_1, VEX_W_0F16_P_1,
VEX_W_0F16_P_2, VEX_W_0F17_M_0, VEX_W_0F28, VEX_W_0F29,
VEX_W_0F2B_M_0, VEX_W_0F2E_P_0, VEX_W_0F2E_P_2, VEX_W_0F2F_P_0,
VEX_W_0F2F_P_2, VEX_W_0F50_M_0, VEX_W_0F51_P_0, VEX_W_0F51_P_1,
VEX_W_0F51_P_2, VEX_W_0F51_P_3, VEX_W_0F52_P_0, VEX_W_0F52_P_1,
VEX_W_0F53_P_0, VEX_W_0F53_P_1, VEX_W_0F58_P_0, VEX_W_0F58_P_1,
VEX_W_0F58_P_2, VEX_W_0F58_P_3, VEX_W_0F59_P_0, VEX_W_0F59_P_1,
VEX_W_0F59_P_2, VEX_W_0F59_P_3, VEX_W_0F5A_P_0, VEX_W_0F5A_P_1,
VEX_W_0F5A_P_3, VEX_W_0F5B_P_0, VEX_W_0F5B_P_1, VEX_W_0F5B_P_2,
VEX_W_0F5C_P_0, VEX_W_0F5C_P_1, VEX_W_0F5C_P_2, VEX_W_0F5C_P_3,
VEX_W_0F5D_P_0, VEX_W_0F5D_P_1, VEX_W_0F5D_P_2, VEX_W_0F5D_P_3,
VEX_W_0F5E_P_0, VEX_W_0F5E_P_1, VEX_W_0F5E_P_2, VEX_W_0F5E_P_3,
VEX_W_0F5F_P_0, VEX_W_0F5F_P_1, VEX_W_0F5F_P_2, VEX_W_0F5F_P_3,
VEX_W_0F60_P_2, VEX_W_0F61_P_2, VEX_W_0F62_P_2, VEX_W_0F63_P_2,
VEX_W_0F64_P_2, VEX_W_0F65_P_2, VEX_W_0F66_P_2, VEX_W_0F67_P_2,
VEX_W_0F68_P_2, VEX_W_0F69_P_2, VEX_W_0F6A_P_2, VEX_W_0F6B_P_2,
VEX_W_0F6C_P_2, VEX_W_0F6D_P_2, VEX_W_0F6F_P_1, VEX_W_0F6F_P_2,
VEX_W_0F70_P_1, VEX_W_0F70_P_2, VEX_W_0F70_P_3,
VEX_W_0F71_R_2_P_2, VEX_W_0F71_R_4_P_2, VEX_W_0F71_R_6_P_2,
VEX_W_0F72_R_2_P_2, VEX_W_0F72_R_4_P_2, VEX_W_0F72_R_6_P_2,
VEX_W_0F73_R_2_P_2, VEX_W_0F73_R_3_P_2, VEX_W_0F73_R_6_P_2,
VEX_W_0F73_R_7_P_2, VEX_W_0F74_P_2, VEX_W_0F75_P_2,
VEX_W_0F76_P_2, VEX_W_0F77_P_0, VEX_W_0F7C_P_2, VEX_W_0F7C_P_3,
VEX_W_0F7D_P_2, VEX_W_0F7D_P_3, VEX_W_0F7E_P_1, VEX_W_0F7F_P_1,
VEX_W_0F7F_P_2, VEX_W_0FAE_R_2_M_0, VEX_W_0FAE_R_3_M_0,
VEX_W_0FC2_P_0, VEX_W_0FC2_P_1, VEX_W_0FC2_P_2, VEX_W_0FC2_P_3,
VEX_W_0FD0_P_2, VEX_W_0FD0_P_3, VEX_W_0FD1_P_2, VEX_W_0FD2_P_2,
VEX_W_0FD3_P_2, VEX_W_0FD4_P_2, VEX_W_0FD5_P_2, VEX_W_0FD6_P_2,
VEX_W_0FD7_P_2_M_1, VEX_W_0FD8_P_2, VEX_W_0FD9_P_2,
VEX_W_0FDA_P_2, VEX_W_0FDB_P_2, VEX_W_0FDC_P_2, VEX_W_0FDD_P_2,
VEX_W_0FDE_P_2, VEX_W_0FDF_P_2, VEX_W_0FE0_P_2, VEX_W_0FE1_P_2,
VEX_W_0FE2_P_2, VEX_W_0FE3_P_2, VEX_W_0FE4_P_2, VEX_W_0FE5_P_2,
VEX_W_0FE6_P_1, VEX_W_0FE6_P_2, VEX_W_0FE6_P_3,
VEX_W_0FE7_P_2_M_0, VEX_W_0FE8_P_2, VEX_W_0FE9_P_2,
VEX_W_0FEA_P_2, VEX_W_0FEB_P_2, VEX_W_0FEC_P_2, VEX_W_0FED_P_2,
VEX_W_0FEE_P_2, VEX_W_0FEF_P_2, VEX_W_0FF0_P_3_M_0,
VEX_W_0FF1_P_2, VEX_W_0FF2_P_2, VEX_W_0FF3_P_2, VEX_W_0FF4_P_2,
VEX_W_0FF5_P_2, VEX_W_0FF6_P_2, VEX_W_0FF7_P_2, VEX_W_0FF8_P_2,
VEX_W_0FF9_P_2, VEX_W_0FFA_P_2, VEX_W_0FFB_P_2, VEX_W_0FFC_P_2,
VEX_W_0FFD_P_2, VEX_W_0FFE_P_2, VEX_W_0F3800_P_2,
VEX_W_0F3801_P_2, VEX_W_0F3802_P_2, VEX_W_0F3803_P_2,
VEX_W_0F3804_P_2, VEX_W_0F3805_P_2, VEX_W_0F3806_P_2,
VEX_W_0F3807_P_2, VEX_W_0F3808_P_2, VEX_W_0F3809_P_2,
VEX_W_0F380A_P_2, VEX_W_0F380B_P_2, VEX_W_0F3817_P_2,
VEX_W_0F381C_P_2, VEX_W_0F381D_P_2, VEX_W_0F381E_P_2,
VEX_W_0F3820_P_2, VEX_W_0F3821_P_2, VEX_W_0F3822_P_2,
VEX_W_0F3823_P_2, VEX_W_0F3824_P_2, VEX_W_0F3825_P_2,
VEX_W_0F3828_P_2, VEX_W_0F3829_P_2, VEX_W_0F382A_P_2_M_0,
VEX_W_0F382B_P_2, VEX_W_0F3830_P_2, VEX_W_0F3831_P_2,
VEX_W_0F3832_P_2, VEX_W_0F3833_P_2, VEX_W_0F3834_P_2,
VEX_W_0F3835_P_2, VEX_W_0F3837_P_2, VEX_W_0F3838_P_2,
VEX_W_0F3839_P_2, VEX_W_0F383A_P_2, VEX_W_0F383B_P_2,
VEX_W_0F383C_P_2, VEX_W_0F383D_P_2, VEX_W_0F383E_P_2,
VEX_W_0F383F_P_2, VEX_W_0F3840_P_2, VEX_W_0F3841_P_2,
VEX_W_0F38DB_P_2, VEX_W_0F3A08_P_2, VEX_W_0F3A09_P_2,
VEX_W_0F3A0A_P_2, VEX_W_0F3A0B_P_2, VEX_W_0F3A0C_P_2,
VEX_W_0F3A0D_P_2, VEX_W_0F3A0E_P_2, VEX_W_0F3A0F_P_2,
VEX_W_0F3A21_P_2, VEX_W_0F3A40_P_2, VEX_W_0F3A41_P_2,
VEX_W_0F3A42_P_2, VEX_W_0F3A62_P_2, VEX_W_0F3A63_P_2 and
VEX_W_0F3ADF_P_2 entries.
(mod_table): Update MOD_VEX_0F2B, MOD_VEX_0F50,
MOD_VEX_0FD7_PREFIX_2, MOD_VEX_0FE7_PREFIX_2,
MOD_VEX_0FF0_PREFIX_3 and MOD_VEX_0F382A_PREFIX_2 entries.
|
|
* i386-opc.tbl (VexWIG): New.
Replace VexW=3 with VexWIG.
|
|
AVX vrsqrtss is a VEX WIG instruction.
* i386-opc.tbl: Set VexW=3 on AVX vrsqrtss.
* i386-tbl.h: Regenerated.
|
|
AVX "VMOVQ xmm1, xmm2/m64" and "VMOVQ xmm1/m64, xmm2" can only be
encoded with VEX.128. Set Vex=1 on VEX.128 only vmovq and update
assembler tests.
gas/
PR gas/23665
* testsuite/gas/i386/avx-scalar-intel.d: Updated.
* testsuite/gas/i386/avx-scalar.d: Likewise.
* testsuite/gas/i386/x86-64-avx-scalar-intel.d: Likewise.
* testsuite/gas/i386/x86-64-avx-scalar.d: Likewise.
opcodes/
PR gas/23665
* i386-dis.c (vex_len_table): Update VEX_LEN_0F7E_P_1 and
VEX_LEN_0FD6_P_2 entries.
* i386-opc.tbl: Set Vex=1 on VEX.128 only vmovq.
* i386-tbl.h: Regenerated.
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|
Add VEXWIG, defined as 3, to indicate that the VEX.W/EVEX.W bit is
ignored by such VEX/EVEX instructions, aka WIG instructions. Set
VexW=3 on VEX/EVEX WIG instructions. Update assembler to check
VEXWIG when setting the VEX.W bit.
gas/
PR gas/23642
* config/tc-i386.c (build_vex_prefix): Check VEXWIG when setting
the VEX.W bit.
(build_evex_prefix): Check VEXWIG when setting the EVEX.W bit.
opcodes/
PR gas/23642
* i386-opc.h (VEXWIG): New.
* i386-opc.tbl: Set VexW=3 on VEX/EVEX WIG instructions.
* i386-tbl.h: Regenerated.
|
|
Update x86 disassembler to handle the unsupported static rounding in
vcvt[u]si2sd in 32-bit mode.
gas/
PR binutils/23655
* testsuite/gas/i386/evex.d: Updated.
opcodes/
PR binutils/23655
* i386-dis-evex.h: Replace EXxEVexR with EXxEVexR64 for
vcvtsi2sd%LQ and vcvtusi2sd%LQ.
* i386-dis.c (EXxEVexR64): New.
(evex_rounding_64_mode): Likewise.
(OP_Rounding): Handle evex_rounding_64_mode.
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Update x86 disassembler to ignore the EVEX.W bit in EVEX vcvt[u]si2s[sd]
instructions in 32-bit mode.
gas/
PR binutils/23655
* testsuite/gas/i386/evex.d: New file.
* testsuite/gas/i386/evex.s: Likewise.
* testsuite/gas/i386/i386.exp: Run evex.
opcodes/
PR binutils/23655
* i386-dis-evex.h (evex_table): Replace Eq with Edqa for
vcvtsi2ss%LQ, vcvtsi2sd%LQ, vcvtusi2ss%LQ and vcvtusi2sd%LQ.
* i386-dis.c (Edqa): New.
(dqa_mode): Likewise.
(intel_operand_size): Handle dqa_mode as m_mode.
(OP_E_register): Handle dqa_mode as dq_mode.
(OP_E_memory): Set shift for dqa_mode based on address_mode.
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* i386-dis.c (OP_E_memory): Reformat.
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Just like other insns having byte and word forms, these can also make
use of the W modifier, which at the same time allows simplifying some
other code a little bit.
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Put back changes lost in commit 41d1ab6a6d96937fd0db04e53746f93f53687807.
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1. Mark VEX.W0 VEX instructions with VexW=1.
2. Mark VEX.W1 VEX instructions with VexW=2.
3. Remove VexW=1 from WIG VEX instructions.
* i386-opc.tbl: Add VexW=1 to VEX.W0 VEX movd, cvtsi2ss, cvtsi2sd,
pextrd, pinsrd, vcvtsi2sd, vcvtsi2ss, vmovd, vpextrd and vpinsrd.
Add VexW=2 to VEX.W1 VEX movd, movq, pextrq, pinsrq, vmod, vmovq,
vpextrq and vpinsrq. Remove VexW=1 from WIG VEX movq and vmovq.
* i386-tbl.h: Regenerated.
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