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2018-10-19Arm: Fix disassembler crashing on -b binary when thumb file and thumb not for...Tamar Christina2-3/+14
2018-10-16AArch64: Fix error checking for SIMD udot (by element)Matthew Malcomson2-1/+7
2018-10-10x86: fold Size{16,32,64} template attributesJan Beulich5-15577/+11696
2018-10-09[PATCH, BINUTULS, AARCH64, 9/9] Add SSBS to MSR/MRSSudakshina Das2-0/+23
2018-10-09[PATCH, BINUTILS, AARCH64, 8/9] Add SCXTNUM_ELx and ID_PFR2_EL1 system registersSudakshina Das2-0/+26
2018-10-09[PATCH, BINUTILS, AARCH64, 7/9] Add BTI instructionSudakshina Das8-1136/+1182
2018-10-09[PATCH, BINUTILS, AARCH64, 6/9] Add Random number instructionsSudakshina Das2-0/+16
2018-10-09[PATCH, BINUTILS, AARCH64, 5/9] Add DC CVADP instructionSudakshina Das2-0/+11
2018-10-09[PATCH, BINUTILS, AARCH64, 4/9] Add Execution and Data Restriction instructionsSudakshina Das7-1089/+1147
2018-10-09[PATCH, BINUTILS, AARCH64, 3/9] Add instruction SB for ARMv8.5-ASudakshina Das5-1014/+1030
2018-10-09[PATCH, BINUTILS, AARCH64, 2/9] Add Data procoessing instructions for ARMv8.5-ASudakshina Das5-2644/+2766
2018-10-09[PATCH, BINUTILS, AARCH64, 1/9] Add -march=armv8.5-a and related internal fea...Sudakshina Das2-0/+11
2018-10-08AArch64: Replace C initializers with memsetTamar Christina2-1/+7
2018-10-05x86: Add Intel ENCLV to assembler and disassemblerH.J. Lu4-1/+22
2018-10-05[Arm, 2/3] Add instruction SB for AArch32Sudakshina Das2-0/+11
2018-10-05or1k: Add the l.muld, l.muldu, l.macu, l.msbu insnsRichard Henderson6-29/+163
2018-10-05or1k: Add the l.adrp insn and supporting relocationsStafford Horne9-137/+320
2018-10-05or1k: Add relocations for high-signed and low-storesRichard Henderson2-272/+172
2018-10-03AArch64: Constraint disassembler and assembler changes.Tamar Christina4-11/+104
2018-10-03AArch64: Add SVE constraints verifier.Tamar Christina3-1/+358
2018-10-03AArch64: Refactor verifiers to make more general.Tamar Christina3-7/+16
2018-10-03AArch64: Refactor err_type.Tamar Christina2-13/+13
2018-10-03AArch64: Wire through instr_sequenceTamar Christina3-1/+10
2018-10-03AArch64: Mark sve instructions that require MOVPRFX constraintsTamar Christina2-231/+254
2018-10-02RISC-V: Add fence.tso instructionPalmer Dabbelt2-0/+5
2018-09-23Fix incorrect extraction of signed constants in nios2 disassembler.Sandra Loosemore2-13/+21
2018-09-21csky-opc.h: Initialize fields of last array elementsSimon Marchi7-68/+14
2018-09-20ARC: Fix build errors with large constants and C89Maciej W. Rozycki2-26/+30
2018-09-20Andes Technology has good news for you, we plan to update the nds32 port of b...Nick Clifton5-300/+944
2018-09-17RISC-V: bge[u] should get higher priority than ble[u].Jim Wilson2-2/+6
2018-09-17x86: Set EVex=2 on EVEX.128 only vmovd and vmovqH.J. Lu5-13/+94
2018-09-17x86: Set Vex=1 on VEX.128 only vmovd and vmovqH.J. Lu4-18/+24
2018-09-17x86: Update disassembler for VexWIGH.J. Lu2-1563/+619
2018-09-17x86: Replace VexW=3 with VexWIGH.J. Lu2-468/+475
2018-09-15x86: Set VexW=3 on AVX vrsqrtssH.J. Lu3-2/+7
2018-09-15x86: Set Vex=1 on VEX.128 only vmovqH.J. Lu4-6/+12
2018-09-14x86: Support VEX/EVEX WIG encodingH.J. Lu4-932/+941
2018-09-14x86: Handle unsupported static rounding in vcvt[u]si2sd in 32-bit modeH.J. Lu3-2/+22
2018-09-14x86: Properly decode EVEX.W in vcvt[u]si2s[sd] in 32-bit modeH.J. Lu3-4/+23
2018-09-14i386: Reformat OP_E_memoryH.J. Lu2-2/+6
2018-09-14x86: fold CRC32 templatesJan Beulich3-45/+12
2018-09-13x86: Remove VexW=1 from WIG VEX movq and vmovqH.J. Lu2-8/+8
2018-09-13i386: Update VexW field for VEX instructionsH.J. Lu3-36/+44
2018-09-13x86: drop bogus IgnoreSize from a few further insnsJan Beulich3-52/+61
2018-09-13x86: drop bogus IgnoreSize from AVX512_4* insnsJan Beulich3-12/+18
2018-09-13x86: drop bogus IgnoreSize from AVX512DQ insnsJan Beulich3-96/+102
2018-09-13x86: drop bogus IgnoreSize from AVX512BW insnsJan Beulich3-78/+84
2018-09-13x86: drop bogus IgnoreSize from AVX512VL insnsJan Beulich3-26/+32
2018-09-13x86: drop bogus IgnoreSize from AVX512ER insnsJan Beulich3-32/+38
2018-09-13x86: drop bogus IgnoreSize from AVX512F insnsJan Beulich3-742/+748
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