Age | Commit message (Collapse) | Author | Files | Lines |
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check to fix false keyword trigger with names such as <keyword>_foo.
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(run-cgen-all): New rule.
* Makefile.in: Regenerate.
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2002-12-18 Chris Demetriou <cgd@broadcom.com>
* mips-opc.c (mips_builtin_opcodes): Remove one "ror" and two
"dror" entries, and reorder the remaining "dror" and "ror" entries.
[ gas/ChangeLog ]
2002-12-18 Chris Demetriou <cgd@broadcom.com>
* config/tc-mips.c (macro): In M_DROL, M_DROR, M_ROL, and M_ROR,
use hardware rotate ops as appropriate. In M_DROL_I, M_DROR_I,
M_ROL_I, and M_ROR_I, simplify code, clean up warnings, and
arrange not to issue warnings about use of AT when AT is not
actually used.
[ gas/testsuite/ChangeLog ]
2002-12-18 Chris Demetriou <cgd@broadcom.com>
* gas/mips/rol.s: Add ".set noat" and some new instructions to test.
* gas/mips/rol64.s: Likewise.
* gas/mips/rol.l: New file.
* gas/mips/rol.d: Adjust to use rol.l and for rol.s changes.
* gas/mips/rol64.l: New file.
* gas/mips/rol64.d: Adjust to use rol64.l and for rol64.s changes.
* gas/mips/rol-hw.d: New file.
* gas/mips/rol-hw.l: New file.
* gas/mips/rol64-hw.d: New file.
* gas/mips/rol64-hw.l: New file.
* gas/mips/mips.exp: Run rol-hw and rol64-hw tests.
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keyword.
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warnings.
* config/tc-h8500.c (cons): Delete declaration.
(md_begin <opcode>): Constify.
(displacement_size, immediate_size, absolute_size): Remove.
(build_relaxable_instruction <operand>): Add ATTRIBUTE_UNUSED.
(tc_crawl_symbol_chain <headers>): Likewise.
(md_undefined_symbol <name>): Likewise.
(tc_headers_hook <headers>): Likewise.
(md_parse_option <c,arg>): Likewise.
(md_show_usage <stream>): Likewise.
(md_convert_frag <headers, seg>): Likewise.
(tc_coff_symbol_emit_hook <ignore>): Likewise.
(md_atof): Remove declaration of atof_ieee.
(tc_aout_fix_to_chars): Remove unused function.
(parse_reg): Prototype.
(parse_exp): Prototype.
(skip_colonthing): Prototype. Use &&, not & in logical expressions.
(parse_reglist): Prototype.
(get_operand): Prototype.
(get_operands): Prototype.
(get_specific): Prototype. Make "this_index" signed.
(check): Prototype, make static.
(insert): Prototype
(build_relaxable_instruction): Prototype, make static.
(build_bytes): Prototype.
(wordify_scb): Prototype.
* config/tc-h8500.h (start_label): Declare.
(tc_coff_sizemachdep): Declare.
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* pj-dis.c (print_insn_pj): Adjust for pj_opc_info_t change.
* config/tc-pj.c (little, big, parse_exp_save_ilp): Prototype.
(c_to_r, ipush_code, fake_opcode, alias): Likewise.
(fake_opcode): Adjust for pj_opc_int_t change.
(md_begin): Likewise.
(md_assemble): Likewise.
(ipush_code): Correct parse_exp_save_ilp call. Test pending_reloc
instead of non-existent third arg of parse_exp_save_ilp.
(md_parse_option): Correct "little" and "big" calls.
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(whatreg, parse_reg, parse_exp): Make static, prototype.
(checkfor, regword, regaddr, get_ctrl_operand): Prototype.
(get_flags_operand, get_interrupt_operand, get_cc_operand): Likewise.
(get_operand, get_operands, get_specific, newfix): Likewise.
(apply_fix, build_bytes): Likewise.
(md_atof): Remove declaration of atof_ieee.
(tc_aout_fix_to_chars): Delete.
(md_begin): Constify "opcode". Don't try to init opcode->idx.
Fix s_unseg call.
(md_parse_option): Fix s_segm and s_unseg calls.
* z8kgen.c: Include "libiberty.h".
(opt, args, toks): Fix initializer warnings.
(chewname): Make "name" a char **. Return mnemonic trimmed of
operands.
(gas): Improve emitted "DO NOT EDIT" warning. Format emitted
opcode_entry_type, and make "nicename" and "name" const. Make
z8k_table const too. Formatting. Generate idx as gas needs it.
* z8k-opc.h: Regenerate.
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for 9 and 16-bit PC-relative addressing mode.
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* ppc-opc.c: Delete evsabs, evsnabs, evsneg, evsadd, evssub,
evsmul, evsdiv, evscmpgt, evsgmplt, evststgt, evtstlt, evststeq,
evscfui, evscfsi, evscfuf, evscfsf, evsctui, evsctuiz, evsctsi,
evsctsiz, evsctuf, evsctsf, evmwhssfaa, evmwhssmaa, evmwhsmfaa,
evmwhsmiaa, evmwhusiaa, evmwhumiaa, evmwhssfan, evmwhssian,
evmwhsmfan, evmwhsmian, evmwhusian, evmwhumian, evmwhgssfaa,
evmwhgsmfaa, evmwhgsmiaa, evmwhgumiaa, evmwhgssfan, evmwhgsmfan,
evmwhgsmian, evmwhgumian.
(mftb): Add to opcode table.
(mtspefscr): Change RT to RS in opcode table.
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msync.
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bfd/ChangeLog
* cpu-ia64-opc.c: Add operand constant "ar.csd".
gas/ChangeLog
* config/tc-ia64.c (pseudo_func): Add "@pause" constant for "hint"
instruction.
(emit_one_bundle): Handle "hint" instruction.
(operand_match): Match IA64_OPND_AR_CSD.
gas/testsuite/ChangeLog
* gas/ia64/opc-b.d: Update for instructions added by SDM2.1.
* gas/ia64/opc-b.s: Ditto.
* gas/ia64/opc-f.d: Ditto.
* gas/ia64/opc-f.s: Ditto.
* gas/ia64/opc-i.d: Ditto.
* gas/ia64/opc-i.s: Ditto.
* gas/ia64/opc-m.d: Ditto.
* gas/ia64/opc-m.s: Ditto.
* gas/ia64/opc-x.d: Ditto.
* gas/ia64/opc-x.s: Ditto.
include/opcode/ChangeLog
* ia64.h: Fix copyright message.
(IA64_OPND_AR_CSD): New operand kind.
opcodes/ChangeLog
* ia64-opc-d.c (ia64_opcodes_d): Add "hint" instruction.
* ia64-opc-b.c: Add "hint.b" instruction.
* ia64-opc-f.c: Add "hint.f" instruction.
* ia64-opc-i.c: Add "hint.i" instruction.
* ia64-opc-m.c: Add "hint.m", "fc.i", "ld16", "st16", and
"cmp8xchg16" instructions.
* ia64-opc-x.c: Add "hint.x" instruction.
* ia64-opc.h (AR_CSD): New macro.
* ia64-ic.tbl: Update according to SDM2.1.
* ia64-raw.tbl: Ditto.
* ia64-waw.tbl: Ditto.
* ia64-gen.c (in_iclass): Handle "hint" like "nop".
(lookup_regindex): Recognize AR[FCR], AR[EFLAG], AR[CSD],
AR[SSD], AR[CFLG], AR[FSR], AR[FIR], and AR[FDR].
* ia64-asmtab.c: Regenerate.
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* ppc-opc.c: Remove evmwlssf, evmwlssfa, evmwlsmf, evmwlsmfa,
evmwlssfaaw, evmwlsmfaaw, evmwlssfanw, evmwlsfanw.
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* ppc-opc.c (PMRN): Remove.
(RA): Set to NB + 1.
(powerpc_opcodes): Change PMRN to SPR.
Change all RD to RS.
Change mftb to look like mftbl.
Move mftb before mftbl.
Add mfbbtar.
Add mtbbtar.
Change mfpmr to use PMR.
Change mtpmr to use PMR.
(RD): Remove.
(insert_ev2): Fix mask and shift.
(extract_ev2): Same.
(insert_ev4): Same.
(extract_ev4): Same.
(PMR): Define.
(extract_pmrn): Remove.
(insert_pmrn): Remove.
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* ia64.h (enum ia64_opnd): Add IA64_OPND_LDXMOV.
bfd/
* cpu-ia64-opc.c (elf64_ia64_operands): Add ldxmov entry.
opcodes/
* ia64-opc-m.c: Add ld8.mov.
* ia64-asmtab.c: Regenerate.
gas/
* config/tc-ia64.c (operand_match): Add IA64_OPND_LDXMOV case.
gas/testsuite/
* gas/ia64/ldxmov-1.[ds]: New.
* gas/ia64/ldxmov-2.[ls]: New.
* gas/ia64/ia64.exp: Run them.
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* fr30-desc.c: Regenerate.
* fr30-dis.c: Regenerate.
* frv-desc.c: Regenerate.
* frv-dis.c: Regenerate.
* ip2k-asm.c: Regenerate.
* ip2k-desc.c: Regenerate.
* ip2k-dis.c: Regenerate.
* ip2k-opc.c: Regenerate.
* ip2k-opc.h: Regenerate.
* m32r-desc.c: Regenerate.
* m32r-dis.c: Regenerate.
* openrisc-desc.c: Regenerate.
* openrisc-dis.c: Regenerate.
* xstormy16-asm.c: Regenerate.
* xstormy16-desc.c: Regenerate.
* xstormy16-dis.c: Regenerate.
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(print_insn_thumb): Likewise.
* h8500-dis.c (print_insn_h8500): Constify "opcode".
* mcore-dis.c (print_insn_mcore): Constify "op". Formatting.
* ns32k-dis.c (print_insn_arg <case 'F'>): Use a union to avoid
type-punned pointer warnings.
<case 'L'>: Likewise. Fix error message too.
* pdp11-dis.c (print_reg): Warning fix.
* sh-dis.c (print_movxy): Constify "op" param.
(print_insn_ddt): Constify sh_opcode_info vars.
(print_insn_ppi): Likewise.
(print_insn_sh): Likewise.
* tic30-dis.c (cnvt_tmsfloat_ieee): Use a union to avoid
type-punned pointer warnings.
* w65-dis.c (print_insn_w65): Constify "op".
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(print_indexed_operand): Need an adjustment for some PC-relative
operand modes; print the final address of PC-relative modes.
(print_insn): Take into account movw/movb to adjust the PC-relative
operand addresses.
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comparisons of bfd_boolean vars with TRUE/FALSE. Formatting.
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* ia64-dis.c (print_insn_ia64): Correct handling of IA64_OPND_TGT64.
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* xstormy16-opc.c: Regenerate.
* xstormy16-opc.h: Regenerate.
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* avr-dis.c: Include libiberty.h (for xmalloc).
(struct avr_opcodes_s): Remove 'bin_mask' field (it's
automatically computed in the init routine).
(AVR_INSN): No longer provide bin_mask field in initializer.
(avr_opcodes_s): Declare as const.
(print_insn_avr): Store the bin_mask field in a separate table
(allocated with xmalloc); iterate through it at the same time as
we iterate through the opcodes.
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* h8300.h (h8_opcode): Remove 'length' field.
(h8_opcodes): Mark as 'const' (both the declaration and
definition). Modify initializer and initializer macros to no
longer initialize the length field.
2002-11-11 Klee Dienes <kdienes@apple.com>
* h8300-dis.c: Include libiberty.h (for xmalloc).
(struct h8_instruction): New type, used to wrap h8_opcodes with a
length field (computed at run-time).
(h8_instructions): New variable.
(bfd_h8_disassemble_init): Allocate the storage for
h8_instructions. Fill h8_instructions with pointers to the
appropriate opcode and the correct value for the length field.
(bfd_h8_disassemble): Iterate through h8_instructions instead of
h8_opcodes.
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* arc.h (arc_ext_opcodes): Declare as extern.
(arc_ext_operands): Declare as extern.
* i860.h (i860_opcodes): Declare as const.
2002-11-18 Klee Dienes <kdienes@apple.com>
* arc-opc.c (arc_ext_opcodes): Define.
(arc_ext_operands): Define.
* i386-dis.c (Suffix3DNow): Declare as const.
* arm-opc.h (arm_opcodes): Declare as const.
(thumb_opcodes): Declare as const.
* h8500-opc.h (h8500_table): Declare as const.
(h8500_table): Use a NULL for the opcode in the terminator, so
that code testing (opcode->name) behaves correctly.
* mcore-opc.h (mcore_table): Declare as const.
* sh-opc.h (sh_table): Declare as const.
* w65-opc.h (optable): Declare as const.
* z8k-opc.h (z8k_table): Declare as const.
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parameters. Added support for new opcode-list format. General
error message fixups.
(c4x_inst_add): Reject insn not for our CPU
(md_begin): Added matrix for setting the proper opcode-level &
device-flags according to cpu type and revision. Rewrite the
opcode hasher.
(c4x_operand_parse): Fix opcode bug
(c4x_operands_match): New function argument. Added dry-run
mechanism, that is optional error generation. Added constraint 'i'
and 'j'.
(c4x_insn_check): Added new function for post-verification of the
generated insn.
(md_assemble): Check all opcodes before croaking because of an
argument mismatch. Need this to be able to fully support
ortogonally arguments.
(md_parse_options): Revised commandprompt swicthes and added new
ones.
(md_show_usage): Complete rewrite of printout.
* gas/testsuite/gas/tic4x/addressing.s: Fix bug in one insn
* gas/testsuite/gas/tic4x/addressing_c3x.d: Update thereafter
* gas/testsuite/gas/tic4x/addressing_c4x.d: Update thereafter
* gas/testsuite/gas/tic4x/allopcodes.S: Add support for new
opclass.h changes
* gas/testsuite/gas/tic4x/opclasses.h: Added testsuites for
the new enhanced opcodes.
* gas/testsuite/gas/tic4x/opcodes.s: Regenerate
* gas/testsuite/gas/tic4x/opcodes_c3x.d: Update from above
* gas/testsuite/gas/tic4x/opcodes_c4x.d: Update from above
* gas/testsuite/gas/tic4x/opcodes_new.d: Added new testsuite for
the enhanced and special insns.
* gas/testsuite/gas/tic4x/tic4x.exp: Added the opcodes_new testsuite
* include/opcode/tic4x.h: File reordering. Added enhanced opcodes.
* opcodes/tic4x-dis.c: Added support for enhanced and special
insn.
(c4x_print_op): Added insn class 'i' and 'j'
(c4x_hash_opcode_special): Add to support special insn
(c4x_hash_opcode): Update to support the new opcode-list
format. Add support for the new special insns.
(c4x_disassemble): New opcode-list support.
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* m88k-dis.c: Include libiberty.h (for xmalloc).
(HASHTAB): New type, used to build instruction hash tables.
Contains a pointer to an INSTAB and a pointer to the next hash
chain entry.
(instructions): Move definition from m88k.h; remove initialization
of 'next' field.
(hashtable): Now an aray of pointer-to-HASHTAB, not INSTAB.
(printop): Mark pointer to OPSPEC as const.
(install): Remove; fold into init_disasm.
(m88kdis): Update to ihashtab_initialized to 1 after calling
init_disasm. entry_ptr now iterates through HASHTABs, not
INSTABs.
(init_disasm): Iterate through the instructions and add to
hashtable[].
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(c4x_operands_match): Added check for 8-bits LDF insn. Give
warning when using constant direct bigger than 2^16. Add the new
arguments.
* include/opcode/tic4x.h: Major rewrite of entire file. Define
instruction classes, and put each instruction into a class.
* opcodes/tic4x-dis.c: (c4x_print_op): Add support for the new
argument format. Fix bug in 'N' register printer.
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* ppc-opc.c (EVUIMM_4): Change bit size to 32.
(EVUIMM_2): Same.
(EVUIMM_8): Same.
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* ppc-opc.c (EVUIMM_4): Change bit size to 32.
(EVUIMM_2): Same.
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Convert Makefile.am to pass --srcdir to ia64-gen. Fix compile time warnings.
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* opcodes/ppc-opc.c: Change RD to RS for evmerge*.
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at the end.
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* mips.h: Update comment for new opcodes.
(OP_MASK_VECBYTE, OP_SH_VECBYTE): New.
(OP_MASK_VECALIGN, OP_SH_VECALIGN): New.
(INSN_4111, INSN_4120, INSN_5400, INSN_5500): New.
(CPU_VR4120, CPU_VR5400, CPU_VR5500): New.
(OPCODE_IS_MEMBER): Handle the new CPU_* values and INSN_* flags.
Don't match CPU_R4111 with INSN_4100.
[opcodes/]
* mips-dis.c (print_insn_arg): Handle '[', ']', 'e' and '%'.
(mips_isa_type): Handle bfd_mach_mips4120, bfd_mach_mips5400
and bfd_mach_mips5500.
* mips-opc.c (V1): Include INSN_4111 and INSN_4120.
(N411, N412, N5, N54, N55): New convenience defines.
(mips_builtin_opcodes): Add vr4120, vr5400 and vr5500 opcodes.
Change dmadd16 and madd16 from V1 to N411.
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* config/tc-mips.c (CPU_HAS_MIPS16): Add mips-lsi-elf as MIPS16
capable configuration.
(macro_build): Check for MIPS16 capability, not for actual MIPS16 code
generation.
(mips_ip): Likewise.
/gas/testsuite/ChangeLog
* gas/mips/mips-jalx.d: New file, check jalx assembly.
* gas/mips/mips-jalx.s: Likewise.
* gas/mips/mips-no-jalx.l: Likewise.
* gas/mips/mips-no-jalx.s: Likewise.
* gas/mips/mips16-jalx.d: Likewise.
* gas/mips/mips16-jalx.s: Likewise.
* gas/mips/mips.exp: Add new tests.
/opcodes/ChangeLog:
* mips-dis.c (print_insn_mips): Always allow disassembly of
32-bit jalx opcode.
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* Makefile.in: Regenerate.
* po/POTFILES.in: Regenerate.
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Convert functions to K&R format.
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is the BookE32. (case 107575)
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arguments.
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