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least significant bits set.
PR 11201.
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register prefix.
Fixes improper disassembly of movm instructions.
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mov am,(imm32,sp).
Found during initial simulator work.
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* mips16-opc.c: New file.
* mips-dis.c: Include "elf-bfd.h" and "elf/mips.h".
(mips16_reg_names): New static array.
(print_insn_big_mips): Use print_insn_mips16 in 16 bit mode or
after seeing a 16 bit symbol.
(print_insn_little_mips): Likewise.
(print_insn_mips16): New static function.
(print_mips16_insn_arg): New static function.
* mips-opc.c: Add jalx instruction.
* Makefile.in (mips16-opc.o): New target.
* configure.in: Use mips16-opc.o for bfd_mips_arch.
* configure: Rebuild.
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operand specifiers in *save, *restore and movem* instructions.
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the coldfire.
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instruction for the coldfire.
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register operands for immediate arithmetic, not, neg, negx, and
set according to condition instructions.
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specifier of the effective-address operand in immediate forms of
arithmetic instructions. The specifier for the immediate operand
notes how and where the constant will be stored.
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opcode.
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register prefix.
It's easier for the assembler...
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More disassembler stuff.
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"call", "ret", and "rets" instructions.
Stuff noticed while working on disasembler.
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addresses symbolically if possible.
* mn10300-opc.c: Distinguish between absolute memory addresses,
pc-relative offsets & random immediates.
More disassembler work.
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in 7 byte insns.
(disassemble): Handle SPLIT and EXTENDED operands.
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* mn10300-opc.c (mn10300_opcodes): Fix masks on several insns.
Selects opcodes & consumes bytes. Breaks badly if given data instead of
code. No operands yet.
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list.
(mn10300_opcodes): Use REGS for register list in "movm" instructions.
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register argument is calls and jmp instructions.
Found trying to build libgcc2 for the mn10300 :-)
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getx operand. Fix opcode for mulqu imm,dn.
Fix bugs exposed by gas testsuite (extended instructions).
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in MN10300_OPERAND_SPLIT operands for how many bits
appear in the basic insn word. Add IMM32_HIGH24,
IMM32_HIGH24_LOWSHIFT8, IMM8E_SHIFT8.
(mn10300_opcodes): Use new operands as needed.
Support for everything in the basic instruction manual (yippie!)
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for bset, bclr, btst instructions.
(mn10300_opcodes): Use new IMM32_LOWSHIFT8 as needed.
For btst, bclr & bset.
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operands. Update opcode table as appropriate.
(IMM32): Add MN10300_OPERAND_SPLIT flag.
(mn10300_opcodes): Fix single bit error in mov imm32,dn insn.
Cleaning up a little.
Attempting to insert most 32bit operands.
And a bug found by assembler testsuite.
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operands (for indexed load/stores). Fix bitpos for DI
operand. Add SN8N_SHIFT8, IMM8_SHIFT8, and D16_SHIFT for the
few instructions that insert immediates/displacements in the
middle of the instruction. Add IMM8E for 8 bit immediate in
the extended part of an instruction.
(mn10300_operands): Use new opcodes as appropriate.
Opcode table changes so we can correctly insert everything except
32bit operands.
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* d10v-opc.c (d10v_opcodes): Declare the trap instruction
sequential so the assembler never parallelizes it with
other instructions.
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a data/address register that appears in register field 0
and register field 1.
(mn10300_opcodes): Use DN01 and AN01 for mov/cmp imm8,DN/AN
Hacking Matsushita again. Yippie!
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* alpha-dis.c (print_insn_alpha): Use new NOPAL mask for
standard disassembly.
* alpha-opc.c (alpha_operands): Rearrange flags slot.
(alpha_opcodes): Add new BWX, CIX, and MAX instructions.
Recategorize PALcode instructions.
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there are no operand types.
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changed.
(v850_operands): Make sure D22 immediately follows D9_RELAX.
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"bCC"instructions).
Because quantum's code uses jnz, jcc, etc etc etc.
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and the arguments.
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(powerpc_opcodes): Use PPCPWR2 for fsqrt, rather than duplicating
it.
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field for movhu instruction.
Bug found by gas testsuite.
* v850-dis.c (disassemble): For V850_OPERAND_SIGNED operands,
cast value to "long" not "signed long" to keep hpux10
compiler quiet.
Found in an attempt to build the v850 on hpux10 with the HP
compiler.
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for mov (abs16),DN.
Bug found by gas testsuite. Matsushita.
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Moved into opcode/mn10300.h
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for shift-by-register opcodes.
Bug found by testsuite.
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into [AD][MN][01] for encoding the position of the register
in the opcode.
Matsushita.
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"putx", "getx", "mulq", "mulqu", "sat16", "sat24", "bsch".
Matsushita.
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Fix various typos. Add "PAREN" operand.
(MEM, MEM2): Define.
(mn10300_opcodes): Surround all memory addresses with "PAREN"
operands. Fix several typos.
Should parse all opcodes in the instruction specification, except the
"user extension instructions".
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changes.
Matsushita.
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(mn10300_operands): Rough cut. Enough to parse "mov" instructions
at this time.
(mn10300_opcodes): Break opcode format out into its own field.
Update many operand fields to deal with signed vs unsigned
issues. Fix one or two typos in the "mov" instruction
opcode, mask and/or operand fields.
Checkpointing today's work. Matsushita.
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<schwab@issan.informatik.uni-dortmund.de>
* m68k-opc.c (plusha): Prefer encoding for m68040up, in case
m68851 wasn't reset.
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all opcodes. Very rough cut at operands for all opcodes.
Matsushita.
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opcode table.
Checkpointint 10300 work.
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mn10300-dis.o, and mn10300-opc.o.
Also add d10v and v850 files, with appropriate sanitization.
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with a single generic configuration. So break them up into two different
configurations. See the individual ChangeLogs for additional detail.
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