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2016-04-20update many old style function definitionsTrevor Saunders21-141/+98
2016-04-19opcodes/arc: Add yet more nps instructionsAndrew Burgess3-23/+246
2016-04-19opcodes/arc: Add more nps instructionsAndrew Burgess2-0/+23
2016-04-15Regenerate Makefile.in/aclocal.m4 automake 1.11.6H.J. Lu3-45/+104
2016-04-14arc/nps400 : New cmem instructions and associated relocationAndrew Burgess3-0/+42
2016-04-14opcodes/arc: Move instruction length logic to new functionAndrew Burgess2-13/+50
2016-04-13Fix disassembly of the V850's LD.BU instruction.Nick Clifton2-2/+8
2016-04-12Add support for .extCondCode, .extCoreRegister and .extAuxRegister.Claudiu Zissulescu5-437/+543
2016-04-12Update ARC instruction data-base.Claudiu Zissulescu2-0/+10
2016-04-12Add support for .extInstruction pseudo-op.Claudiu Zissulescu5-142/+554
2016-04-11MIPS/opcodes: Fix undecoded MIPS16 extended instruction bit disassemblyMaciej W. Rozycki2-2/+9
2016-04-07arc/nps400: Add new instructionsAndrew Burgess3-0/+73
2016-04-07gas/arc: Handle multiple arc_opcode chains for same mnemonicAndrew Burgess2-1/+35
2016-04-05arc/nps400: Add additional instructionsAndrew Burgess3-2/+241
2016-04-05[ARC] Fix support for double assist instructions.Claudiu Zissulescu4-1064/+1077
2016-04-05[ARM] Add ARMv8.2 FP16 vmul/vmla/vmls (by scalar)Jiong Wang2-6/+22
2016-03-31opcodes: Fix date in ChangeLog entryAndrew Burgess1-1/+1
2016-03-31opcodes/arc/nps: Fix some operand flagsAndrew Burgess2-2/+7
2016-03-31enable -Wwrite-strings for gasTrevor Saunders1-2/+18
2016-03-30opcodes/arc: Comment and whitespace fixes in opcode tableAndrew Burgess2-6/+13
2016-03-30[ARC] Cleanup AUX register names.Claudiu Zissulescu2-27/+13
2016-03-29[ARC] Fix typo in extension instruction name.Claudiu Zissulescu2-1/+5
2016-03-29[ARC] Add support for Quarkse opcodes.Claudiu Zissulescu5-6/+130
2016-03-24More -Wstack-usage warnings: opcodes/aarch64-*Jan Kratochvil3-7/+11
2016-03-24sparc: reorder wr instructions in sparc_opcodes to fix diagnosticsJose E. Marchesi2-6/+11
2016-03-22Add -Wstack-usage to the gcc warning flags list, but only if using a sufficie...Nick Clifton2-1/+23
2016-03-21arc/nps400: Add first nps400 instructionsAndrew Burgess3-0/+173
2016-03-21arc/opcodes: Use flag operand class to handle multiple flag matchesAndrew Burgess2-25/+31
2016-03-21arc: Add nps400 machine type, and assembler flag.Andrew Burgess2-0/+8
2016-03-21arc/gas: default mach is arc700, initialised in md_beginAndrew Burgess2-3/+4
2016-03-21Remove use of alloca.Nick Clifton2-2/+3
2016-03-18Fix the disassembly of the AArch64's OOR instruction as a MOV instruction.Nick Clifton2-1/+7
2016-03-16[ARM] Support ARMv8.2 FP16 simd instructionsJiong Wang2-23/+85
2016-03-07Add const qualifiers at various places.Trevor Saunders5-7/+15
2016-03-03Regenerate or1k opcodes fileAlan Modra2-3/+4
2016-03-02Regenerate rl78 opcodes fileAlan Modra2-2/+3
2016-03-02Fix shift left warning at sourceAlan Modra2-1/+5
2016-03-01Fix typo in print_insn_rl78_common function.Nick Clifton2-1/+7
2016-02-24[OPCODES][ARM][1/3]Add armv8.2 fp16 instruction dissembler support.Renlin Li2-4/+92
2016-02-24[OPCODES][ARM]Fix mask for a few coprocessor opcodes.Renlin Li2-8/+13
2016-02-24[OPCODE][ARM]Correct disassembler for cdp/cdp2, mcr/mcr2, mrc/mrc2, ldc/ldc2,...Renlin Li2-0/+28
2016-02-15Add parentheses to prevent truncated addressesH.J. Lu2-2/+8
2016-02-10Add support for ARC instruction relaxation in the assembler.Claudiu Zissulescu2-0/+132
2016-02-04Fix the encoding of the MSP430's RRUX instruction.Nick Clifton2-2/+14
2016-02-02opcodes/cgen: Rework calculation of shift when inserting fieldsAndrew Burgess15-42/+157
2016-02-02epiphany/disassembler: Improve alignment of output.Andrew Burgess2-2/+7
2016-02-01Fix undefined compilation behaviour shifting a value into the sign bit of a s...Michael McConville2-1/+7
2016-01-25[PATCH[ARM]Check mapping symbol while backward searching for IT block.Renlin Li2-3/+83
2016-01-20[AArch64] Reject invalid immediate operands to MSR UAOMatthew Wahab2-2/+9
2016-01-18MIPS: Remove remnants of 48-bit microMIPS instruction supportMaciej W. Rozycki2-35/+6
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