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2015-11-27[AArch64][PATCH 3/3] Add floating-point FP16 instructionsMatthew Wahab5-682/+964
2015-11-27[AArch64][PATCH 2/3] Adjust a utility function for floating point values.Matthew Wahab2-7/+37
2015-11-27[AArch64][PATCH 1/3] Support ARMv8.2 FP16 floating point instructions.Matthew Wahab2-0/+8
2015-11-27[AArch64] Add ARMv8.2 instruction alias REV64.Matthew Wahab5-768/+785
2015-11-27[AArch64] Add ARMv8.2 instructions BFC and REV64.Matthew Wahab8-861/+967
2015-11-27[AArch64] Let aliased instructions be their preferred form.Matthew Wahab5-2/+202
2015-11-27[Aarch64] Support an ARMv8.2 system register.Matthew Wahab2-0/+11
2015-11-23opcodes: handle mach-o for thumb/arm disambiguation.Tristan Gingold2-0/+12
2015-11-20[AArch64] Add support for ARMv8.1 Virtulization Host Extensions.Matthew Wahab2-0/+78
2015-11-20Remove a if-clause that is redundant because the same test has been performed...Nick Clifton2-4/+5
2015-11-20Update translations.Nick Clifton2-317/+1153
2015-11-19[AArch64] Reject invalid immediate operands to MSR PANMatthew Wahab2-0/+13
2015-11-17Fix the disassembly of conditional instructions will illegal condition select...Nick Clifton2-1/+6
2015-11-14Bump version to 2.26.51Tristan Gingold2-10/+14
2015-11-11Add assembler, disassembler and linker support for power9.Peter Bergner3-107/+686
2015-11-09Move copy_u.w to MSA64 ASE, remove copy_u.d.Robert Suchanek1-2/+1
2015-11-02Disassemble RX NOP instructions as such.Nick Clifton3-18/+98
2015-11-02Fix disassembly of RX zero-offset register indirect instructions.Nick Clifton4-7/+14
2015-10-28Pass noaliases_p to aarch64_decode_insnYao Qi2-5/+15
2015-10-27Fix RL78 disassembly of DE+offset addressing to always show the offset, even ...Vinay Kumar3-24/+31
2015-10-27Display system registers by their names when disassembling RL78 instructions.Vinay Kumar4-13/+34
2015-10-27Fix RL78 disassembly so that SP+OFFSET addressing always shows the offset, ev...Vinay Kumar3-20/+27
2015-10-14Add missing changelog entriesAndreas Krebbel1-0/+7
2015-10-14S/390: Fix instruction type of troo, trot, trto, and trtt.Andreas Krebbel2-5/+5
2015-10-08Fix compile time warning compiling ARC port.Nick Clifton2-1/+6
2015-10-07Avoid using 'template' C++ keywordYao Qi3-3/+9
2015-10-07New ARC implementation.Nick Clifton9-2824/+21958
2015-10-02[aarch64] expose disas_aarch64_insn and rename it to aarch64_decode_insnYao Qi2-4/+12
2015-10-02[aarch64] Remove argument pc from disas_aarch64_insnYao Qi2-3/+7
2015-09-29Add support for extensions in the .machine pseudoop on S/390, e.g. ".machine ...Dominik Vogt3-508/+522
2015-09-28Updare French translation for binutils and German translation for opcodes.Nick Clifton2-3/+7
2015-09-28Patches for illegal ppc 500 instructionsTom Rix2-7/+11
2015-09-25The FT32's disassembly of 10-bit literals has the incorrect mask.jamesbowman1-1/+1
2015-09-23Fix compile time warnings generated when compiling with clang.Nick Clifton11-44/+50
2015-09-22Enhance the RX disassembler to detect and report bad instructions.Nick Clifton4-28/+57
2015-09-22opcodes/ppc-opc.c: Add dscr and ctrl SPR mnemonicsAnton Blanchard2-0/+8
2015-09-10S/390: Fix instruction format of crj*, clrj*, and clgrj*.Andreas Krebbel1-3/+3
2015-09-10S/390: Remove F_20 and FE_20. Adjust comments.Andreas Krebbel1-70/+66
2015-09-10S/390: Fix MASK_RIE_R0PI and MASK_RIE_R0PU.Andreas Krebbel1-2/+2
2015-09-09S/390: Remove trailing zeros on 4-bytes opcodes.Andreas Krebbel2-7/+9
2015-09-09S/390: Fix opcode of ppno.Andreas Krebbel1-1/+1
2015-08-25Support for the sparc %pmcdper privileged register.Jose E. Marchesi2-2/+11
2015-08-24Fix the partial disassembly of a broken three byte instruction at the end of ...Jan Stancek2-2/+8
2015-08-21PR binutils/18257: Properly decode x86/Intel mask instructions.Alexander Fomin2-59/+450
2015-08-17Trailing space in opcodes/ generated filesAlan Modra5-845/+835
2015-08-13Fixes for unpredictable nops and 26-bit versions of teq,tst,cmn,cmp.Andre Vieira2-3/+19
2015-08-12[MIPS] Map 'move' to 'or'.Simon Dardis3-3/+8
2015-08-12Remove trailing spaces in opcodesH.J. Lu137-4012/+4012
2015-08-11Fix the disassembly of the AArch64 SIMD EXT instruction.Nick Clifton2-1/+7
2015-08-10Add SIGRIE instruction for MIPS R6Robert Suchanek2-0/+5