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2010-02-10gas/Richard Sandiford2-4/+27
* config/tc-ppc.c (md_show_usage): Add -mpwr4, -mpwr5, -mpwr5x, -mpwr6 and -mpwr7. opcodes/ * ppc-dis.c (ppc_opts): Add "pwr4", "pwr5", "pwr5x", "pwr6" and "pwr7". Move "a2" into alphabetical order.
2010-02-08include/Alan Modra3-141/+172
* opcode/ppc.h (PPC_OPCODE_TITAN): Define. bfd/ * archures.c (bfd_mach_ppc_titan): Define. * bfd-in2.h: Regenerate. * cpu-powerpc.c (bfd_powerpc_archs): Add titan entry. opcodes/ * ppc-dis.c (ppc_opts): Add titan entry. * ppc-opc.c (TITAN, MULHW): Define. (powerpc_opcodes): Support AppliedMicro Titan core (APM83xxx). gas/ * config/tc-ppc.c (md_show_usage): Mention -mtitan. Don't use tabs. (ppc_mach): Handle titan. * doc/c-ppc.texi: Mention -mtitan. gas/testsuite/ * gas/ppc/titan.d, * gas/ppc/titan.s: New test. * gas/ppc/ppc.exp: Run it.
2010-02-032010-02-03 Quentin Neill <quentin.neill@amd.com>Sebastian Pop3-2/+8
gas/ * config/tc-i386.c (cpu_arch): Change amdfam15 to bdver1. (i386_align_code): Rename PROCESSOR_AMDFAM15 to PROCESSOR_BDVER1. * config/tc-i386.h (processor_type): Same. * doc/c-i386.texi: Change amdfam15 to bdver1. opcodes/ * i386-gen.c (cpu_flag_init): Rename CPU_AMDFAM15_FLAGS to CPU_BDVER1_FLAGS * i386-init.h: Regenerated. testsuite/ * gas/i386/i386.exp: Rename amdfam15 test cases to bdver1. * gas/i386/x86-64-nops-1-amdfam15.d: Renamed test case to gas/i386/x86-64-nops-1-bdver1.d. * gas/i386/nops-1-amdfam15.d: Renamed test case to gas/i386/nops-1-bdver1.d.
2010-02-03Move NOP from 0x00 to 0x0f.Anthony Green2-3/+11
2010-01-29 gas/testsuite/Daniel Jacobowitz2-54/+164
* gas/arm/dis-data.d: Update test name. Do not expect .word output. * gas/arm/dis-data2.d, gas/arm/dis-data2.s, gas/arm/dis-data3.d, gas/arm/dis-data3.s: New tests. opcodes/ * opcodes/arm-dis.c (struct arm_private_data): New. (print_insn_coprocessor, print_insn_arm): Update to use struct arm_private_data. (is_mapping_symbol, get_map_sym_type): New functions. (get_sym_code_type): Check the symbol's section. Do not check mapping symbols. (print_insn): Default to disassembling ARM mode code. Check for mapping symbols separately from other symbols. Use struct arm_private_data.
2010-01-28Allow VL=1 on scalar FMA instructions.H.J. Lu2-13/+30
gas/testsuite/ 2010-01-28 H.J. Lu <hongjiu.lu@intel.com> * gas/i386/fma-scalar-intel.d: New. * gas/i386/fma-scalar.d: Likewise. * gas/i386/fma-scalar.s: Likewise. * gas/i386/x86-64-fma-scalar-intel.d: Likewise. * gas/i386/x86-64-fma-scalar.d: Likewise. * gas/i386/x86-64-fma-scalar.s: Likewise. * gas/i386/i386.exp: Run fma-scalar, fma-scalar-intel, x86-64-fma-scalar and x86-64-fma-scalar-intel. opcodes/ 2010-01-28 H.J. Lu <hongjiu.lu@intel.com> * i386-dis.c (EXVexWdqScalar): New. (vex_scalar_w_dq_mode): Likewise. (prefix_table): Update entries for PREFIX_VEX_3899, PREFIX_VEX_389B, PREFIX_VEX_389D, PREFIX_VEX_389F, PREFIX_VEX_38A9, PREFIX_VEX_38AB, PREFIX_VEX_38AD, PREFIX_VEX_38AF, PREFIX_VEX_38B9, PREFIX_VEX_38BB, PREFIX_VEX_38BD and PREFIX_VEX_38BF. (intel_operand_size): Handle vex_scalar_w_dq_mode. (OP_EX): Likewise.
2010-01-27Allow VL=1 on AVX scalar instructions.H.J. Lu2-44/+167
gas/ 2010-01-27 H.J. Lu <hongjiu.lu@intel.com> * config/tc-i386.c (avxscalar): New. (OPTION_MAVXSCALAR): Likewise. (build_vex_prefix): Select vector_length for scalar instructions based on avxscalar. (md_longopts): Add OPTION_MAVXSCALAR. (md_parse_option): Handle OPTION_MAVXSCALAR. (md_show_usage): Add -mavxscalar=. * doc/c-i386.texi: Document -mavxscalar=. gas/testsuite/ 2010-01-27 H.J. Lu <hongjiu.lu@intel.com> * gas/i386/avx-scalar-intel.d: New. * gas/i386/avx-scalar.d: Likewise. * gas/i386/avx-scalar.s: Likewise. * gas/i386/x86-64-avx-scalar-intel.d: Likewise. * gas/i386/x86-64-avx-scalar.d: Likewise. * gas/i386/x86-64-avx-scalar.s: Likewise. * gas/i386/i386.exp: Run avx-scalar, avx-scalar-intel, x86-64-avx-scalar and x86-64-avx-scalar-intel. opcodes/ 2010-01-27 H.J. Lu <hongjiu.lu@intel.com> * i386-dis.c (XMScalar): New. (EXdScalar): Likewise. (EXqScalar): Likewise. (EXqScalarS): Likewise. (VexScalar): Likewise. (EXdVexScalarS): Likewise. (EXqVexScalarS): Likewise. (XMVexScalar): Likewise. (scalar_mode): Likewise. (d_scalar_mode): Likewise. (d_scalar_swap_mode): Likewise. (q_scalar_mode): Likewise. (q_scalar_swap_mode): Likewise. (vex_scalar_mode): Likewise. (vex_len_table): Duplcate entries for VEX_LEN_10_P_1, VEX_LEN_10_P_3, VEX_LEN_11_P_1, VEX_LEN_11_P_3, VEX_LEN_2A_P_1, VEX_LEN_2A_P_3, VEX_LEN_2C_P_3, VEX_LEN_2D_P_1, VEX_LEN_2E_P_0, VEX_LEN_2E_P_2, VEX_LEN_2F_P_2, VEX_LEN_51_P_1, VEX_LEN_51_P_3, VEX_LEN_52_P_1, VEX_LEN_53_P_1, VEX_LEN_58_P_1, VEX_LEN_58_P_3, VEX_LEN_59_P_1, VEX_LEN_5A_P_1, VEX_LEN_5A_P_3, VEX_LEN_5C_P_1, VEX_LEN_5C_P_3, VEX_LEN_5D_P_1, VEX_LEN_5D_P_3, VEX_LEN_5E_P_1, VEX_LEN_5E_P_3, VEX_LEN_5F_P_1, VEX_LEN_5F_P_3, VEX_LEN_6E_P_2, VEX_LEN_7E_P_1, VEX_LEN_7E_P_2, VEX_LEN_D6_P_2, VEX_LEN_C2_P_1, VEX_LEN_C2_P_3, VEX_LEN_3A0A_P_2 and VEX_LEN_3A0B_P_2. (vex_w_table): Update entries for VEX_W_10_P_1, VEX_W_10_P_3, VEX_W_11_P_1, VEX_W_11_P_3, VEX_W_2E_P_0, VEX_W_2E_P_2, VEX_W_2F_P_0, VEX_W_2F_P_2, VEX_W_51_P_1, VEX_W_51_P_3, VEX_W_52_P_1, VEX_W_53_P_1, VEX_W_58_P_1, VEX_W_58_P_3, VEX_W_59_P_1, VEX_W_59_P_3, VEX_W_5A_P_1, VEX_W_5A_P_3, VEX_W_5C_P_1, VEX_W_5C_P_3, VEX_W_5D_P_1, VEX_W_5D_P_3, VEX_W_5E_P_1, VEX_W_5E_P_3, VEX_W_5F_P_1, VEX_W_5F_P_3, VEX_W_7E_P_1, VEX_W_D6_P_2 VEX_W_C2_P_1, VEX_W_C2_P_3, VEX_W_3A0A_P_2 and VEX_W_3A0B_P_2. (intel_operand_size): Handle d_scalar_mode, d_scalar_swap_mode, q_scalar_mode, q_scalar_swap_mode. (OP_XMM): Handle scalar_mode. (OP_EX): Handle d_scalar_mode, d_scalar_swap_mode, q_scalar_mode and q_scalar_swap_mode. (OP_VEX): Handle vex_scalar_mode.
2010-01-24Remove trailing { Bad_Opcode }.H.J. Lu2-1/+4
2010-01-24Remove trailing { Bad_Opcode } in vex_len_table.H.J. Lu2-1/+4
2010-01-24 H.J. Lu <hongjiu.lu@intel.com> * i386-dis.c (vex_len_table): Remove trailing { Bad_Opcode }.
2010-01-24Remove trailing { Bad_Opcode }.H.J. Lu2-1/+4
2010-01-24 H.J. Lu <hongjiu.lu@intel.com> * i386-dis.c (prefix_table): Remove trailing { Bad_Opcode }.
2010-01-24Remove trailing "(bad)" entries and replace { "(bad)", { XX } }H.J. Lu2-3561/+2670
with { Bad_Opcode }. 2010-01-24 H.J. Lu <hongjiu.lu@intel.com> * i386-dis.c (Bad_Opcode): New. (bad_opcode): Likewise. (dis386): Replace { "(bad)", { XX } } with { Bad_Opcode }. (dis386_twobyte): Likewise. (reg_table): Likewise. (prefix_table): Likewise. (x86_64_table): Likewise. (vex_len_table): Likewise. (vex_w_table): Likewise. (mod_table): Likewise. (rm_table): Likewise. (float_reg): Likewise. (reg_table): Remove trailing "(bad)" entries. (prefix_table): Likewise. (x86_64_table): Likewise. (vex_len_table): Likewise. (vex_w_table): Likewise. (mod_table): Likewise. (rm_table): Likewise. (get_valid_dis386): Handle bytemode 0.
2010-01-24Replace "Vex" with "Vex=3" on AVX scalar instructions.H.J. Lu4-418/+428
2010-01-23 H.J. Lu <hongjiu.lu@intel.com> * i386-opc.h (VEXScalar): New. * i386-opc.tbl: Replace "Vex" with "Vex=3" on AVX scalar instructions. * i386-tbl.h: Regenerated.
2010-01-21Correct month.H.J. Lu1-1/+1
2010-01-21Add xsave64 and xrstor64.H.J. Lu4-3/+32
gas/testsuite/ 2010-02-21 H.J. Lu <hongjiu.lu@intel.com> * gas/i386/x86-64-xsave.s: Add tests for xsave64 and xrstor64. * gas/i386/x86-64-xsave-intel.d: Updated. * gas/i386/x86-64-xsave.d: Likewise. opcodes/ 2010-02-21 H.J. Lu <hongjiu.lu@intel.com> * i386-dis.c (mod_table): Use FXSAVE on xsave and xrstor. * i386-opc.tbl: Add xsave64 and xrstor64. * i386-tbl.h: Regenerated.
2010-01-20 PR 11170Nick Clifton2-3/+9
* arm-dis.c (print_arm_address): Do not ignore negative bit in PC based post-indexed addressing.
2010-01-152010-01-15 Sebastian Pop <sebastian.pop@amd.com>Sebastian Pop3-0/+1093
gas/ * config/tc-i386.c (md_assemble): Before accessing the IMM field check that it's not an XOP insn. gas/testsuite/ * gas/i386/x86-64-xop.d: Add missing patterns. * gas/i386/x86-64-xop.s: Same. * gas/i386/xop.d: Same. * gas/i386/xop.s: Same. opcodes/ * i386-opc.tbl: Support all the possible aliases for VPCOM* insns. * i386-tbl.h: Regenerated.
2010-01-14Replace VEX.DNS with VEX.NDS in comments.H.J. Lu2-2/+7
2010-01-14 H.J. Lu <hongjiu.lu@intel.com> * i386-opc.h (VexVVVV): Replace VEX.DNS with VEX.NDS in comments.
2010-01-14Add names_mm, names_xmm and names_ymm.H.J. Lu2-58/+130
2010-01-14 H.J. Lu <hongjiu.lu@intel.com> * i386-dis.c (names_mm): New. (intel_names_mm): Likewise. (att_names_mm): Likewise. (names_xmm): Likewise. (intel_names_xmm): Likewise. (att_names_xmm): Likewise. (names_ymm): Likewise. (intel_names_ymm): Likewise. (att_names_ymm): Likewise. (print_insn): Set names_mm, names_xmm and names_ymm. (OP_MMX): Use names_mm, names_xmm and names_ymm. (OP_XMM): Likewise. (OP_EM): Likewise. (OP_EMC): Likewise. (OP_MXC): Likewise. (OP_EX): Likewise. (XMM_Fixup): Likewise. (OP_VEX): Likewise. (OP_EX_VexReg): Likewise. (OP_Vex_2src): Likewise. (OP_Vex_2src_1): Likewise. (OP_Vex_2src_2): Likewise. (OP_REG_VexI4): Likewise.
2010-01-13Update commentsH.J. Lu2-3/+7
2010-01-13 H.J. Lu <hongjiu.lu@intel.com> * i386-dis.c (print_insn): Update comments.
2010-01-13Remove rex_originalH.J. Lu2-7/+8
2010-01-12 H.J. Lu <hongjiu.lu@intel.com> * i386-dis.c (rex_original): Removed. (ckprefix): Remove rex_original. (print_insn): Update comments.
2010-01-09Sync Libtool from GCC.Ralf Wildenhues3-434/+562
/: * libtool.m4: Sync from git Libtool. * ltmain.sh: Likewise. * ltoptions.m4: Likewise. * ltversion.m4: Likewise. * lt~obsolete.m4: Likewise. sim/iq2000/: * configure: Regenerate. sim/d10v/: * configure: Regenerate. sim/m32r/: * configure: Regenerate. sim/frv/: * configure: Regenerate. sim/: * avr/configure: Regenerate. * cris/configure: Regenerate. * microblaze/configure: Regenerate. sim/h8300/: * configure: Regenerate. sim/mn10300/: * configure: Regenerate. sim/erc32/: * configure: Regenerate. sim/arm/: * configure: Regenerate. sim/m68hc11/: * configure: Regenerate. sim/lm32/: * configure: Regenerate. sim/sh64/: * configure: Regenerate. sim/v850/: * configure: Regenerate. sim/cr16/: * configure: Regenerate. sim/moxie/: * configure: Regenerate. sim/m32c/: * configure: Regenerate. sim/mips/: * configure: Regenerate. sim/mcore/: * configure: Regenerate. sim/sh/: * configure: Regenerate. gprof/: * Makefile.in: Regenerate. * configure: Regenerate. opcodes/: * Makefile.in: Regenerate. * configure: Regenerate. gas/: * Makefile.in: Regenerate. * configure: Regenerate. * doc/Makefile.in: Regenerate. ld/: * configure: Regenerate. gdb/testsuite/: * gdb.cell/configure: Regenerate. binutils/: * Makefile.in: Regenerate. * configure: Regenerate. * doc/Makefile.in: Regenerate. bfd/: * Makefile.in: Regenerate. * configure: Regenerate. bfd/doc/: * Makefile.in: Regenerate.
2010-01-07 * cgen-ibld.in (insert_normal, extract_normal): Minor cleanup.Doug Evans14-39/+47
* fr30-ibld.c, * frv-ibld.c, * ip2k-ibld.c, * iq2000-ibld.c, * lm32-ibld.c, * m32c-ibld.c, * m32r-ibld.c, * mep-ibld.c, * mt-ibld.c, * openrisc-ibld.c, * xc16x-ibld.c, * xstormy16-ibld.c: Regenerate.
2010-01-062010-01-06 Quentin Neill <quentin.neill@amd.com>Sebastian Pop3-0/+12
gas/ * config/tc-i386.c (cpu_arch): Add amdfam15. (i386_align_code): Add PROCESSOR_AMDFAM15 cases. * config/tc-i386.h (processor_type): Add PROCESSOR_AMDFAM15. * doc/c-i386.texi: Add amdfam15. opcodes/ * i386-gen.c (cpu_flag_init): Add new CPU_AMDFAM15_FLAGS. * i386-init.h: Regenerated. testsuite/ * gas/i386/i386.exp: Add new amdfam15 test cases. * gas/i386/nops-1-amdfam15.d: New.
2010-01-06 * arm-dis.c (print_insn): Fixed search for nextNick Clifton2-3/+11
symbol and data dumping condition, and the initial mapping symbol state. * gas/arm/dis-data.d: New test case. * gas/arm/dis-data.s: New file.
2010-01-06 cpu/Doug Evans14-188/+209
* m32c.cpu (f-dsp-32-u24): Fix mode of extract handler. (f-dsp-40-u20, f-dsp-40-u24): Ditto. opcodes/ * cgen-ibld.in: #include "cgen/basic-modes.h". * fr30-ibld.c, * frv-ibld.c, * ip2k-ibld.c, * iq2000-ibld.c, * lm32-ibld.c, * m32c-ibld.c, * m32r-ibld.c, * mep-ibld.c, * mt-ibld.c, * openrisc-ibld.c, * xc16x-ibld.c, * xstormy16-ibld.c: Regenerate.
2010-01-04 PR 11123Nick Clifton2-1/+6
* arm-dis.c (print_insn_coprocessor): Initialise value.
2010-01-04bfd/Alan Modra2-1/+10
* archures.c: Add bfd_mach_ppc_e500mc64. * bfd-in2.h: Regenerate. * cpu-powerpc.c (bfd_powerpc_archs): Add entry for bfd_mach_ppc_e500mc64. gas/ * config/tc-ppc.c (md_show_usage): Document -me500mc64. opcodes/ * ppc-dis.c (ppc_opts): Add entry for "e500mc64".
2010-01-02 * cgen-asm.in: Update copyright year.Doug Evans90-89/+115
* cgen-dis.in: Update copyright year. * cgen-ibld.in: Update copyright year. * fr30-asm.c, * fr30-desc.c, * fr30-desc.h, * fr30-dis.c, * fr30-ibld.c, * fr30-opc.c, * fr30-opc.h, * frv-asm.c, * frv-desc.c, * frv-desc.h, * frv-dis.c, * frv-ibld.c, * frv-opc.c, * frv-opc.h, * ip2k-asm.c, * ip2k-desc.c, * ip2k-desc.h, * ip2k-dis.c, * ip2k-ibld.c, * ip2k-opc.c, * ip2k-opc.h, * iq2000-asm.c, * iq2000-desc.c, * iq2000-desc.h, * iq2000-dis.c, * iq2000-ibld.c, * iq2000-opc.c, * iq2000-opc.h, * lm32-asm.c, * lm32-desc.c, * lm32-desc.h, * lm32-dis.c, * lm32-ibld.c, * lm32-opc.c, * lm32-opc.h, * lm32-opinst.c, * m32c-asm.c, * m32c-desc.c, * m32c-desc.h, * m32c-dis.c, * m32c-ibld.c, * m32c-opc.c, * m32c-opc.h, * m32r-asm.c, * m32r-desc.c, * m32r-desc.h, * m32r-dis.c, * m32r-ibld.c, * m32r-opc.c, * m32r-opc.h, * m32r-opinst.c, * mep-asm.c, * mep-desc.c, * mep-desc.h, * mep-dis.c, * mep-ibld.c, * mep-opc.c, * mep-opc.h, * mt-asm.c, * mt-desc.c, * mt-desc.h, * mt-dis.c, * mt-ibld.c, * mt-opc.c, * mt-opc.h, * openrisc-asm.c, * openrisc-desc.c, * openrisc-desc.h, * openrisc-dis.c, * openrisc-ibld.c, * openrisc-opc.c, * openrisc-opc.h, * xc16x-asm.c, * xc16x-desc.c, * xc16x-desc.h, * xc16x-dis.c, * xc16x-ibld.c, * xc16x-opc.c, * xc16x-opc.h, * xstormy16-asm.c, * xstormy16-desc.c, * xstormy16-desc.h, * xstormy16-dis.c, * xstormy16-ibld.c, * xstormy16-opc.c, * xstormy16-opc.h: Regenerate.
2010-01-01Move 2009 binutils ChangeLog to ChangeLog-2009.H.J. Lu2-1793/+1802
2009-12-19Replace VexNDS, VexNDD and VexLWP with VexVVVV.H.J. Lu5-4351/+4374
gas/ 2009-12-19 H.J. Lu <hongjiu.lu@intel.com> * config/tc-i386.c (process_operands): Check vexvvvv instead of vexnds and vexndd. (build_modrm_byte): Check vexvvvv instead of vexnds, vexndd and vexlwp. opcodes/ 2009-12-19 H.J. Lu <hongjiu.lu@intel.com> * i386-gen.c (opcode_modifiers): Remove VexNDS, VexNDD and VexLWP. Add VexVVVV. * i386-opc.h (VexNDS): Removed. (VexNDD): Likewise. (VexLWP): Likewise. (VEXXDS): New. (VEXNDD): Likewise. (VEXLWP): Likewise. (VexVVVV): Likewise. (i386_opcode_modifier): Remove vexnds, vexndd and vexlwp. Add vexvvvv. * i386-opc.tbl: Replace VexNDS with VexVVVV=1, VexNDD with VexVVVV=2 and VexLWP with VexVVVV=3. * i386-tbl.h: Regenerated.
2009-12-18Move Imm1 before Imm8.H.J. Lu2-1/+5
2009-12-18 H.J. Lu <hongjiu.lu@intel.com> * i386-gen.c (operand_types): Move Imm1 before Imm8.
2009-12-17 PR binutils/10924Nick Clifton2-206/+289
* config/tc-arm.c (do_ldstv4): Do not allow r15 as the destination register. (do_mrs): Likewise. (do_mul): Likewise. * arm-dis.c: Add support for %<>ru and %<>rU formats to enforce unique register numbers. Extend support for %<>R format to thumb32 and coprocessor instructions. * gas/arm/unpredictable.s: Add more unpredictable instructions. * gas/arm/unpredictable.d: Add expected disassemblies.
2009-12-16Remove ByteOkIntel.H.J. Lu5-3826/+3832
gas/ 2009-12-16 H.J. Lu <hongjiu.lu@intel.com> * config/tc-i386.c (process_suffix): Set i.suffix to 0 in Intel syntax if size is ignored and b/l/w suffixes are illegal. (check_byte_reg): Remove byteokintel check. opcodes/ 2009-12-16 H.J. Lu <hongjiu.lu@intel.com> * i386-gen.c (opcode_modifiers): Remove ByteOkIntel. * i386-opc.h (ByteOkIntel): Removed. (i386_opcode_modifier): Remove byteokintel. * i386-opc.tbl: Remove ByteOkIntel. * i386-tbl.h: Regenerated.
2009-12-16Replace Vex0F, Vex0F38, Vex0F3A, XOP08, XOP09 and XOP0A with VexOpcode.H.J. Lu5-3569/+3585
gas/ 2009-12-16 H.J. Lu <hongjiu.lu@intel.com> * config/tc-i386.c (build_vex_prefix): Replace vex0f, vex0f38, vex0f3a, xop08, xop09 and xop0a with vexopcode. opcodes/ 2009-12-16 H.J. Lu <hongjiu.lu@intel.com> * i386-gen.c (opcode_modifiers): Remove Vex0F, Vex0F38, Vex0F3A, XOP08, XOP09 and XOP0A. Add VexOpcode. * i386-opc.h (Vex0F): Removed. (Vex0F38): Likewise. (Vex0F3A): Likewise. (VexOpcode): New. (VEX0F): Likewise. (VEX0F38): Likewise. (VEX0F3A): Likewise. (XOP08): Defined as a macro. (XOP09): Likewise. (XOP0A): Likewise. (i386_opcode_modifier): Remove vex0f, vex0f38, vex0f3a, xop08, xop09 and xop0a. Add vexopcode. * i386-opc.tbl: Replace Vex0F with VexOpcode=0, Vex0F38 with VexOpcode=1, Vex0F3A with VexOpcode=2, XOP08 with VexOpcode=3, XOP09 with VexOpcode=4 and XOP0A with VexOpcode=5. * i386-tbl.h: Regenerated.
2009-12-16Fix a typo in ChangeLog.H.J. Lu1-1/+1
2009-12-16Replace VEX2SOURCES with XOP2SOURCES.H.J. Lu2-3/+8
gas/ 2009-12-15 H.J. Lu <hongjiu.lu@intel.com> * config/tc-i386.c (build_modrm_byte): Check XOP2SOURCES instead VEX2SOURCES. opcodes/ 2009-12-15 H.J. Lu <hongjiu.lu@intel.com> * i386-opc.h (VEX2SOURCES): Renamed to ... (XOP2SOURCES): This.
2009-12-16Replace Vex2Sources and Vex3Sources with VexSources.H.J. Lu5-2522/+2540
gas/ 2009-12-15 H.J. Lu <hongjiu.lu@intel.com> * config/tc-i386.c (process_operands): Check vexsources instead of vex3sources. (build_modrm_byte): Check vexsources instead of vex2sources and vex3sources. opcodes/ 2009-12-15 H.J. Lu <hongjiu.lu@intel.com> * i386-gen.c (opcode_modifiers): Remove Vex3Sources and Vex2Sources. Add VexSources. * i386-opc.h ()Vex2Sources: Removed. (Vex3Sources): Likewise. (VEX2SOURCES): New. (VEX3SOURCES): Likewise. (VexSources): Likewise. (i386_opcode_modifier): Remove vex2sources and vex3sources. Add vexsources. * i386-opc.tbl: Replace Vex2Sources with VexSources=1 and Vex3Sourceswith VexSources=2. * i386-tbl.h: Regenerated.
2009-12-16Remove VexW0 and VexW1. Add VexW.H.J. Lu5-3500/+3519
gas/ 2009-12-15 H.J. Lu <hongjiu.lu@intel.com> * config/tc-i386.c (build_vex_prefix): Replace vexw0/vexw1 with vexw. (build_modrm_byte): Likewise. opcodes/ 2009-12-15 H.J. Lu <hongjiu.lu@intel.com> * i386-gen.c (opcode_modifiers): Remove VexW0 and VexW1. Add VexW. * i386-opc.h (VexW0): Removed. (VexW1): Likewise. (VEXW0): New. (VEXW1): Likewise. (VexW): Likewise. (i386_opcode_modifier): Remove vexw0 and vexw1. Add vexw. * i386-opc.tbl: Replace VexW0 with VexW=1 and VexW1 with Vex=2. * i386-init.h: Regenerated. * i386-tbl.h: Likewise.
2009-12-15Add VEX_W_3818_P_2_M_0.H.J. Lu2-1/+13
2009-12-15 H.J. Lu <hongjiu.lu@intel.com> * i386-dis.c (VEX_W_3818_P_2_M_0): New. (vex_w_table): Add VEX_W_3818_P_2_M_0. (mod_table): Use VEX_W_3818_P_2_M_0.
2009-12-15Reformat vex_w_table.H.J. Lu2-2/+6
2009-12-15 H.J. Lu <hongjiu.lu@intel.com> * i386-dis.c (vex_w_table): Reformat.
2009-12-15Add VEX_W_382X_P_2_M_0.H.J. Lu2-4/+34
2009-12-15 H.J. Lu <hongjiu.lu@intel.com> * i386-dis.c (VEX_W_382X_P_2_M_0): New. (vex_w_table): Add VEX_W_382X_P_2_M_0. (mod_table): Use VEX_W_382X_P_2_M_0.
2009-12-15Reformat vex_w_table.H.J. Lu2-3/+7
2009-12-15 H.J. Lu <hongjiu.lu@intel.com> * i386-dis.c (vex_w_table): Reformat.
2009-12-15Add USE_VEX_W_TABLE, VEX_W_TABLE and VEX_W_XXX.H.J. Lu4-1987/+3507
2009-12-15 H.J. Lu <hongjiu.lu@intel.com> * i386-dis.c (USE_VEX_W_TABLE): New. (VEX_W_TABLE): Likewise. (VEX_W_XXX): Likewise. (vex_w_table): Likewise. (prefix_table): Use VEX_W_XXX. (vex_table): Likewise. (vex_len_table): Likewise. (mod_table): Likewise. (get_valid_dis386): Handle USE_VEX_W_TABLE. * i386-opc.tbl: Add VexW0 to AVX instructions where the VEX.W bit isn't used. * i386-tbl.h: Regenerated.
2009-12-15Define VEX128 and VEX256.H.J. Lu2-0/+7
gas/ 2009-12-15 H.J. Lu <hongjiu.lu@intel.com> * config/tc-i386.c (build_vex_prefix): Use VEX256. opcodes/ 2009-12-15 H.J. Lu <hongjiu.lu@intel.com> * i386-opc.h (VEX128): New. (VEX256): Likewise.
2009-12-15Reformat vex_len_table.H.J. Lu2-4/+10
2009-12-14 H.J. Lu <hongjiu.lu@intel.com> * i386-dis.c (vex_len_table): Reformat.
2009-12-14Rename MOD_VEX_51 to MOD_VEX_50.H.J. Lu2-3/+10
2009-12-14 H.J. Lu <hongjiu.lu@intel.com> * i386-dis.c (MOD_VEX_51): Renamed to ... (MOD_VEX_50): This. (vex_table): Updated. (mod_table): Likewise.
2009-12-14 PR binutils/10924Nick Clifton2-24/+52
* arm-dis.c (arm_opcodes): Specify %R in cases where using r15 results in unpredictable behaviour. (print_insn_arm): Handle %R. * gas/arm/unpredictable.s: New test case - checks the disassembly of instructions with unpredictable behaviour. * gas/arm/unpredictable.d: New file - expected disassembly.
2009-12-12Set vex.w to 0 for VEX C5 prefix.H.J. Lu2-1/+8
2009-12-11 H.J. Lu <hongjiu.lu@intel.com> * i386-dis.c (get_valid_dis386): Set vex.w to 0 for VEX C5 prefix. (print_insn): Don't set vex.w here.
2009-12-122009-12-11 H.J. Lu <hongjiu.lu@intel.com>H.J. Lu2-0/+5
* i386-dis.c (print_insn): Set vex.w to 0.
2009-12-112009-12-11 Quentin Neill <quentin.neill@amd.com>Sebastian Pop2-54/+69
gas/testsuite/ * gas/i386/fma4.d: Add test cases. * gas/i386/fma4.s: Add test cases. * gas/i386/x86-64-fma4.d: Add test cases. * gas/i386/x86-64-fma4.s: Add test cases. opcodes/ * i386-dis.c (get_vex_imm8): Extend logic to apply in all cases, to avoid fetching ahead for the immediate bytes when OP_E_memory has already been called. Fix indentation.
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