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2019-11-07x86: support further AMD Zen2 instructionsJan Beulich7-4080/+4160
2019-11-07x86: adjust register names printed for MONITOR/MWAITJan Beulich2-16/+20
2019-11-07x86/Intel: drop IgnoreSize from operand-less MOVSD/CMPSD againJan Beulich3-4/+11
2019-11-05x86: fold OP_Mwaitx() into OP_Mwait()Jan Beulich2-24/+11
2019-11-05x86: split MONITORX/MWAITX entriesJan Beulich2-2/+21
2019-11-05x86: consolidate disassembler enum naming a littleJan Beulich2-75/+130
2019-11-04Fix potential array overruns when disassembling corrupt v850 binaries.Nick Clifton2-60/+129
2019-10-30Modify the ARNM assembler to accept the omission of the immediate argument fo...Delia Burduv4-3/+15
2019-10-30x86: re-do "shorthand" handlingJan Beulich4-219/+214
2019-10-30x86: slightly rearrange struct insn_templateJan Beulich4-3918/+3925
2019-10-30x86: drop stray WJan Beulich5-19/+54
2019-10-29Fix array overrun when disassembling corrupt TIC30 binaries.Nick Clifton2-1/+5
2019-10-29Fix a potential illegal array access in the D30V disassembler.Nick Clifton2-1/+9
2019-10-29Prevent a left shift by a negative value when disassembling IA64 binaries.Nick Clifton2-3/+11
2019-10-29Fix array overruns in the S12Z disassembler.Nick Clifton3-16/+56
2019-10-28Fix potentially illegal shift and assign operation in CSKY disassembler.Nick Clifton2-2/+7
2019-10-28Fix buffer overrun in TIC30 disassembler.Nick Clifton2-7/+27
2019-10-28Stop potential illegal memory access in the NS32K disassembler.Nick Clifton2-1/+17
2019-10-28Prevent an illegal memory access in the xgate disassembler.Nick Clifton2-3/+8
2019-10-25Fix potential undefined behaviour in the RX disassembler.Nick Clifton2-1/+6
2019-10-23Fix typo in RX disassembler error messages.Nick Clifton2-10/+19
2019-10-22Prevent more potential illegal memory accesses in the RX disassembler.Nick Clifton2-16/+41
2019-10-16Fix potential illegal memory access when disassembling corrupt RX binaries.Nick Clifton2-15/+92
2019-10-09Fix the disassembly of the LDS and STS instructions of the AVR architecture.Nick Clifton2-0/+8
2019-10-08S/390: Add support for z15 as CPU name.Andreas Krebbel1-1/+2
2019-10-07x86/Intel: correct MOVSD and CMPSD handlingJan Beulich3-12/+18
2019-09-23m68k bfd.h tidyAlan Modra2-1/+5
2019-09-23mips bfd.h tidyAlan Modra2-2/+8
2019-09-20x86-64: fix handling of PUSH/POP of segment registerJan Beulich3-4/+39
2019-09-19bfd_section_* macrosAlan Modra2-1/+5
2019-09-18Re-generate many configure and Makefile.in filesSimon Marchi3-16/+8
2019-09-17RISC-V: Gate opcode tables by enum rather than string.Jim Wilson2-658/+664
2019-09-16Update version to 2.33.50 and regenerate configure scripts.Phil Blundell2-10/+14
2019-09-10Use the correct alias for the M68K tdiv instruction.Miod Vallat2-2/+7
2019-09-09Add markers for 2.33 branch to NEWS and ChangeLog files.Phil Blundell1-0/+4
2019-09-03Fix buffer underrun bug in the TI C30 disassembler.Nick Clifton2-1/+9
2019-09-03Fix a potential buffer overrun in the MMIX disassembler when processing a cor...Nick Clifton2-37/+66
2019-08-27Add support for the MVE VMOV instruction to the ARM assembler. This instruct...Srinath Parvathaneni2-0/+29
2019-08-22[AArch64][gas] Update MTE system register encodingsKyrylo Tkachov2-10/+16
2019-08-12Modify the ARM encoding and decoding of SQRSHRL and UQRSHLL MVE instructions.Srinath Parvathaneni2-4/+17
2019-08-07Prevent objdump from aborting when asked to disassemble an unknown type of AR...Phillipe Antoine2-6/+19
2019-08-07x86: drop stray FloatMFJan Beulich3-14/+21
2019-08-05Removes support in the ARM assembler for the unsigned variants of the VQ(R)DM...Barnaby Wilks2-4/+9
2019-07-30RISC-V: Fix minor issues with FP csr instructions.Jim Wilson2-16/+24
2019-07-24[ARC] Update disassembler opcode selectionClaudiu Zissulescu2-1/+30
2019-07-24[ARC] Update ARC opcode tableClaudiu Zissulescu4-1461/+2256
2019-07-23[AArch64] Add support for GMID_EL1 register for +memtagKyrylo Tkachov2-1/+8
2019-07-23Add Changelog entry missing from previous delta.Nick Clifton1-0/+5
2019-07-22This patch addresses the change in the June Armv8.1-M Mainline specification,...Barnaby Wilks1-4/+0
2019-07-19cpu,opcodes,gas: use %r0 and %r6 instead of %a and %ctf in eBPF disassemblerJose E. Marchesi2-4/+8
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