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2024-09-12s390: Relax risbg[n]z, risb{h|l}gz, {rns|ros|rxs}bgt operand constraintsJens Remus1-15/+9
2024-09-12s390: Simplify (dis)assembly of insn operands with const bitsJens Remus2-23/+17
2024-09-11x86/APX: correct disassembly for EVEX.B4Jan Beulich1-2/+3
2024-09-09s390: Align opcodes to lower-caseJens Remus1-1/+1
2024-09-06x86/APX: use D for 2-operand CFCMOVccJan Beulich2-577/+276
2024-09-06x86/APX: optimize certain reg-only CFCMOVcc formsJan Beulich2-31/+31
2024-09-06x86: templatize VNNI templatesJan Beulich2-46/+37
2024-09-03RISC-V: Add support for XCVsimd extension in CV32E40PMary Bennett2-0/+231
2024-09-02Support ymm rounding control for Intel AVX10.2Haochen Jiang6-629/+666
2024-08-30x86/APX: drop %SW disassembler macro againJan Beulich2-17/+19
2024-08-30x86: limit RegRex64 useJan Beulich2-48/+48
2024-08-27RISC-V: PR32036, Support Zcmp cm.mva01s and cm.mvsa01 instructions.Jiawei2-0/+28
2024-08-16opcodes/cgen: drop trailing whitespace also for crisJan Beulich2-48/+48
2024-08-12Revert "gas: have scrubber retain more whitespace"H.J. Lu14-447/+234
2024-08-09gas: have scrubber retain more whitespaceJan Beulich14-234/+447
2024-08-09gas: sparc: Fix faligndatai assembly and disassemblyRichard Henderson1-1/+1
2024-08-06RISC-V: map zext.h to pack/packw if Zbkb is enabledHau Hsu1-2/+2
2024-08-06RISC-V: Add support for XCvBitmanip extension in CV32E40PMary Bennett2-0/+27
2024-08-06RISC-V: Add support for Zcmop extensionXiao Zeng1-0/+10
2024-08-06RISC-V: Add support for Zimop extensionXiao Zeng1-0/+42
2024-07-29Updated translations for the bfd, binutils, gas, ld and opcodes directoriesNick Clifton3-557/+573
2024-07-26microMIPS: Add MT ASE instruction set supportYunQiang Su2-1/+61
2024-07-26x86/APX: optimize certain {nf}-form insns to BMI2 onesJan Beulich2-27/+27
2024-07-26ARM print_insn_mve assertionAlan Modra1-17/+2
2024-07-24opcodes/x86: fix minor missed styling caseAndrew Burgess1-2/+2
2024-07-20Change version to 2.43.50Nick Clifton2-193/+195
2024-07-20Add markers for 2.43 branch/releaseNick Clifton1-0/+4
2024-07-19MIPS/opcodes: Replace "y" microMIPS operand code with "x"Maciej W. Rozycki1-2/+2
2024-07-19MIPS/opcodes: Mark MT thread context move assembly idioms as aliasesMaciej W. Rozycki1-38/+38
2024-07-19MIPS/opcodes: Mark PAUSE as an aliasMaciej W. Rozycki1-1/+1
2024-07-19MIPS/opcodes: Reorder coprocessor moves alphabeticallyMaciej W. Rozycki2-58/+62
2024-07-19MIPS/opcodes: Make AL a shorthand for INSN2_ALIASMaciej W. Rozycki2-56/+60
2024-07-19MIPS/opcodes: Rename the AL membership shorthand to ALXMaciej W. Rozycki1-88/+88
2024-07-19MIPS/opcodes: Remove the regular MIPS "+t" operand codeYunQiang Su1-2/+1
2024-07-19MIPS/opcodes: Output thread context registers numerically with MFTR/MTTRMaciej W. Rozycki1-2/+2
2024-07-19MIPS/opcodes: Exclude $0 from "-x" R6 operand typeMaciej W. Rozycki1-1/+1
2024-07-18opcodes: aarch64: enforce checks on subclass flags in aarch64-gen.cIndu Bhagat1-0/+19
2024-07-18opcodes: aarch64: denote subclasses for insns of iclass dp_2srcIndu Bhagat1-24/+24
2024-07-18opcodes: aarch64: add flags to denote subclasses of uncond branchesIndu Bhagat1-19/+19
2024-07-18opcodes: aarch64: add flags to denote subclasses of arithmetic insnsIndu Bhagat1-15/+15
2024-07-18opcodes: aarch64: add flags to denote subclasses of ldst insnsIndu Bhagat1-43/+43
2024-07-12aarch64: Add support for sme2.1 zero instructions.Srinath Parvathaneni3-208/+330
2024-07-12aarch64: Add support for sme2.1 movaz instructions.Srinath Parvathaneni10-283/+493
2024-07-12aarch64: Add support for sme2.1 luti2 and luti4 instructions.Srinath Parvathaneni4-210/+274
2024-07-08aarch64: Add support for sve2p1 pmov instruction.srinath6-221/+409
2024-07-08aarch64: Add support for sve2p1 tbxq instruction.Srinath Parvathaneni2-158/+170
2024-07-08aarch64: Add support for sve2p1 zipq[1-2] instructions.Srinath Parvathaneni2-160/+184
2024-07-08aarch64: Add support for sve2p1 uzpq[1-2] instructions.Srinath Parvathaneni2-151/+175
2024-07-08aarch64: Add support for sve2p1 tblq instruction.Srinath Parvathaneni2-175/+187
2024-07-08aarch64: Add support for sve2p1 orqv instruction.Srinath Parvathaneni2-152/+164
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