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AgeCommit message (Expand)AuthorFilesLines
2023-05-10cpu: add V3 BPF atomic instructionsJose E. Marchesi5-14/+451
2023-05-10opcodes: use CGEN_INSN_LGUINT for base instructionsJose E. Marchesi17-19/+38
2023-04-26 RISC-V: Support XVentanaCondOps extensionPhilipp Tomsich1-0/+4
2023-04-26i386-dis.c UB shift and other tidiesAlan Modra1-94/+76
2023-04-24Revert "x86: work around compiler diagnosing dangling pointer"Alan Modra1-6/+0
2023-04-24gcc-13 i386-dis.c warningAlan Modra1-16/+31
2023-04-24x86: work around compiler diagnosing dangling pointerJan Beulich1-0/+6
2023-04-21Fix -Wmaybe-uninitialized warning in opcodes/i386-dis.cTom Tromey2-1/+6
2023-04-21x86: drop (explicit) BFD64 dependency from disassemblerJan Beulich1-13/+4
2023-04-21x86: drop use of setjmp() from disassemblerJan Beulich1-5/+0
2023-04-21x86: change fetch error handling for get<N>()Jan Beulich1-133/+114
2023-04-21x86: change fetch error handling when processing operandsJan Beulich1-233/+276
2023-04-21x86: change fetch error handling in get_valid_dis386()Jan Beulich1-30/+26
2023-04-21x86: change fetch error handling in ckprefix()Jan Beulich1-12/+20
2023-04-21x86: change fetch error handling in top-level functionJan Beulich1-13/+59
2023-04-21x86: move fetch error handling into a helper functionJan Beulich1-28/+35
2023-04-18RISC-V: Cache the latest mapping symbol and its boundary.Kito Cheng1-0/+43
2023-04-12arc: remove faulty instructionsClaudiu Zissulescu2-720/+6
2023-04-11Fix illegal memory access when disassembling corrupt NFP binaries.Nick Clifton2-1/+9
2023-04-07Support Intel AMX-COMPLEXHaochen Jiang7-4711/+4808
2023-04-03asan: csky floatformat_to_double uninitialised valueAlan Modra1-10/+6
2023-04-03opcodes/arm: adjust whitespace in cpsie instructionAndrew Burgess1-2/+2
2023-03-31RISC-V: Allocate "various" operand typeTsukasa OI2-8/+24
2023-03-31x86: parse VEX and alike specifiers for .insnJan Beulich1-0/+2
2023-03-31x86: introduce .insn directiveJan Beulich3-0/+5
2023-03-30aarch64: Add the RPRFM instructionRichard Sandiford6-885/+925
2023-03-30aarch64: Add the SVE FCLAMP instructionRichard Sandiford2-759/+771
2023-03-30aarch64: Add new SVE shift instructionsRichard Sandiford2-873/+909
2023-03-30aarch64: Add new SVE saturating conversion instructionsRichard Sandiford2-752/+788
2023-03-30aarch64: Add new SVE dot-product instructionsRichard Sandiford6-841/+923
2023-03-30aarch64: Add the SVE BFMLSL instructionsRichard Sandiford2-742/+793
2023-03-30aarch64: Add the SME2 UZP and ZIP instructionsRichard Sandiford2-338/+438
2023-03-30aarch64: Add the SME2 UNPK instructionsRichard Sandiford2-709/+757
2023-03-30aarch64: Add the SME2 shift instructionsRichard Sandiford9-505/+679
2023-03-30aarch64: Add the SME2 saturating conversion instructionsRichard Sandiford6-468/+592
2023-03-30aarch64: Add the SME2 FP<->FP conversion instructionsRichard Sandiford2-948/+1000
2023-03-30aarch64: Add the SME2 FP<->int conversion instructionsRichard Sandiford2-749/+945
2023-03-30aarch64: Add the SME2 CLAMP instructionsRichard Sandiford2-820/+892
2023-03-30aarch64: Add the SME2 MOPA and MOPS instructionsRichard Sandiford2-717/+789
2023-03-30aarch64: Add the SME2 vertical dot-product instructionsRichard Sandiford2-669/+789
2023-03-30aarch64: Add the SME2 dot-product instructionsRichard Sandiford2-753/+1353
2023-03-30aarch64: Add the SME2 MLALL and MLSLL instructionsRichard Sandiford6-851/+1599
2023-03-30aarch64: Add the SME2 MLAL and MLSL instructionsRichard Sandiford8-665/+1485
2023-03-30aarch64: Add the SME2 FMLA and FMLS instructionsRichard Sandiford6-529/+753
2023-03-30aarch64: Add the SME2 maximum/minimum instructionsRichard Sandiford4-439/+979
2023-03-30aarch64: Add the SME2 ADD and SUB instructionsRichard Sandiford8-487/+750
2023-03-30aarch64: Add the SME2 ZT0 instructionsRichard Sandiford8-397/+686
2023-03-30aarch64: Add the SME2 predicate-related instructionsRichard Sandiford10-821/+1270
2023-03-30aarch64: Add the SME2 multivector LD1 and ST1 instructionsRichard Sandiford10-448/+2088
2023-03-30aarch64: Add the SME2 MOVA instructionsRichard Sandiford10-312/+674
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