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2018-01-23Enable Intel PCONFIG instruction.Igor Tsimbalist7-5483/+5529
Intel has disclosed a set of new instructions for Icelake processor. The spec is https://software.intel.com/sites/default/files/managed/c5/15/architecture-instruction-set-extensions-programming-reference.pdf This patch enables Intel PCONFIG instruction. gas/ * config/tc-i386.c (cpu_arch): Add .pconfig. * doc/c-i386.texi: Document .pconfig. * testsuite/gas/i386/i386.exp: Add PCONFIG tests. * testsuite/gas/i386/pconfig-intel.d: New test. * testsuite/gas/i386/pconfig.d: Likewise. * testsuite/gas/i386/pconfig.s: Likewise. * testsuite/gas/i386/x86-64-pconfig-intel.d: Likewise. * testsuite/gas/i386/x86-64-pconfig.d: Likewise. * testsuite/gas/i386/x86-64-pconfig.s: Likewise. opcodes/ * i386-dis.c (enum): Add pconfig. * i386-gen.c (cpu_flag_init): Add CPU_PCONFIG_FLAGS. (cpu_flags): Add CpuPCONFIG. * i386-opc.h (enum): Add CpuPCONFIG. (i386_cpu_flags): Add cpupconfig. * i386-opc.tbl: Add PCONFIG instruction. * i386-init.h: Regenerate. * i386-tbl.h: Likewise.
2018-01-23Enable Intel WBNOINVD instruction.Igor Tsimbalist7-5483/+5535
Intel has disclosed a set of new instructions for Icelake processor. The spec is https://software.intel.com/sites/default/files/managed/c5/15/architecture-instruction-set-extensions-programming-reference.pdf This patch enables Intel WBNOINVD instruction. gas/ * config/tc-i386.c (cpu_arch): Add .wbnoinvd. * doc/c-i386.texi: Document .wbnoinvd. * testsuite/gas/i386/i386.exp: Add WBNOINVD tests. * testsuite/gas/i386/wbnoinvd-intel.d: New test. * testsuite/gas/i386/wbnoinvd.d: Likewise. * testsuite/gas/i386/wbnoinvd.s: Likewise. * testsuite/gas/i386/x86-64-wbnoinvd-intel.d: Likewise. * testsuite/gas/i386/x86-64-wbnoinvd.d: Likewise. * testsuite/gas/i386/x86-64-wbnoinvd.s: Likewise. opcodes/ * i386-dis.c (enum): Add PREFIX_0F09. * i386-gen.c (cpu_flag_init): Add CPU_WBNOINVD_FLAGS. (cpu_flags): Add CpuWBNOINVD. * i386-opc.h (enum): Add CpuWBNOINVD. (i386_cpu_flags): Add cpuwbnoinvd. * i386-opc.tbl: Add WBNOINVD instruction. * i386-init.h: Regenerate. * i386-tbl.h: Likewise.
2018-01-17RISC-V: Fix bug in prior addi/c.nop patch.Jim Wilson2-1/+5
gas/ * config/tc-riscv.c (validate_riscv_insn) <'z'>: New. (riscv_ip) <'z'>: New. opcodes/ * riscv-opc.c (riscv_opcodes) <addi>: Use z instead of 0.
2018-01-17Replace CET bit with IBT and SHSTK bits.Igor Tsimbalist6-5557/+5602
The latest specification for Intel CET technology defined two new bits instead of previously used CET bit. These are IBT and SHSTK bits. The patch replaces CET bit with IBT and SHSTK bits. gas/ * config/tc-i386.c (cpu_arch): Delete .cet. Add .ibt, .shstk. (cpu_noarch): Add noibt, noshstk. (parse_insn): Change cpucet to cpuibt. * doc/c-i386.texi: Delete .cet. Add .ibt, .shstk. * testsuite/gas/i386/cet-ibt-inval.l: New test. * testsuite/gas/i386/cet-ibt-inval.s: Likewise. * testsuite/gas/i386/cet-shstk-inval.l: Likewise. * testsuite/gas/i386/cet-shstk-inval.s: Likewise. * testsuite/gas/i386/x86-64-cet-ibt-inval.l: Likewise. * testsuite/gas/i386/x86-64-cet-ibt-inval.s: Likewise. * testsuite/gas/i386/x86-64-cet-shstk-inval.l: Likewise. * testsuite/gas/i386/x86-64-cet-shstk-inval.s: Likewise. opcodes/ * i386-gen.c (cpu_flag_init): Delete CPU_CET_FLAGS, CpuCET. Add CPU_IBT_FLAGS, CPU_SHSTK_FLAGS, CPY_ANY_IBT_FLAGS, CPU_ANY_SHSTK_FLAGS, CpuIBT, CpuSHSTK. (cpu_flags): Add CpuIBT, CpuSHSTK. * i386-opc.h (enum): Add CpuIBT, CpuSHSTK. (i386_cpu_flags): Add cpuibt, cpushstk. * i386-opc.tbl: Change CpuCET to CpuSHSTK and CpuIBT. * i386-init.h: Regenerate. * i386-tbl.h: Likewise.
2018-01-16Update translations for various binutils components.Nick Clifton3-596/+2117
ld * po/pt_BR.po: Updated Brazilian Portugese translation. opcodes * po/pt_BR.po: Updated Brazilian Portugese translation. * po/de.po: Updated German translation. gas * po/fr.po: Updated French translation. binutils* po/fr.po: Updated French translation.
2018-01-15RISC-V: Add support for addi that compresses to c.nop.Jim Wilson2-0/+13
gas/ * testsuite/gas/riscv/c-zero-imm.s: Test addi that compresses to c.nop. * testsuite/gas/riscv/c-zero-imm.d: Likewise. opcodes/ * riscv-opc.c (match_c_nop): New. (riscv_opcodes) <addi>: Handle an addi that compresses to c.nop.
2018-01-15Update Ukranian translations for bfd, binutils, gas, gold, ld and opcodesNick Clifton2-407/+444
2018-01-13Update pot filesNick Clifton2-371/+407
2018-01-13Bump version number to 2.30.51Nick Clifton2-10/+14
bfd/ * version.m4: Bump version to 2.30.51 * configure: Regenerate. binutils/ * configure: Regenerate. gas/ * configure: Regenerate. gprof/ * configure: Regenerate. ld/ * configure: Regenerate. opcodes/ * configure: Regenerate.
2018-01-13Add note about 2.30 branch creation to changelogsNick Clifton1-0/+4
2018-01-11Remove VL variants for 4FMAPS and 4VNNIW insns.Igor Tsimbalist3-172/+5
AVX512_4FMAPS and AVX512_4VNNIW insns are marked as having AVX512VL variants. That is wrong as SDM doesn't define such instructions. The patch removes these VL variants. gas/ * testsuite/gas/i386/avx512_4fmaps-warn.l: Change xmm to zmm. * testsuite/gas/i386/avx512_4fmaps-warn.s: Likewise. * testsuite/gas/i386/avx512_4fmaps_vl-intel.d: Delete. * testsuite/gas/i386/avx512_4fmaps_vl-warn.l: Likewise. * testsuite/gas/i386/avx512_4fmaps_vl-warn.s: Likewise. * testsuite/gas/i386/avx512_4fmaps_vl.d: Likewise. * testsuite/gas/i386/avx512_4fmaps_vl.s: Likewise. * testsuite/gas/i386/avx512_4vnniw_vl-intel.d: Likewise. * testsuite/gas/i386/avx512_4vnniw_vl.d: Likewise. * testsuite/gas/i386/avx512_4vnniw_vl.s: Likewise. * testsuite/gas/i386/i386.exp: Delete _vl tests for 4fmaps an 4vnniw tests. * testsuite/gas/i386/x86-64-avx512_4fmaps_vl-intel.d: Delete. * testsuite/gas/i386/x86-64-avx512_4fmaps_vl-warn.l: Likewise. * testsuite/gas/i386/x86-64-avx512_4fmaps_vl-warn.s: Likewise. * testsuite/gas/i386/x86-64-avx512_4fmaps_vl.d: Likewise. * testsuite/gas/i386/x86-64-avx512_4fmaps_vl.s: Likewise. * testsuite/gas/i386/x86-64-avx512_4vnniw_vl-intel.d: Likewise. * testsuite/gas/i386/x86-64-avx512_4vnniw_vl.d: Likewise. * testsuite/gas/i386/x86-64-avx512_4vnniw_vl.s: Likewise. opcodes/ * i386-opc.tbl: Remove VL variants for 4FMAPS and 4VNNIW insns. * i386-tbl.h: Regenerate.
2018-01-10x86: fix Disp8 handling for scalar AVX512_4FMAPS insnsJan Beulich3-4/+9
Just like their packed counterparts the memory operand is always 16 bytes wide, and the Disp8 scaling is the same for all of them. (As a side note: I'm also surprised by there being AVX512VL variants of these as well as the AVX512_4VNNIW ones - the SDM doesn't define any such.) Adjust the test cases also for the packed forms to actually live up to their promise of testing correct Disp8 encoding.
2018-01-10x86: fix Disp8 handling for AVX512VL VPCMP*{B,W} variantsJan Beulich3-96/+106
In commit 2645e1d079 ("x86: add support for AVX-512 VPCMP*{B,W} pseudo-ops") I screwed up the Disp8MemShift values of the AVX512VL variants.
2018-01-09RISC-V: Disassemble x0 based addresses as 0.Jim Wilson2-1/+6
gas/ * testsuite/gas/riscv/auipc-x0.d: New. * testsuite/gas/riscv/auipc-x0.s: New. opcodes/ * riscv-dis.c (maybe_print_address): If base_reg is zero, then the hi_addr value is zero.
2018-01-09[Arm] Add CSDB instructionJames Greenhalgh2-0/+11
CSDB is a new instruction which Arm has defined. As it shares the encoding space with NOP instructions, it is available from Armv3 in Arm mode, and Armv6T2 in Thumb mode. OK? If so, please commit on my behalf as I don't have commit rights over here. Thanks, James --- opcodes/ 2018-01-09 James Greenhalgh <james.greenhalgh@arm.com> * arm-dis.c (arm_opcodes): Add csdb. (thumb32_opcodes): Add csdb. gas/ 2018-01-09 James Greenhalgh <james.greenhalgh@arm.com> * config/tc-arm.c (insns): Add csdb, enable for Armv3 and above in Arm execution state, and Armv6T2 and above in Thumb execution state. * testsuite/gas/arm/csdb.s: New. * testsuite/gas/arm/csdb.d: New. * testsuite/gas/arm/thumb2_it_bad.l: Add csdb. * testsuite/gas/arm/thumb2_it_bad.s: Add csdb.
2018-01-09Add support for the AArch64's CSDB instruction.James Greenhalgh5-1012/+1022
CSDB is a new instruction which Arm has defined. It has the same encoding as HINT #0x14 and is available at all architecture levels. opcodes * aarch64-tbl.h (aarch64_opcode_table): Add "csdb". * aarch64-asm-2.c: Regenerate. * aarch64-dis-2.c: Regenerate. * aarch64-opc-2.c: Regenerate. gas * testsuite/gas/aarch64/system.d: Update expected results to expect CSDB.
2018-01-08x86: Properly encode vmovd with 64-bit memeoryH.J. Lu3-42/+13
For historical reason, we allow movd/vmovd with 64-bit register and memeory operands. But for vmovd, we failed to handle 64-bit memeory operand. This has been gone unnoticed since AT&T syntax always treats memory operand as 32-bit memory. This patch properly encodes vmovd with 64-bit memeory operands. It also removes AVX512 vmovd with 64-bit operands since GCC has case TYPE_SSEMOV: switch (get_attr_mode (insn)) { case MODE_DI: /* Handle broken assemblers that require movd instead of movq. */ if (!HAVE_AS_IX86_INTERUNIT_MOVQ && (GENERAL_REG_P (operands[0]) || GENERAL_REG_P (operands[1]))) return "%vmovd\t{%1, %0|%0, %1}"; return "%vmovq\t{%1, %0|%0, %1}"; and all AVX512 GNU assemblers set HAVE_AS_IX86_INTERUNIT_MOVQ, GCC won't generate AVX512 vmovd with 64-bit operand. gas/ PR gas/22681 * testsuite/gas/i386/i386.exp: Run x86-64-movd and x86-64-movd-intel. * testsuite/gas/i386/x86-64-movd-intel.d: New file. * testsuite/gas/i386/x86-64-movd.d: Likewise. * testsuite/gas/i386/x86-64-movd.s: Likewise. opcodes/ PR gas/22681 * i386-opc.tbl: Properly encode vmovd with Qword memeory operand. Remove AVX512 vmovd with 64-bit operands. * i386-tbl.h: Regenerated.
2018-01-05RISC-V: Print symbol address for jalr w/ zero offset.Jim Wilson2-0/+7
ld/ * testsuite/ld-riscv-elf/disas-jalr.d: New. * testsuite/ld-riscv-elf/disas-jalr.s: New. * testsuite/ld-riscv-elf/ld-riscv-elf.exp: Run new testcase. opcodes/ * riscv-dis.c (print_insn_args) <'s'>: Call maybe_print_address for a jalr.
2018-01-03Update year range in copyright notice of binutils filesAlan Modra277-280/+284
2018-01-03ChangeLog rotationAlan Modra2-1965/+1979
2018-01-02x86: partial revert of 10c17abdd0Jan Beulich2-0/+9
Other than the variables in tc-i386.c using them, OPERAND_TYPE_REGYMM and OPERAND_TYPE_REGZMM they aren't entirely unused. No need to update i386-init.h though, as it mistakenly wasn't updated by the original commit.
2017-12-20RISC-V: Add compressed instruction hints, and a few misc cleanups.Jim Wilson2-13/+46
gas/ * config/tc-riscv.c (risc_ip) <o>: Add comment. * testsuite/gas/riscv/c-nonzero-imm.d, * testsuite/gas/riscv/c-nonzero-imm.l, * testsuite/gas/riscv/c-nonzero-imm.s, * testsuite/gas/riscv/c-nonzero-reg.d, * testsuite/gas/riscv/c-nonzero-reg.l, * testsuite/gas/riscv/c-nonzero-reg.s, * testsuite/gas/riscv/c-zero-imm-64.d, * testsuite/gas/riscv/c-zero-imm-64.s, * testsuite/gas/riscv/c-zero-imm.d, testsuite/gas/riscv/c-zero-imm.s, * testsuite/gas/riscv/c-zero-reg.d, * testsuite/gas/riscv/c-zero-reg.s: New. opcodes/ * riscv-opc.c (match_c_add_with_hint, match_c_lui_with_hint): New. (riscv_opcodes) <li>: Delete "d,0" line. Change Cj to Co. <andi, and, add, addiw, addw, c.addi>: Change Cj to Co. <add>: Add explanatory comment for 4-operand add instruction. <c.nop>: Add support for immediate operand. <c.mv, c.add>: Use match_c_add_with_hint instead of match_c_add. <c.lui>: Use match_c_lui_with_hint instead of match_c_lui. <c.li, c.slli>: Use match_opcode instead of match_rd_nonzero.
2017-12-19Correct disassembly of dot product instructions.Tamar Christina5-4/+15
Dot products deviate from the normal disassembly rules for lane indexed instruction. Their canonical representation is in the form of: v0.2s, v0.8b, v0.4b[0] instead of v0.2s, v0.8b, v0.b[0] to try to denote that these instructions select 4x 1 byte elements instead of a single 1 byte element. Previously we were disassembling them following the normal rules, this patch corrects the disassembly. gas/ PR gas/22559 * config/tc-aarch64.c (vectype_to_qualifier): Support AARCH64_OPND_QLF_S_4B. * gas/testsuite/gas/aarch64/dotproduct.d: Update disassembly. include/ PR gas/22559 * aarch64.h (aarch64_opnd_qualifier): Add AARCH64_OPND_QLF_S_4B. opcodes/ PR gas/22559 * aarch64-asm.c (aarch64_ins_reglane): Change AARCH64_OPND_QLF_S_B to AARCH64_OPND_QLF_S_4B * aarch64-dis.c (aarch64_ext_reglane): Change AARCH64_OPND_QLF_S_B to AARCH64_OPND_QLF_S_4B * aarch64-opc.c (aarch64_opnd_qualifiers): Add 4b variant. * aarch64-tbl.h (QL_V2DOT): Change S_B to S_4B.
2017-12-19Add support for V_4B so we can properly reject it.Tamar Christina2-0/+6
Previously parse_vector_type_for_operand was changed to allow the use of 4b register size for indexed lane instructions. However this had the unintended side effect of also allowing 4b for normal vector registers. Because this support was only partial the rest of the tool silently treated 4b as 8b and continued. This patch adds full support for 4b so it can be properly distinguished from 8b and the correct errors are generated. With this patch you still can't encode any instruction which actually requires v<num>.4b but such instructions don't exist so to prevent needing a workaround in get_vreg_qualifier_from_value this was just omitted. gas/ PR gas/22529 * config/tc-aarch64.c (vectype_to_qualifier): Support AARCH64_OPND_QLF_V_4B. * gas/testsuite/gas/aarch64/pr22529.s: New. * gas/testsuite/gas/aarch64/pr22529.d: New. * gas/testsuite/gas/aarch64/pr22529.l: New. include/ PR gas/22529 * opcode/aarch64.h (aarch64_opnd_qualifier): Add AARCH64_OPND_QLF_V_4B. opcodes/ PR gas/22529 * aarch64-opc.c (aarch64_opnd_qualifiers): Add 4b variant.
2017-12-18x86: fold certain AVX and AVX2 templatesJan Beulich5-4106/+789
Just like for instructions in GPRs, there's no need to have separate templates for otherwise identical insns acting on XMM or YMM registers (or memory of the same size).
2017-12-18x86: fold RegXMM/RegYMM/RegZMM into RegSIMDJan Beulich7-46306/+46315
... qualified by their respective sizes, allowing to drop FirstXmm0 at the same time.
2017-12-18x86: drop FloatReg and FloatAccJan Beulich6-32581/+32585
Express them as Reg|Tbyte and Acc|Tbyte respectively.
2017-12-18x86: replace Reg8, Reg16, Reg32, and Reg64Jan Beulich7-32766/+33250
Use a combination of a single new Reg bit and Byte, Word, Dword, or Qword instead. Besides shrinking the number of operand type bits this has the benefit of making register handling more similar to accumulator handling (a generic flag is being accompanied by a "size qualifier"). It requires, however, to split a few insn templates, as it is no longer correct to have combinations like Reg32|Reg64|Byte. This slight growth in size will hopefully be outweighed by this change paving the road for folding a presumably much larger number of templates later on.
2017-12-15Fix disassembly for PowerPCDimitar Dimitrov2-3/+8
* disassemble.c (disassemble_init_for_target): Don't put PRU between powerpc and rs6000 cases.
2017-12-15x86: drop stray CheckRegSize usesJan Beulich3-155/+164
They are relevant only when multiple operands permit registers: operand_type_register_match() returns true if either operand is not a register one. IOW grep -i CheckRegSize i386-opc.tbl | grep -Ev "(Reg[8136]|Acc).*,.*(Reg|Acc)" should produce no output.
2017-12-13Add missing RISC-V fsrmi and fsflagsi instructions.Jim Wilson2-0/+9
PR 22599 gas/ * testsuite/gas/riscv/fsxxi.d, testsuite/gas/riscv/fsxxi.s: New. opcodes/ * riscv-opc.c (riscv_opcodes) <fsrmi, fsflagsi>: New.
2017-12-13This patch enables disassembler_needs_relocs for PRU. It is needed to print ↵Dimitar Dimitrov2-0/+9
correct symbols when disassembling arguments of "call" instructions with a relocation. opcodes * disassemble.c: Enable disassembler_needs_relocs for PRU. gas * testsuite/gas/pru/extern.s: New test for print of U16_PMEMM relocation. * testsuite/gas/pru/extern.d: New test driver.
2017-12-11[Binutils][Objdump]Check symbol section information while search a mapping ↵Renlin Li2-3/+11
symbol backward. When checking mapping symbols backwardly, the section which defines the symbol is not considerted. This patch fixes this by moving the section checking code into get_sym_code_type () function which is shared by forward and backword mapping symbol searching. opcodes/ 2017-12-11 Petr Pavlu <petr.pavlu@arm.com> Renlin Li <renlin.li@arm.com> * aarch64-dis.c (print_insn_aarch64): Move symbol section check ... (get_sym_code_type): Here. binutils/ 2017-12-11 Renlin Li <renlin.li@arm.com> * testsuite/binutils-all/aarch64/objdump.d: New. * testsuite/binutils-all/aarch64/objdump.s: New.
2017-12-03Fix "FAIL: VLE relocations 3"Alan Modra2-7/+7
Correct sign extension. * ppc-opc.c (extract_li20): Rewrite.
2017-12-01Use consistent types for holding instructions, instruction masks, etc.Peter Bergner3-517/+556
include/ * opcode/ppc.h (PPC_INT_FMT): Define. (struct powerpc_opcode) <opcode>: Update type. (struct powerpc_opcode) <mask>: Likewise. (struct powerpc_opcode) <bitm>: Likewise. (struct powerpc_opcode) <insert>: Likewise. (struct powerpc_opcode) <extract>: Likewise. (ppc_optional_operand_value): Likewise. gas/ * config/tc-ppc.c (last_insn): Update type. (insn_validate) <omask, mask>: Likewise. (ppc_setup_opcodes) <mask, right_bit>: Likewise. <PRINT_OPCODE_TABLE>: Update types and printf format specifiers. (ppc_insert_operand): Update return and argument types and remove unneeded type casts. <min, max, right, tmp>: Update type. (md_assemble): Remove unneeded type casts. <insn, val, tmp_insn>: Update type. opcodes/ * opcodes/ppc-dis.c (disassemble_init_powerpc): Fix white space. (operand_value_powerpc): Update return and argument type. <value, top>: Update type. (skip_optional_operands): Update argument type. (lookup_powerpc): Likewise. (lookup_vle): Likewise. <table_opcd, table_mask, insn2>: Update type. (lookup_spe2): Update argument type. <table_opcd, table_mask, insn2>: Update type. (print_insn_powerpc) <insn, value>: Update type. Use PPC_INT_FMT for printing instructions and operands. * opcodes/ppc-opc.c (insert_arx, extract_arx, insert_ary, extract_ary, insert_rx, extract_rx, insert_ry, extract_ry, insert_bat, extract_bat, insert_bba, extract_bba, insert_bdm, extract_bdm, insert_bdp, extract_bdp, valid_bo_pre_v2, valid_bo_post_v2, valid_bo, insert_bo, extract_bo, insert_boe, extract_boe, insert_dcmxs, extract_dcmxs, insert_dxd, extract_dxd, insert_dxdn, extract_dxdn, insert_fxm, extract_fxm, insert_li20, extract_li20, insert_ls, extract_ls, insert_esync, extract_esync, insert_mbe, extract_mbe, insert_mb6, extract_mb6, extract_nb, insert_nbi, insert_nsi, extract_nsi, insert_ral, extract_ral, insert_ram, extract_ram, insert_raq, extract_raq, insert_ras, extract_ras, insert_rbs, extract_rbs, insert_rbx, extract_rbx, insert_sci8, extract_sci8, insert_sci8n, extract_sci8n, insert_sd4h, extract_sd4h, insert_sd4w, extract_sd4w, insert_oimm, extract_oimm, insert_sh6, extract_sh6, insert_spr, extract_spr, insert_sprg, extract_sprg, insert_tbr, extract_tbr, insert_xt6, extract_xt6, insert_xtq6, extract_xtq6, insert_xa6, extract_xa6, insert_xb6, extract_xb6, insert_xb6s, extract_xb6s, insert_xc6, extract_xc6, insert_dm, extract_dm, insert_vlesi, extract_vlesi, insert_vlensi, extract_vlensi, insert_vleui, extract_vleui, insert_vleil, extract_vleil, insert_evuimm1_ex0, extract_evuimm1_ex0, insert_evuimm2_ex0, extract_evuimm2_ex0, insert_evuimm4_ex0, extract_evuimm4_ex0, insert_evuimm8_ex0, extract_evuimm8_ex0, insert_evuimm_lt8, extract_evuimm_lt8, insert_evuimm_lt16, extract_evuimm_lt16, insert_rD_rS_even, extract_rD_rS_even, insert_off_lsp, extract_off_lsp, insert_off_spe2, extract_off_spe2, insert_Ddd, extract_Ddd): Update types. (OP, OPTO, OPL, OPVUP, OPVUPRT, A, AFRALFRC_MASK, B, BD8, BD8IO, BD15, BD24, BBO, Y_MASK , AT1_MASK, AT2_MASK, BBOCB, C_LK, C, CTX, UCTX, DX, EVSEL, IA16, I16A, I16L, IM7, LI20, MME, MD, MDS, SC, SC_MASK, SCI8, SCI8BF, SD4, SE_IM5, SE_R, SE_RR, VX, VX_LSP, VX_RA_CONST, VX_RB_CONST, VX_SPE_CRFD, VX_SPE2_CLR, VX_SPE2_SPLATB, VX_SPE2_OCTET, VX_SPE2_DDHH, VX_SPE2_HH, VX_SPE2_EVMAR, VX_SPE2_EVMAR_MASK, VXA, VXR, VXASH, X, EX, XX2, XX3, XX3RC, XX4, Z, XWRA_MASK, XLRT_MASK, XRLARB_MASK, XLRAND_MASK, XRTLRA_MASK, XRTLRARB_MASK, XRTARARB_MASK, XRTBFRARB_MASK, XOPL, XOPL2, XRCL, XRT, XRTRA, XCMP_MASK, XCMPL_MASK, XTO, XTLB, XSYNC, XEH_MASK, XDSS, XFL, XISEL, XL, XLO, XLYLK, XLOCB, XMBAR, XO, XOPS, XS, XFXM, XSPR, XUC, XW, APU): Update types in casts.
2017-11-30x86: derive DispN from BaseIndexJan Beulich4-4142/+4196
BaseIndex implies - with the exception of string instructions the optional presence of a displacement. This is almost completely uniform for all instructions (the sole exception being MPX ones, which don't allow 16-bit addressing and hence Disp16), so there's no point in explicitly stating this in the main opcode table. Drop those explict specifications in favor of adding logic to i386-gen, shrinking the table size quite a bit and hence making it more readable. The opcodes/i386-tbl.h changes are due to a few cases where pointless Disp* still hadn't been removed from their insns.
2017-11-30x86: drop Vec_Disp8Jan Beulich6-16227/+16225
This is fully redundant with Disp8MemShift being non-zero, and hence can be folded with normal Disp8 handling.
2017-11-29Support --localedir, --datarootdir and --datadirStefan Stroe2-4/+10
bfd/ * po/Make-in (datadir): Define as @datadir@. (localedir): Define as @localedir@. (gnulocaledir, gettextsrcdir): Use @datarootdir@. binutils/ * po/Make-in (datadir): Define as @datadir@. (localedir): Define as @localedir@. (gnulocaledir, gettextsrcdir): Use @datarootdir@. gas/ * po/Make-in (datadir): Define as @datadir@. (localedir): Define as @localedir@. (gnulocaledir, gettextsrcdir): Use @datarootdir@. gold/ * po/Make-in (datadir): Define as @datadir@. (localedir): Define as @localedir@. (gnulocaledir, gettextsrcdir): Use @datarootdir@. gprof/ * po/Make-in (datadir): Define as @datadir@. (localedir): Define as @localedir@. (gnulocaledir, gettextsrcdir): Use @datarootdir@. ld/ * po/Make-in (datadir): Define as @datadir@. (localedir): Define as @localedir@. (gnulocaledir, gettextsrcdir): Use @datarootdir@. opcodes/ * po/Make-in (datadir): Define as @datadir@. (localedir): Define as @localedir@. (gnulocaledir, gettextsrcdir): Use @datarootdir@.
2017-11-27Update the simplified Chinese translation of the messages in the opcodes ↵Nick Clifton2-437/+945
library. * po/zh_CN.po: Updated simplified Chinese translation.
2017-11-24x86: don't omit disambiguating suffixes from "fi*"Jan Beulich2-12/+17
"fi*" typically come in two (loads/stores: three) flavors, distinguished by the suffix. Don't omit the 's' one when disassembling.
2017-11-23Add Disp8MemShift for AVX512 VAES instructions.Igor Tsimbalist3-24/+29
opcodes/ * i386-opc.tbl: Add Disp8MemShift for AVX512 VAES instructions. * i386-tbl.h: Regenerate. gas/ * testsuite/gas/i386/avx512f_vaes-intel.d: Regenerate. * testsuite/gas/i386/avx512f_vaes.d: Likewise. * testsuite/gas/i386/avx512f_vaes-wig1-intel.d: Likewise. * testsuite/gas/i386/avx512f_vaes-wig1.d: Likewise. * testsuite/gas/i386/avx512vl_vaes-intel.d: Likewise. * testsuite/gas/i386/avx512vl_vaes.d: Likewise. * testsuite/gas/i386/x86-64-avx512f_vaes.s: Add instructions with disp8*N. * testsuite/gas/i386/x86-64-avx512f_vaes-intel.d: Regenerate. * testsuite/gas/i386/x86-64-avx512f_vaes.d: Likewise. * testsuite/gas/i386/x86-64-avx512f_vaes-wig.s: Add instructions with disp8*N. * testsuite/gas/i386/x86-64-avx512f_vaes-wig1-intel.d: Regenerate. * testsuite/gas/i386/x86-64-avx512f_vaes-wig1.d: Likewise. * testsuite/gas/i386/x86-64-avx512vl_vaes-intel.d: Regenerate. * testsuite/gas/i386/x86-64-avx512vl_vaes.d: Likewise. * testsuite/gas/i386/x86-64-avx512vl_vaes-wig.s: Add instructions with disp8*N. * testsuite/gas/i386/x86-64-avx512vl_vaes-wig1-intel.d: Regenerate. * testsuite/gas/i386/x86-64-avx512vl_vaes-wig1.d: Regenerate.
2017-11-23x86: fix AVX-512 16-bit addressingJan Beulich2-0/+7
Despite EVEX encodings not being available in real and VM86 modes, 16-bit addressing still needs to be handled properly for 16-bit protected mode as well as 16-bit addressing in 32-bit mode. Neither should displacements be dropped silently by the assembler, nor should the disassembler fail to correctly scale 8-bit displacements.
2017-11-23x86: correct UDnJan Beulich4-14/+47
Make the assembler recognize UD0, supporting only the newer form expecting a ModR/M byte. Make assembler and disassembler properly emit / expect a ModR/M byte for UD1. For the testsuite, as arch-4 already tests all UDn, avoid producing a huge delta for other tests using UD2B by making them use UD2 instead.
2017-11-22Remove Vec_Disp8 field for vgf2p8mulb for AVX flavor.Igor Tsimbalist3-4/+9
* i386-opc.tbl: Remove Vec_Disp8 from vgf2p8mulb. * i386-tbl.h: Regenerate.
2017-11-22Update ChangeLogIgor Tsimbalist1-0/+5
2017-11-22Remove Vec_Disp8 from vpcompressb and vpexpandb.Igor Tsimbalist2-13/+12
* i386-opc.tbl: Remove Vec_Disp8 from vpcompressb and vpexpandb. * i386-tbl.h: Regenerate.
2017-11-22[ARC] Fix handling of ARCv2 H-register class.claziss2-0/+6
For ARCv2, h-regs are only valid unitl r31. gas/ 2017-11-21 Claudiu Zissulescu <claziss@synopsys.com> * testsuite/gas/arc/hregs-err.s: New test. opcodes/ 2017-11-21 Claudiu Zissulescu <claziss@synopsys.com> * arc-opc.c (insert_rhv2): Check h-regs range.
2017-11-21[ARC] Improve printing of pc-relative instructions.claziss3-17/+52
opcodes/ 2017-11-21 Claudiu Zissulescu <claziss@synopsys.com> * arc-dis.c (print_insn_arc): Pretty print pc-relative offsets. * arc-opc.c (SIMM21_A16_5): Make it pc-relative. gas/ 2017-11-21 Claudiu Zissulescu <claziss@synopsys.com> * testsuite/gas/arc/b.d : Update test. * testsuite/gas/arc/bl.d: Likewise. * testsuite/gas/arc/jli-1.d: Likewise. * testsuite/gas/arc/lp.d: Likewise. * testsuite/gas/arc/pcl-relocs.d: Likewise. * testsuite/gas/arc/pcrel-relocs.d: Likewise. * testsuite/gas/arc/pic-relocs.d: Likewise. * testsuite/gas/arc/plt-relocs.d: Likewise. * testsuite/gas/arc/pseudos.d: Likewise. * testsuite/gas/arc/relax-avoid2.d: Likewise. * testsuite/gas/arc/relax-avoid3.d: Likewise. * testsuite/gas/arc/relax-b.d: Likewise. * testsuite/gas/arc/tls-relocs.d: Likewise. * testsuite/gas/arc/relax-add01.d: Likewise. * testsuite/gas/arc/relax-add04.d: Likewise. * testsuite/gas/arc/relax-ld01.d: Likewise. * testsuite/gas/arc/relax-sub01.d: Likewise. * testsuite/gas/arc/relax-sub02.d: Likewise. * testsuite/gas/arc/relax-sub04.d: Likewise. * testsuite/gas/arc/pcl-print.s: New file. * testsuite/gas/arc/pcl-print.d: Likewise. * testsuite/gas/arc/nps400-12.d: Likewise. ld/ 2017-11-21 Claudiu Zissulescu <claziss@synopsys.com> * testsuite/ld-arc/jli-simple.d: Update test.
2017-11-16Add new AArch64 FP16 FM{A|S} instructions.Tamar Christina2-2/+7
This patch separates the new FP16 instructions backported from Armv8.4-a to Armv8.2-a into a new flag order to distinguish them from the rest of the already existing optional FP16 instructions in Armv8.2-a. The new flag "+fp16fml" is available from Armv8.2-a and implies +fp16 and is mandatory on Armv8.4-a. gas/ * config/tc-aarch64.c (fp16fml): New. * doc/c-aarch64.texi (fp16fml): New. * testsuite/gas/aarch64/armv8_2-a-crypto-fp16.d (fp16): Make fp16fml. * testsuite/gas/aarch64/armv8_3-a-crypto-fp16.d (fp16): Make fp16fml. include/ * opcode/aarch64.h: (AARCH64_FEATURE_F16_FML): New. (AARCH64_ARCH_V8_4): Enable AARCH64_FEATURE_F16_FML by default. opcodes/ * aarch64-tbl.h (aarch64_feature_fp_16_v8_2): Require AARCH64_FEATURE_F16_FML and AARCH64_FEATURE_F16.
2017-11-16Correct AArch64 crypto dependencies.Tamar Christina1-4/+6
The crypto options depend on SIMD and FP, the documentation states so but the dependency is not there the code. We have mostly gotten away with this due to the default flags for the architectures (e.g. Armv8.2-a implies +simd) but this discrepancy needs to be addressed. gas/ 2017-11-16 Tamar Christina <tamar.christina@arm.com> * opcodes/aarch64-tbl.h (aarch64_feature_crypto): Add ARCH64_FEATURE_SIMD and AARCH64_FEATURE_FP. (aarch64_feature_crypto_v8_2, aarch64_feature_sm4): Likewise. (aarch64_feature_sha3): Likewise.
generated by cgit v1.1 at 2024-11-26 21:14:28 +0000