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2021-11-25Updated French translation for the opcodes directory.Nick Clifton2-236/+264
2021-11-23Update bug reporting addressAlan Modra1-1/+1
2021-11-18Re: Don't compile some opcodes files when bfd is 32-bit onlyAlan Modra2-10/+10
2021-11-18RISC-V: Add instructions and operand set for z[fdq]inxjiawei2-148/+152
2021-11-17aarch64: [SME] SVE2 instructions added to support SMEPrzemyslaw Wirkus10-191/+387
2021-11-17aarch64: [SME] Add new SME system registersPrzemyslaw Wirkus1-1/+11
2021-11-17aarch64: [SME] Add SME mode selection and state access instructionsPrzemyslaw Wirkus10-1514/+1641
2021-11-17aarch64: [SME] Add LD1x, ST1x, LDR and STR instructionsPrzemyslaw Wirkus9-236/+605
2021-11-17aarch64: [SME] Add ZERO instructionPrzemyslaw Wirkus6-140/+204
2021-11-17aarch64: [SME] Add MOV and MOVA instructionsPrzemyslaw Wirkus10-175/+363
2021-11-17aarch64: [SME] Add SME instructionsPrzemyslaw Wirkus6-133/+547
2021-11-17aarch64: [SME] Add +sme option to -marchPrzemyslaw Wirkus1-0/+11
2021-11-17RISC-V: Support rvv extension with released version 1.0.Nelson Chu2-0/+893
2021-11-16RISC-V: Scalar crypto instructions and operand set.jiawei2-20/+80
2021-11-12Don't compile some opcodes files when bfd is 32-bit onlyAlan Modra5-56/+74
2021-11-11RISC-V: Dump objects according to the elf architecture attribute.Nelson Chu1-6/+26
2021-11-05Missing va_end in aarch64-dis.cAlan Modra1-0/+1
2021-11-02opcodes: d10v: simplify header includesMike Frysinger1-2/+1
2021-11-01arm: add armv9-a architecture to -marchPrzemyslaw Wirkus1-3/+2
2021-10-28ubsan: arm: undefined shiftAlan Modra1-1/+1
2021-10-27RISC-V: Tidy riscv assembler and disassembler.Nelson Chu1-8/+10
2021-10-27opcodes: Fix RPATH not being set for dynamic libbfd dependencyMaciej W. Rozycki5-36/+10
2021-10-24LoongArch opcodes supportliuzhensong10-0/+1637
2021-10-11z80/disassembler: call memory_error_func when appropriateAndrew Burgess1-0/+2
2021-10-11s12z/disassembler: call memory_error_func when appropriateAndrew Burgess1-0/+3
2021-10-07RISC-V: Support aliases for Zbs instructionsPhilipp Tomsich1-0/+4
2021-10-07RISC-V: Add support for Zbs instructionsPhilipp Tomsich1-0/+9
2021-10-07RISC-V: Split Zb[abc] into commented sectionsPhilipp Tomsich1-0/+6
2021-09-28x86: Print {bad} on invalid broadcast in OP_E_memoryCui,Lili1-74/+81
2021-09-27configure: regenerate in all projects that use libtool.m4Nick Alcock2-45/+50
2021-09-25PowerPC: Enable mfppr mfppr32, mtppr and mtppr32 extended mnemonics on POWER5Peter Bergner2-4/+9
2021-09-20riscv: print .2byte or .4byte before an unknown instruction encodingAndrew Burgess2-1/+29
2021-09-13[gdb/tdep] Reset force_thumb in parse_arm_disassembler_optionsTom de Vries1-0/+1
2021-09-08RISC-V: Pretty print values formed with lui and addiw.Jim Wilson1-5/+18
2021-09-06Add a sanity check to the init_nfp6000_mecsr_sec() function in the NFP disass...Yinjun Zhang1-2/+5
2021-09-03pj: asan: out of bounds, ubsan: left shift of negativeAlan Modra1-3/+4
2021-09-02Add support for the haiku operating system. These are the os support patches...Alexander von Gluck IV1-1/+1
2021-09-02Fix the V850 assembler's generation of relocations for the st.b instruction.Nick Clifton2-1/+7
2021-09-01nfp: add validity check of island and meYinjun Zhang1-1/+10
2021-08-30RISC-V: PR28291, Fix the gdb fails that PR27916 caused.Nelson Chu1-2/+2
2021-08-30RISC-V: PR27916, Support mapping symbols.Nelson Chu1-12/+233
2021-08-24FT32: Remove recursion in ft32_opcodeJames Bowman (FTDI-UK)1-114/+115
2021-08-19x86: Put back 3 aborts in OP_E_memoryH.J. Lu1-3/+3
2021-08-19x86: Avoid abort on invalid broadcastH.J. Lu1-4/+4
2021-08-17opcodes: Fix the auxiliary register numbers for ARC HSShahab Vahedi2-2/+6
2021-08-13PR28168: [CSKY] Fix stack overflow in disassemblerLifang Xia1-4/+4
2021-08-11Deprecate a.out support for NetBSD targets.John Ericson1-53/+53
2021-08-10Updated Serbian and Russian translations for various sub-directoriesNick Clifton2-236/+293
2021-08-05[PATCH 1/2] Enable Intel AVX512_FP16 instructionsCui,Lili9-16206/+25260
2021-08-04IBM Z: Remove lpswey parameterAndreas Krebbel2-1/+3
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