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2017-04-25[ARC] Enhance enter/leave mnemonics.Claudiu Zissulescu4-4/+44
2017-04-25[ARC] Prefer NOP instead of MOV 0,0Claudiu Zissulescu2-3/+7
2017-04-25MIPS16/opcodes: Add `-M no-aliases' disassembler option help textMaciej W. Rozycki2-0/+8
2017-04-25MIPS16/opcodes: Annotate instruction aliasesMaciej W. Rozycki2-5/+13
2017-04-24Fix snafu in aarch64 opcodes debugging statement.Tamar Christina2-2/+7
2017-04-22PowerPC VLE insn set additionsAlan Modra2-7/+19
2017-04-21opcodes: mark SPARC RETT instructions as v6notv9.Jose E. Marchesi2-7/+11
2017-04-21Fix detection of illegal AArch64 opcodes that resemble LD1R, LD2R, LD3R and L...Nick Clifton2-8/+14
2017-04-13Regen cgen filesAlan Modra14-24/+53
2017-04-11Reorder PPC_OPCODE_* and set PPC_OPCODE_TMR for e6500Alan Modra3-6/+7
2017-04-11Bye bye PPC_OPCODE_HTM and -mhtmAlan Modra3-9/+8
2017-04-11Bye Bye PPC_OPCODE_VSX3Alan Modra3-7/+8
2017-04-11Bye bye PPC_OPCODE_ALTIVEC2Alan Modra3-7/+13
2017-04-10Tidy ppc476 opcodesAlan Modra3-43/+50
2017-04-10WebAssembly disassembler supportPip Cet2-3/+7
2017-04-07Remove E6500 insns from PPC_OPCODE_ALTIVEC2Alan Modra2-25/+33
2017-04-06Add support for disassembling WebAssembly opcodes.Pip Cet9-3/+569
2017-04-05-Wwrite-strings: Constify struct disassemble_info's disassembler_options fieldPedro Alves5-6/+13
2017-04-04RISC-V: Resurrect GP-relative disassembly hintsPalmer Dabbelt2-1/+6
2017-03-30Add support for the WebAssembly file format and the wasm32 ELF conversion to ...Pip Cet4-158/+189
2017-03-29opcodes: sparc: support missing SPARC ASIs from UA2005, UA2007, OSA2011, & OS...Jose E. Marchesi2-0/+34
2017-03-29PowerPC -Mraw disassemblyAlan Modra2-10/+26
2017-03-27PR21303, objdump doesn't show e200z4 insnsAlan Modra2-2/+19
2017-03-27Implement ARC NPS-400 Ultra Ip and Miscellaneous instructions.Rinat Zelig3-350/+612
2017-03-21S/390: Remove vx2 facility flagAndreas Krebbel3-146/+147
2017-03-21arc/nps400: Add cp16/cp32 instructions to opcodes libraryRinat Zelig3-3/+279
2017-03-17E6500 spr mnemonicsAlan Modra2-8/+15
2017-03-15RISC-V: Fix assembler for c.li, c.andi and c.addiwKito Cheng2-3/+9
2017-03-15RISC-V: Fix assembler for c.addi, rd can be x0Kito Cheng2-1/+5
2017-03-14RISC-V: Fix [dis]assembly of srai/srliAndrew Waterman2-4/+11
2017-03-09X86: Add pseudo prefixes to control encodingH.J. Lu5-73/+183
2017-03-09Use CpuCET on rdsspqH.J. Lu3-2/+7
2017-03-08Update -maltivec and -mvsx options to only enable their oldest instructions.Peter Bergner2-2/+7
2017-03-08Add support for the new 'lnia' extended mnemonic.Peter Bergner2-0/+7
2017-03-06Add support for Intel CET instructionsH.J. Lu7-334/+681
2017-03-06Don't decode powerpc insns with invalid fieldsAlan Modra2-49/+168
2017-02-28GDB: Add support for the new set/show disassembler-options commands.Peter Bergner6-218/+394
2017-02-28x86: fix handling of 64-bit operand size VPCMPESTR{I,M}Jan Beulich4-26/+170
2017-02-24[AArch64] Additional SVE instructionsRichard Sandiford11-2089/+2815
2017-02-24[AArch64] Add a "compnum" featureRichard Sandiford2-6/+17
2017-02-24x86: also correctly support TEST opcode aliasesJan Beulich2-2/+6
2017-02-23S/390: Add support for new cpu architecture - arch12.Andreas Krebbel3-79/+311
2017-02-23opcodes,gas: associate SPARC ASIs with an architecture level.Sheldon Lobo2-195/+196
2017-02-23x86: drop stray VEX opcode 82 referencesJan Beulich2-4/+9
2017-02-22aarch64: actually copy first operand in convert_bfc_to_bfm()Jan Beulich2-2/+7
2017-02-15Add SFENCE.VMA instructionAndrew Waterman2-0/+8
2017-02-15[AArch64] Add SVE system registersRichard Sandiford2-0/+21
2017-02-15[ARC] Fix assembler relaxation.Claudiu Zissulescu2-34/+75
2017-02-15Distinguish some of the registers different on ARC700 and HS38 cpusVineet Gupta2-12/+41
2017-02-14PowerPC register expression checksAlan Modra2-5/+11
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