riscv-gnu-toolchain/gdb.git - Unnamed repository; edit this file 'description' to name the repository.

Age	Commit message (Expand)	Author	Files	Lines
2017-11-03	[ARC] Force the disassam to use the hexadecimal number for printing	claziss	2	-1/+21
2017-11-03	[ARC] Sync opcode data base.	claziss	3	-1588/+3455
2017-10-25	PR22348, conflicting global vars in crx and cr16	Alan Modra	4	-20/+33
2017-10-24	RISC-V: Fix disassembly of c.addi4spn, c.addi16sp, c.lui when imm=0	Andrew Waterman	2	-7/+33
2017-10-23	Add missing ChangeLog entries	Igor Tsimbalist	1	-0/+110
2017-10-23	Fix the master due to bad regenerated files	Igor Tsimbalist	3	-5469/+11545
2017-10-23	Enable Intel AVX512_BITALG instructions.	Igor Tsimbalist	5	-3/+51
2017-10-23	Enable Intel AVX512_VNNI instructions.	Igor Tsimbalist	5	-6/+48
2017-10-23	Enable Intel VPCLMULQDQ instruction.	Igor Tsimbalist	5	-14/+30
2017-10-23	Enable Intel VAES instructions.	Igor Tsimbalist	7	-5576/+5902
2017-10-23	Enable Intel GFNI instructions.	Igor Tsimbalist	7	-5443/+6011
2017-10-23	Enable Intel AVX512_VBMI2 instructions.	Igor Tsimbalist	7	-5389/+6652
2017-10-18	[Visium] Disassemble the operands of the stop instruction.	Eric Botcazou	2	-1/+5
2017-10-12	FT32: support for FT32B processor - part 1	James Bowman	3	-22/+49
2017-10-09	S/390: Sync with latest POP - 3 new instructions	Andreas Krebbel	2	-0/+8
2017-10-09	S/390: Sync with IBM z14 POP - SI_RD format	Andreas Krebbel	3	-4/+13
2017-10-01	Add new mnemonics for VLE multiple load instructions	Alexander Fedotov	2	-0/+15
2017-09-27	Add support for the new names of the RISC-V fmv.x.s and fmv.s.x instructions,...	Nick Clifton	2	-0/+11
2017-09-26	Allow the macw and macl instructions to be used on CPUs that have emacs support.	Nick Clifton	2	-0/+20
2017-09-25	Initialize 'imm' on opcodes/aarch64-opc.c:expand_fp_imm (and fix breakage on ...	Sergio Durigan Junior	2	-1/+5
2017-09-11	nds32: Rename __BIT() to N32_BIT().	Kuan-Lin Chen	4	-40/+46
2017-09-09	x86: Remove restriction on NOTRACK prefix position	H.J. Lu	2	-16/+8
2017-08-31	Add updated French translations for opcodes and gprof	Nick Clifton	2	-418/+786
2017-08-30	FT32: improve disassembly readability	James Bowman	2	-7/+17
2017-08-24	[PowerPC VLE] Add SPE2 and EFS2 instructions support	Alexander Fedotov	3	-12/+1239
2017-08-23	ppc-opc.c formatting	Alan Modra	2	-1089/+1101
2017-08-22	RISC-V: Mark "c.nop" as an alias	Palmer Dabbelt	2	-1/+5
2017-08-21	[PowerPC VLE] Add LSP (Lightweight Signal Processing) instruction support	Alexander Fedotov	3	-6/+920
2017-08-09	[ARM] Don't warn on REG_SP when used in CRC32 instructions	Jiong Wang	2	-11/+13
2017-08-07	Mark big and mach with ATTRIBUTE_UNUSED	H.J. Lu	2	-1/+8
2017-08-07	GDB/opcodes: Remove arch/mach/endian disassembler assertions	Maciej W. Rozycki	2	-12/+6
2017-07-25	Fix typos in error and option messages in OPCODES library.	Nick Clifton	3	-36/+75
2017-07-24	[AArch64] Fix the bit pattern order in the comments in auto-generated file	Jiong Wang	3	-1689/+1699
2017-07-21	S/390: Support z14 as CPU name.	Andreas Krebbel	2	-1/+7
2017-07-20	Update the German translation for the opcodes library.	Nick Clifton	2	-466/+890
2017-07-19	[ARC] Add SecureShield AUX registers	claziss	2	-0/+21
2017-07-19	[ARC] Add SJLI instruction.	Claudiu Zissulescu	3	-1/+27
2017-07-19	[ARC] Add JLI support.	John Eric Martin	4	-2/+17
2017-07-18	Fix spelling typos.	Yuri Chornovian	3	-2/+8
2017-07-14	binutils/objdump: Fix disassemble for huge elf sections	Ravi Bangoria	2	-3/+8
2017-07-12	Update PO files	Alan Modra	16	-875/+2049
2017-07-11	Mark generated cgen files read-only	Alan Modra	96	-8/+211
2017-07-07	Move print_insn_XXX to an opcodes internal header, again	Alan Modra	4	-3/+9
2017-07-05	X86: Disassemble primary opcode map's group 2 ModRM.reg == 6 aliases correctly	Borislav Petkov	2	-6/+10
2017-07-05	Fixup changelog entries for previous commit	Ramana Radhakrishnan	1	-0/+5
2017-07-04	[Patch ARM] Support MVFR2 VFP Coprocessor register for ARMv8-A	Ramana Radhakrishnan	1	-0/+4
2017-07-04	Regenerate configure.	Tristan Gingold	2	-10/+14
2017-07-03	Regenerate pot files.	Tristan Gingold	2	-133/+150
2017-06-30	MIPS/opcodes: Reorder LSA and DLSA instructions	Maciej W. Rozycki	2	-3/+8
2017-06-30	MIPS: Add Imagination interAptiv MR2 MIPS32r3 processor support (ChangeLog)	Maciej W. Rozycki	1	-1/+1