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2020-09-02CSKY: Add CPU CK803r3.Cooper Qu2-2/+7
2020-09-02CSKY: Fix Encode of mulsws.Cooper Qu2-1/+5
2020-09-01mep: ubsan: mep-ibld.c:1635,1645,1652 left shift of negative valueAlan Modra2-5/+9
2020-08-31CSKY: Refine operand format error reporting.Cooper Qu2-0/+6
2020-08-30cr16 disassembly error of disp20 fieldsAlan Modra2-63/+60
2020-08-29PR26446 UBSAN: tc-csky.c:2618,4022 index out of boundsAlan Modra2-2/+8
2020-08-28PR26449, PR26450 UBSAN: frv-ibld.c:135 left shiftAlan Modra16-90/+133
2020-08-28CSKY: Support attribute section.Cooper Qu3-11/+49
2020-08-26opcodes: Add missing entries to ebpf_isa_attrJose E. Marchesi2-1/+5
2020-08-26bpf: add xBPF ISADavid Faust6-283/+330
2020-08-25PR26504, ASAN: parse_disassembler_options vax-dis.c:142Alan Modra2-2/+8
2020-08-24CSKY: Add new arch CK860.Cooper Qu3-6/+128
2020-08-24CSKY: Add ck803r2 series cpu.Cooper Qu2-2/+13
2020-08-21Fix problems with the AArch64 linker exposed by testing it with sanitization ...Nick Clifton2-1/+14
2020-08-21CSKY: Support two operands form for bloop.Cooper Qu2-4/+11
2020-08-19Correct vcmpsq, vcmpuq and xvtlsbb BF fieldAlan Modra2-3/+8
2020-08-18Add ChangeLog entries for previous commit.Peter Bergner1-0/+5
2020-08-18PowerPC: Rename xvcvbf16sp to xvcvbf16spnPeter Bergner1-1/+1
2020-08-12aarch64: Add support for MPAM system registersAlex Coplan2-0/+21
2020-08-12Updated Serbian and Russian translations for various sub-directoriesNick Clifton2-244/+318
2020-08-11PowerPC CELL cctp*Alan Modra2-4/+11
2020-08-10[aarch64] GAS doesn't validate the architecture version for any tlbi register...Przemyslaw Wirkus2-102/+105
2020-08-10Implement missing powerpc mtspr and mfspr extended insnsAlan Modra2-6/+161
2020-08-10Implement missing powerpc extended mnemonicsAlan Modra2-7/+16
2020-08-10Prioritise mtfprd and mtvrd over mtvsrd in PowerPC disassemblyAlan Modra2-2/+7
2020-08-04Z8k: fix sout/soudb opcodes with direct addressChristian Groessler3-6/+13
2020-07-30x86: Add {disp16} pseudo prefixH.J. Lu4-20/+61
2020-07-29PR26279 Work around maybe-uninitialized warning in s390-mkopc.cAndreas Arnez2-1/+8
2020-07-24Updated German translation for the opcodes sub-directoryNick Clifton2-245/+319
2020-07-21Revert "x86: Don't display eiz with no scale"Jan Beulich2-1/+5
2020-07-15x86: Don't display eiz with no scaleH.J. Lu2-1/+7
2020-07-15x86: move putop() case labels to restore alphabetic sortingJan Beulich2-49/+52
2020-07-15x86: make PUSH/POP disassembly uniformJan Beulich2-30/+27
2020-07-15x86: avoid attaching suffixes to unambiguous insnsJan Beulich2-99/+58
2020-07-14x86-64: Zero-extend lower 32 bits displacement to 64 bitsH.J. Lu2-2/+13
2020-07-14arc: Detect usage of illegal double register pairsClaudiu Zissulescu2-3/+16
2020-07-14x86/Intel: debug registers are named DRnJan Beulich2-1/+5
2020-07-14x86: drop Rm and the 'L' macroJan Beulich2-74/+67
2020-07-14x86: drop Rdq, Rd, and MaskRJan Beulich6-63/+122
2020-07-14x86: simplify decode of opcodes valid only without any (embedded) prefixJan Beulich2-135/+61
2020-07-14x86: also use %BW / %DQ for kshift*Jan Beulich2-65/+35
2020-07-14x86: simplify decode of opcodes valid with (embedded) 66 prefix onlyJan Beulich8-4913/+1647
2020-07-14x86: drop further EVEX table entries that can be served by VEX onesJan Beulich4-42/+25
2020-07-14x86: drop need_vex_regJan Beulich3-53/+41
2020-07-14x86: drop Vex128 and Vex256Jan Beulich3-56/+65
2020-07-14x86: replace %LW by %DQJan Beulich4-52/+59
2020-07-14x86: merge/move logic determining the EVEX disp8 shiftJan Beulich2-29/+23
2020-07-14x86: extend %BW use to VP{COMPRESS,EXPAND}{B,W}Jan Beulich4-24/+22
2020-07-14x86-64: fix {,V}PCMPESTR{I,M} disassembly in Intel modeJan Beulich4-43/+35
2020-07-14x86: fold VCMP_Fixup() into CMP_Fixup()Jan Beulich4-74/+58
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