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AgeCommit message (Expand)AuthorFilesLines
2016-09-30Don't assign alt twiceH.J. Lu2-1/+5
2016-09-30[AArch64] PR target/20553, fix opcode mask for SIMD multiply by elementJiong Wang2-4/+9
2016-09-29Disallow 3-operand cmp[l][i] for ppc64Alan Modra2-73/+39
2016-09-26When building target binaries, ensure that the warning flags selected for the...Vlad Zakharov3-6/+56
2016-09-26[ARC] ISA alignment.Claudiu Zissulescu4-35/+67
2016-09-21[AArch64] Print spaces after commas in addressesRichard Sandiford2-8/+14
2016-09-21[AArch64] Use "must" rather than "should" in error messagesRichard Sandiford2-3/+8
2016-09-21[AArch64] Add SVE condition codesRichard Sandiford3-20/+72
2016-09-21[AArch64][SVE 31/32] Add SVE instructionsRichard Sandiford8-116/+9454
2016-09-21[AArch64][SVE 30/32] Add SVE instruction classesRichard Sandiford5-0/+217
2016-09-21[AArch64][SVE 29/32] Add new SVE core & FP register operandsRichard Sandiford7-20/+75
2016-09-21[AArch64][SVE 28/32] Add SVE FP immediate operandsRichard Sandiford11-50/+239
2016-09-21[AArch64][SVE 27/32] Add SVE integer immediate operandsRichard Sandiford11-100/+647
2016-09-21[AArch64][SVE 26/32] Add SVE MUL VL addressing modesRichard Sandiford10-38/+290
2016-09-21[AArch64][SVE 25/32] Add support for SVE addressing modesRichard Sandiford11-41/+739
2016-09-21[AArch64][SVE 24/32] Add AARCH64_OPND_SVE_PATTERN_SCALEDRichard Sandiford11-17/+126
2016-09-21[AArch64][SVE 23/32] Add SVE pattern and prfop operandsRichard Sandiford7-11/+127
2016-09-21[AArch64][SVE 22/32] Add qualifiers for merging and zeroing predicationRichard Sandiford2-0/+13
2016-09-21[AArch64][SVE 21/32] Add Zn and Pn registersRichard Sandiford11-1/+291
2016-09-21[AArch64][SVE 20/32] Add support for tied operandsRichard Sandiford3-16/+41
2016-09-21[AArch64][SVE 19/32] Refactor address-printing codeRichard Sandiford2-36/+65
2016-09-21[AArch64][SVE 18/32] Tidy definition of aarch64-opc.c:int_regRichard Sandiford2-18/+17
2016-09-21[AArch64][SVE 17/32] Add a prefix parameter to print_register_listRichard Sandiford2-13/+21
2016-09-21[AArch64][SVE 16/32] Use specific insert/extract methods for fpimmRichard Sandiford8-6/+40
2016-09-21[AArch64][SVE 15/32] Add {insert,extract}_all_fields helpersRichard Sandiford3-14/+50
2016-09-21[AArch64][SVE 14/32] Make aarch64_logical_immediate_p take an element sizeRichard Sandiford3-29/+39
2016-09-21[AArch64][SVE 13/32] Add an F_STRICT flagRichard Sandiford2-1/+14
2016-09-21[AArch64][SVE 02/32] Avoid hard-coded limit in indented_printRichard Sandiford2-5/+5
2016-09-16[ARC] Disassemble correctly extension instructions.Claudiu Zissulescu2-3/+7
2016-09-14Modify POWER9 support to match final ISA 3.0 documentation.Peter Bergner2-22/+23
2016-09-14Stop the ARC disassembler from seg-faulting if initialised without a BFD pres...Anton Kolesov2-3/+12
2016-09-12S/390: Add alternate processor names.Andreas Krebbel2-9/+21
2016-09-12S/390: Fix kmctr instruction type.Patrick Steuer2-1/+5
2016-09-07X86: Allow additional ISAs for IAMCU in assemblerH.J. Lu3-9/+5
2016-08-30Fixed issue with NULL pointer access on header var.Cupertino Miranda2-1/+8
2016-08-26opcodes, gas: fix mnemonic of sparc camellia_flJose E. Marchesi2-1/+6
2016-08-26Add missing ARMv8-M special registersThomas Preud'homme2-14/+29
2016-08-24X86: Add ptwrite instructionH.J. Lu7-5329/+5392
2016-08-24[ARC] C++ compatibility for arc-dis.hAnton Kolesov2-0/+13
2016-08-23[AArch64] Add V8_2_INSN macroRichard Sandiford2-2/+9
2016-08-23[AArch64] Make more use of CORE/FP/SIMD_INSNRichard Sandiford2-67/+72
2016-08-23[AArch64] Add OP parameter to aarch64-tbl.h macrosRichard Sandiford2-722/+727
2016-08-01 Fix some PowerPC VLE BFD issues and add some PowerPC VLE instructions.Andrew Jenner3-2/+40
2016-07-27MIPS/GAS: Implement microMIPS branch/jump compactionMaciej W. Rozycki2-7/+21
2016-07-27Begin implementing ARC NPS-400 Accelerator instructionsGraham Markall5-32/+283
2016-07-21Set BFD_VERSION to 2.27.51H.J. Lu2-10/+14
2016-07-20Add support to the ARC disassembler for selecting instruction classes.Claudiu Zissulescu3-127/+364
2016-07-13MIPS/opcodes: Address issues with NAL disassemblyMaciej W. Rozycki2-1/+6
2016-07-13opcodes,gas: support for the ldtxa SPARC instructions.Jose E. Marchesi2-0/+42
2016-07-08FT32: adjust disassembly opcode match fieldsjamesbowman2-2/+7
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