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2017-07-25Fix typos in error and option messages in OPCODES library.Nick Clifton3-36/+75
2017-07-24[AArch64] Fix the bit pattern order in the comments in auto-generated fileJiong Wang3-1689/+1699
2017-07-21S/390: Support z14 as CPU name.Andreas Krebbel2-1/+7
2017-07-20Update the German translation for the opcodes library.Nick Clifton2-466/+890
2017-07-19[ARC] Add SecureShield AUX registersclaziss2-0/+21
2017-07-19[ARC] Add SJLI instruction.Claudiu Zissulescu3-1/+27
2017-07-19[ARC] Add JLI support.John Eric Martin4-2/+17
2017-07-18Fix spelling typos.Yuri Chornovian3-2/+8
2017-07-14binutils/objdump: Fix disassemble for huge elf sectionsRavi Bangoria2-3/+8
2017-07-12Update PO filesAlan Modra16-875/+2049
2017-07-11Mark generated cgen files read-onlyAlan Modra96-8/+211
2017-07-07Move print_insn_XXX to an opcodes internal header, againAlan Modra4-3/+9
2017-07-05X86: Disassemble primary opcode map's group 2 ModRM.reg == 6 aliases correctlyBorislav Petkov2-6/+10
2017-07-05Fixup changelog entries for previous commitRamana Radhakrishnan1-0/+5
2017-07-04[Patch ARM] Support MVFR2 VFP Coprocessor register for ARMv8-ARamana Radhakrishnan1-0/+4
2017-07-04Regenerate configure.Tristan Gingold2-10/+14
2017-07-03Regenerate pot files.Tristan Gingold2-133/+150
2017-06-30MIPS/opcodes: Reorder LSA and DLSA instructionsMaciej W. Rozycki2-3/+8
2017-06-30MIPS: Add Imagination interAptiv MR2 MIPS32r3 processor support (ChangeLog)Maciej W. Rozycki1-1/+1
2017-06-30MIPS: Add microMIPS XPA supportMaciej W. Rozycki2-0/+19
2017-06-30MIPS: Add microMIPS R5 supportMaciej W. Rozycki2-0/+8
2017-06-30MIPS: Fix XPA base and Virtualization ASE instruction handlingMaciej W. Rozycki3-24/+53
2017-06-30MIPS/opcodes: Correctly combine ASE flags for ASE_MIPS16E2_MT calculationMaciej W. Rozycki2-3/+20
2017-06-29[ARC] Use FOR_EACH_DISASSEMBLER_OPTION to iterate over optionsAnton Kolesov2-14/+11
2017-06-29[ARC] Fix handling of cpu=... disassembler option valueAnton Kolesov2-8/+14
2017-06-28[AArch64] Add dot product support for AArch64 to binutilsTamar Christina5-179/+265
2017-06-28[ARM] Assembler and disassembler support Dot Product ExtensionJiong Wang2-0/+10
2017-06-28MIPS: Add Imagination interAptiv MR2 MIPS32r3 processor supportMaciej W. Rozycki5-73/+152
2017-06-23RISC-V: Fix SLTI disassemblyAndrew Waterman2-2/+7
2017-06-21x86: CET v2.0: Update incssp and setssbsyH.J. Lu4-25/+41
2017-06-21x86: CET v2.0: Rename savessp to saveprevsspH.J. Lu4-3/+9
2017-06-21x86: CET v2.0: Update NOTRACK prefixH.J. Lu2-8/+13
2017-06-19Prevent address violation when attempting to disassemble a corrupt score binary.Nick Clifton2-0/+6
2017-06-17Regen rx-decode.cAlan Modra2-712/+716
2017-06-15i386-dis: Check valid bnd registerH.J. Lu2-0/+16
2017-06-15Prevent address violation problem when disassembling corrupt aarch64 binary.Nick Clifton2-0/+9
2017-06-15Fix address violation when disassembling a corrupt RL78 binary.Nick Clifton3-411/+424
2017-06-15Prevent invalid array accesses when disassembling a corrupt bfin binary.Nick Clifton2-4/+12
2017-06-14Fix seg-fault when trying to disassemble a corrupt score binary.Nick Clifton2-1/+7
2017-06-14Don't use print_insn_XXX in GDBYao Qi7-5/+26
2017-06-14Fix address violation problems when disassembling a corrupt RX binary.Nick Clifton3-20/+37
2017-06-14[opcodes][arm] Remove bogus entry added by accident in former patchAndre Vieira2-2/+4
2017-06-01S/390: idte/ipte fixesAndreas Krebbel1-5/+2
2017-05-30[ARC] Allow CPU to be enforced via disassemble_info optionsAnton Kolesov2-26/+114
2017-05-30S/390: Fix instruction types of csdtr and csxtrAndreas Krebbel2-2/+6
2017-05-30S/390: Add missing operand to tb instructionAndreas Krebbel1-1/+1
2017-05-30S/390: Add ipte/idte variants with optional operandsAndreas Krebbel2-1/+4
2017-05-30S/390: Improve error checking for optional operandsAndreas Krebbel2-3/+16
2017-05-24Move print_insn_XXX to an opcodes internal headerYao Qi70-68/+198
2017-05-24Use disassemble.c:disassembler select rl78 disassemblerYao Qi2-1/+10
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