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2017-04-05
-Wwrite-strings: Constify struct disassemble_info's disassembler_options field
Pedro Alves
5
-6
/
+13
2017-04-04
RISC-V: Resurrect GP-relative disassembly hints
Palmer Dabbelt
2
-1
/
+6
2017-03-30
Add support for the WebAssembly file format and the wasm32 ELF conversion to ...
Pip Cet
4
-158
/
+189
2017-03-29
opcodes: sparc: support missing SPARC ASIs from UA2005, UA2007, OSA2011, & OS...
Jose E. Marchesi
2
-0
/
+34
2017-03-29
PowerPC -Mraw disassembly
Alan Modra
2
-10
/
+26
2017-03-27
PR21303, objdump doesn't show e200z4 insns
Alan Modra
2
-2
/
+19
2017-03-27
Implement ARC NPS-400 Ultra Ip and Miscellaneous instructions.
Rinat Zelig
3
-350
/
+612
2017-03-21
S/390: Remove vx2 facility flag
Andreas Krebbel
3
-146
/
+147
2017-03-21
arc/nps400: Add cp16/cp32 instructions to opcodes library
Rinat Zelig
3
-3
/
+279
2017-03-17
E6500 spr mnemonics
Alan Modra
2
-8
/
+15
2017-03-15
RISC-V: Fix assembler for c.li, c.andi and c.addiw
Kito Cheng
2
-3
/
+9
2017-03-15
RISC-V: Fix assembler for c.addi, rd can be x0
Kito Cheng
2
-1
/
+5
2017-03-14
RISC-V: Fix [dis]assembly of srai/srli
Andrew Waterman
2
-4
/
+11
2017-03-09
X86: Add pseudo prefixes to control encoding
H.J. Lu
5
-73
/
+183
2017-03-09
Use CpuCET on rdsspq
H.J. Lu
3
-2
/
+7
2017-03-08
Update -maltivec and -mvsx options to only enable their oldest instructions.
Peter Bergner
2
-2
/
+7
2017-03-08
Add support for the new 'lnia' extended mnemonic.
Peter Bergner
2
-0
/
+7
2017-03-06
Add support for Intel CET instructions
H.J. Lu
7
-334
/
+681
2017-03-06
Don't decode powerpc insns with invalid fields
Alan Modra
2
-49
/
+168
2017-02-28
GDB: Add support for the new set/show disassembler-options commands.
Peter Bergner
6
-218
/
+394
2017-02-28
x86: fix handling of 64-bit operand size VPCMPESTR{I,M}
Jan Beulich
4
-26
/
+170
2017-02-24
[AArch64] Additional SVE instructions
Richard Sandiford
11
-2089
/
+2815
2017-02-24
[AArch64] Add a "compnum" feature
Richard Sandiford
2
-6
/
+17
2017-02-24
x86: also correctly support TEST opcode aliases
Jan Beulich
2
-2
/
+6
2017-02-23
S/390: Add support for new cpu architecture - arch12.
Andreas Krebbel
3
-79
/
+311
2017-02-23
opcodes,gas: associate SPARC ASIs with an architecture level.
Sheldon Lobo
2
-195
/
+196
2017-02-23
x86: drop stray VEX opcode 82 references
Jan Beulich
2
-4
/
+9
2017-02-22
aarch64: actually copy first operand in convert_bfc_to_bfm()
Jan Beulich
2
-2
/
+7
2017-02-15
Add SFENCE.VMA instruction
Andrew Waterman
2
-0
/
+8
2017-02-15
[AArch64] Add SVE system registers
Richard Sandiford
2
-0
/
+21
2017-02-15
[ARC] Fix assembler relaxation.
Claudiu Zissulescu
2
-34
/
+75
2017-02-15
Distinguish some of the registers different on ARC700 and HS38 cpus
Vineet Gupta
2
-12
/
+41
2017-02-14
PowerPC register expression checks
Alan Modra
2
-5
/
+11
2017-02-11
Fix use after free in cgen instruction lookup
Alan Modra
2
-15
/
+20
2017-02-10
POWER9 add scv/rfscv instruction support
Nicholas Piggin
2
-1
/
+7
2017-02-06
[ARC] Provide an interface to decode ARC instructions.
Claudiu Zissulescu
4
-363
/
+609
2017-02-03
Fix compile time warning messages when compiling binutils with gcc 7.0.1.
Nick Clifton
3
-5
/
+16
2017-01-27
Fix disassembling of TIC6X parallel instructions where the previous fetch pac...
Alexis Deruell
2
-2
/
+18
2017-01-25
Clarify that include/opcode/ files are part of GNU opcodes
Dimitar Dimitrov
2
-2
/
+5
2017-01-20
Updated Irish translation for the opcodes library.
Nick Clifton
2
-458
/
+813
2017-01-18
[ARM] Fix the decoding of indexed element VCMLA instruction
Szabolcs Nagy
2
-4
/
+8
2017-01-13
Return -1 on memory error in print_insn_m68k
Yao Qi
2
-7
/
+19
2017-01-13
Remove magic numbers in m68k-dis.c:print_insn_arg
Yao Qi
2
-41
/
+72
2017-01-12
Enable Intel AVX512_VPOPCNTDQ instructions
Igor Tsimbalist
8
-5344
/
+5432
2017-01-12
Return -1 on memory error in print_insn_msp430
Yao Qi
2
-14
/
+99
2017-01-05
Prevent an abort in the FRV disassembler if the target bfd name is unknown.
Nick Clifton
2
-3
/
+11
2017-01-04
[AArch64] Add separate feature flag for weaker release consistent load insns
Szabolcs Nagy
2
-3
/
+13
2017-01-03
Add support for the Q extension to the RISCV ISA.
Kito Cheng
2
-0
/
+66
2017-01-03
Add fall through comment.
Dilyan Palauzov
2
-0
/
+5
2017-01-03
Add new Serbian translation for the opcodes library.
Nick Clifton
4
-2
/
+1515
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