aboutsummaryrefslogtreecommitdiff
path: root/opcodes
AgeCommit message (Collapse)AuthorFilesLines
2005-06-23 * m68k-dis.c: Use ISC C90.Ben Elliston3-54/+32
* m68k-opc.c: Formatting fixes.
2005-06-16* mips16-opc.c (mips16_opcodes): Add the following MIPS16eDavid Ung2-0/+12
instructions to the table; seb/seh/sew/zeb/zeh/zew.
2005-06-152005-06-15 Dave Brolley <brolley@redhat.com>Dave Brolley13-8/+5973
Contribute Morpho ms1 on behalf of Red Hat * ms1-asm.c, ms1-desc.c, ms1-dis.c, ms1-ibld.c, ms1-opc.c, ms1-opc.h: New files, Morpho ms1 target. 2004-05-14 Stan Cox <scox@redhat.com> * disassemble.c (ARCH_ms1): Define. (disassembler): Handle bfd_arch_ms1 2004-05-13 Michael Snyder <msnyder@redhat.com> * Makefile.am, Makefile.in: Add ms1 target. * configure.in: Ditto.
2005-06-08opcodes:Zack Weinberg5-134/+91
* arm-opc.h: Delete; fold contents into ... * arm-dis.c: ... here. Move includes of internal COFF headers next to includes of internal ELF headers. (streq, WORD_ADDRESS, BDISP, BDISP23): Delete, unused. (struct arm_opcode): Rename struct opcode32. Make 'assembler' const. (struct thumb_opcode): Rename struct opcode16. Make 'assembler' const. (arm_conditional, arm_fp_const, arm_shift, arm_regname, regnames) (iwmmxt_wwnames, iwmmxt_wwssnames): Make const. (regnames): Remove iWMMXt coprocessor register sets. (iwmmxt_regnames, iwmmxt_cregnames): New statics. (get_arm_regnames): Adjust fourth argument to match above changes. (set_iwmmxt_regnames): Delete. (print_insn_arm): Constify 'c'. Use ISO syntax for function pointer calls. Expand sole use of BDISP. Use iwmmxt_regnames and iwmmxt_cregnames, not set_iwmmxt_regnames. (print_insn_thumb16, print_insn_thumb32): Constify 'c'. Use ISO syntax for function pointer calls. include: * dis-asm.h (get_arm_regnames): Update prototype.
2005-06-07 * arm-dis.c: Split up the comments describing the format codes, soZack Weinberg2-139/+118
that the ARM and 16-bit Thumb opcode tables each have comments preceding them that describe all the codes, and only the codes, valid in those tables. (32-bit Thumb table is already like this.) Reorder the lists in all three comments to match the order in which the codes are implemented. Remove all forward declarations of static functions. Convert all function definitions to ISO C format. (print_insn_arm, print_insn_thumb16, print_insn_thumb32): Return nothing. (print_insn_thumb16): Remove unused case 'I'. (print_insn): Update for changed calling convention of subroutines.
2005-05-25gas/testsuite/Jan Beulich2-17/+56
2005-05-25 Jan Beulich <jbeulich@novell.com> * gas/i386/intelok.d: Account for 32-bit displacements being shown in hex. opcodes/ 2005-05-25 Jan Beulich <jbeulich@novell.com> * i386-dis.c (OP_E): In Intel mode, display 32-bit displacements in hex (but retain it being displayed as signed). Remove redundant checks. Add handling of displacements for 16-bit addressing in Intel mode.
2005-05-25opcodes/Jan Beulich2-10/+11
2005-05-25 Jan Beulich <jbeulich@novell.com> * i386-dis.c (prefix_name): Remove pointless mode_64bit check. (OP_E): Remove redundant REX_EXTZ handling. Remove pointless masking of 'rm' in 16-bit memory address handling.
2005-05-19 * ppc-dis.c (powerpc_dialect): Handle "-Mpower5".Alan Modra3-5/+35
(print_ppc_disassembler_options): Document it. * ppc-opc.c (SCV_LEV): Define. (LEV): Allow optional operand. (POWER5): Define. (powerpc_opcodes): Extend "sc". Adjust "svc" and "svcl". Add "hrfid", "popcntb", "fsqrtes", "fsqrtes.", "fre" and "fre.".
2005-05-192005-05-19 Kelley Cook <kcook@gcc.gnu.org>Kelley Cook2-1/+4
* Makefile.in: Regenerate.
2005-05-18include/elf:Zack Weinberg2-339/+986
* arm.h: Import complete list of official relocation names and numbers from AAELF. Define FAKE_RELOCs for old names. Remove a few old names no longer used anywhere. bfd: * elf32-arm.c: Wherever possible, use official reloc names from AAELF. (elf32_arm_howto_table, elf32_arm_tls_gd32_howto) (elf32_arm_tls_ldo32_howto, elf32_arm_tls_ldm32_howto) (elf32_arm_tls_le32_howto, elf32_arm_tls_ie32_howto) (elf32_arm_vtinherit_howto, elf32_arm_vtentry_howto) (elf32_arm_pc11_howto, elf32_arm_thm_pc9_howto, elf32_arm_got_prel) (elf32_arm_r_howto): Replace with elf32_arm_howto_table_1, elf32_arm_howto_table_2, and elf32_arm_howto_table_3. Add many new relocations from AAELF. (elf32_arm_howto_from_type): Update to match. (elf32_arm_reloc_map): Add entries for R_ARM_THM_JUMP24, R_ARM_THM_JUMP11, R_ARM_THM_JUMP19, R_ARM_THM_JUMP8, R_ARM_THM_JUMP6, R_ARM_GNU_VTINHERIT, and R_ARM_GNU_VTENTRY. (elf32_arm_reloc_type_lookup): Use elf32_arm_howto_from_type. (elf32_arm_final_link_relocate): Add support for R_ARM_THM_JUMP24, R_ARM_THM_JUMP19, R_ARM_THM_JUMP6. Remove case entries redundant with default. * reloc.c: Reorganize ARM relocations. Add Thumb assembler-internal relocations BFD_RELOC_ARM_T32_OFFSET_U8, BFD_RELOC_ARM_T32_OFFSET_IMM, BFD_RELOC_ARM_T32_IMMEDIATE. Add visible relocations BFD_RELOC_THUMB_PCREL_BRANCH7, BFD_RELOC_THUMB_BRANCH20, BFD_RELOC_THUMB_BRANCH25. Delete unused relocations BFD_RELOC_ARM_GOT12, BFD_RELOC_ARM_COPY. * bfd-in2.h, libbfd.h: Regenerate. opcodes: * arm-dis.c (thumb_opcodes): Add disassembly for V6T2 16-bit instructions. Adjust disassembly of some opcodes to match unified syntax. (thumb32_opcodes): New table. (print_insn_thumb): Rename print_insn_thumb16; don't handle two-halfword branches here. (print_insn_thumb32): New function. (print_insn): Choose among print_insn_arm, print_insn_thumb16, and print_insn_thumb32. Be consistent about order of halfwords when printing 32-bit instructions. gas: * hash.c (hash_lookup): Add len parameter. All callers changed. (hash_find_n): New interface. * hash.h: Prototype hash_find_n. * sb.c: Include as.h. (scrub_from_sb, sb_to_scrub, scrub_position): New statics. (sb_scrub_and_add_sb): New interface. * sb.h: Prototype sb_scrub_and_add_sb. * input-scrub.c (input_scrub_include_sb): Use sb_scrub_and_add_sb. * config/tc-arm.h (TC_FORCE_RELOCATION_LOCAL): Remove reference to BFD_RELOC_ARM_GOT12 which is never generated. * config/tc-arm.c: Rewrite, adding Thumb-2 support. gas/testsuite: * gas/arm/arm.exp: Convert all existing "gas_test" tests to "run_dump_test" tests. Run more tests unconditionally. Run new tests. * gas/arm/arch4t.s, gas/arm/arch6zk.s, gas/arm/arm3.s, gas/arm/arm6.s * gas/arm/arm7dm.s, gas/arm/bignum1.s, gas/arm/float.s * gas/arm/immed.s, gas/arm/iwmmxt.s, gas/arm/offset.s, gas/arm/thumb.s: Adjust to work as a dump test. * gas/arm/arch4t.d, gas/arm/arch6zk.d, gas/arm/arm3.d, gas/arm/arm6.d * gas/arm/arm7dm.d, gas/arm/bignum1.d, gas/arm/float.d * gas/arm/immed.d, gas/arm/iwmmxt.d, gas/arm/offset.d, gas/arm/thumb.d: New files. * gas/arm/armv1-bad.l, gas/arm/armv1-bad.s: Remove tests for diagnostics that don't happen in the first pass anymore. * gas/arm/iwmmxt-bad.l, gas/arm/r15-bad.l, gas/arm/req.l * gas/arm/vfp-bad.l: Update expected diagnostics. * gas/arm/pic.d: Update expected reloc name. * gas/arm/thumbv6.d: CPY no longer appears in disassembly. * gas/arm/r15-bad.s: Avoid two-argument mul. * gas/arm/req.s: Adjust comments. * gas/arm/maverick.d, gas/arm/maverick.s: Avoid inappropriate use of PC. * gas/arm/macro-1.d, gas/arm/macro1.s * gas/arm/t16-bad.l, gas/arm/t16-bad.s * gas/arm/tcompat.d, gas/arm/tcompat.s * gas/arm/tcompat2.d, gas/arm/tcompat2.s * gas/arm/thumb32.d, gas/arm/thumb32.s New test pair. ld/testsuite: * ld-arm/mixed-app.d: Adjust expected disassembly a little.
2005-05-07gas/testsuite/H.J. Lu2-1/+22
2005-05-07 H.J. Lu <hongjiu.lu@intel.com> PR 843 * gas/i386/i386.exp: Add x86-64-branch. * gas/i386/x86-64-branch.d: New. * gas/i386/x86-64-branch.s: New. opcodes/ 2005-05-07 H.J. Lu <hongjiu.lu@intel.com> PR 843 * i386-dis.c (branch_v_mode): New. (indirEv): Use branch_v_mode instead of v_mode. (OP_E): Handle branch_v_mode.
2005-05-072005-05-07 H.J. Lu <hongjiu.lu@intel.com>H.J. Lu2-1/+6
* d10v-dis.c (dis_2_short): Support 64bit host.
2005-05-07Update Dutch translationNick Clifton2-153/+178
2005-05-07Update the address and phone number of the FSFNick Clifton156-217/+255
2005-05-05Fix ia64-hpux build failure.Jim Wilson2-1/+5
* ia64-opc.c: Include sysdep.h before libiberty.h.
2005-05-05* configure.in (ALL_LINGUAS): Add vi.Nick Clifton4-2/+813
* configure: Regenerate. * po/vi.po: New.
2005-04-26 * configure.in: Fix the check for basename declaration.Jerome Guitton3-3/+7
* configure: Regenerate.
2005-04-19 * ppc-opc.c (RTO): Define.Alan Modra2-6/+10
(powerpc_opcodes <tlbsx, tlbsx., tlbre>): Combine PPC403 and BOOKE entries to suit PPC440.
2005-04-18gas/ChangeLog:Mark Kettenis2-8/+13
* config/tc-i386.c (md_begin): Allow hyphens in mnemonics. include/opcode/ChangeLog: * i386.h: Insert hyphens into selected VIA PadLock extensions. Add xcrypt-ctr. Provide aliases without hyphens. opcodes/ChangeLog: * i386-dis.c: Insert hyphens into selected VIA PadLock extensions. Add xcrypt-ctr.
2005-04-14* po/fi.po: New translation: Finnish.Nick Clifton4-2/+820
* configure.in (ALL_LINGUAS): Add fi. * configure: Regenerate.
2005-04-14bfd/Alan Modra6-59/+41
* Makefile.am (NO_WERROR): Define. * warning.m4: New file * acinclude.m4: Include warning.m4. * configure.in: Invoke AM_BINUTILS_WARNINGS. * Makefile.in: Regenerate. * configure: Regenerate. bfd/doc/ * Makefile.in: Regenerate. binutils/ * Makefile.am (NO_WERROR): Define. Use instead of -Wno-error. * configure.in: Include ../bfd/warning.m4 contents. * Makefile.in: Regenerate. * configure: Regenerate. * doc/Makefile.in: Regenerate. gas/ * Makefile.am (NO_WERROR): Define. Use instead of -Wno-error. * acinclude.m4: Include ../bfd/warning.m4. * configure.in: Invoke AM_BINUTILS_WARNINGS. * Makefile.in: Regenerate. * configure: Regenerate. * doc/Makefile.in: Regenerate. gprof/ * Makefile.am (NO_WERROR): Define. * acinclude.m4: Include ../bfd/warning.m4. * configure.in: Invoke AM_BINUTILS_WARNINGS. * Makefile.in: Regenerate. * aclocal.m4: Regenerate. * configure: Regenerate. ld/ * Makefile.am (NO_WERROR): Define. Use instead of -Wno-error. * configure.in: Include ../bfd/warning.m4 contents. * Makefile.in: Regenerate. * configure: Regenerate. opcodes/ * Makefile.am (NO_WERROR): Define. * configure.in: Invoke AM_BINUTILS_WARNINGS. * Makefile.in: Regenerate. * aclocal.m4: Regenerate. * configure: Regenerate.
2005-04-04Initialise value to zero to avoid a compile time warning.Nick Clifton6-14/+21
2005-04-01opcodes/Jan Beulich2-4/+26
2005-04-01 Jan Beulich <jbeulich@novell.com> * i386-dis.c (PNI_Fixup): Neither mwait nor monitor have any visible operands in Intel mode. The first operand of monitor is %rax in 64-bit mode.
2005-04-01include/opcode/Jan Beulich2-8/+20
2005-04-01 Jan Beulich <jbeulich@novell.com> * i386.h (i386_optab): Add rdtscp. opcodes/ 2005-04-01 Jan Beulich <jbeulich@novell.com> * i386-dis.c (INVLPG_Fixup): Decode rdtscp; change code to allow for easier future additions.
2005-03-31 * configure.in: Check for basename.Jerome Guitton4-0/+86
* configure: Regenerate. * config.in: Ditto.
2005-03-29gas/testsuite/H.J. Lu2-2/+59
2005-03-29 H.J. Lu <hongjiu.lu@intel.com> * gas/i386/i386.exp: Run segment and inval-seg for i386. Run x86-64-segment and x86-64-inval-seg for x86-64. * gas/i386/intel.d: Expect movw for moving between memory and segment register. * gas/i386/naked.d: Likewise. * gas/i386/opcode.d: Likewise. * gas/i386/x86-64-opcode.d: Likewise. * gas/i386/opcode.s: Use movw for moving between memory and segment register. * gas/i386/x86-64-opcode.s: Likewise. * : Likewise. * gas/i386/inval-seg.l: New. * gas/i386/inval-seg.s: New. * gas/i386/segment.l: New. * gas/i386/segment.s: New. * gas/i386/x86-64-inval-seg.l: New. * gas/i386/x86-64-inval-seg.s: New. * gas/i386/x86-64-segment.l: New. * gas/i386/x86-64-segment.s: New. include/opcode/ 2005-03-29 H.J. Lu <hongjiu.lu@intel.com> * i386.h (i386_optab): Don't allow the `l' suffix for moving moving between memory and segment register. Allow movq for moving between general-purpose register and segment register. opcodes/ 2005-03-29 H.J. Lu <hongjiu.lu@intel.com> * i386-dis.c (SEG_Fixup): New. (Sv): New. (dis386): Use "Sv" for 0x8c and 0x8e.
2005-03-29Add VAX specific disassembler option -Mentry: to specify a function entryNick Clifton2-10/+124
address, and add code to test this new option.
2005-03-232005-03-23 H.J. Lu <hongjiu.lu@intel.com>H.J. Lu2-1/+6
* cris-dis.c (print_with_operands): Use ~31L for long instead of ~31.
2005-03-202005-03-20 H.J. Lu <hongjiu.lu@intel.com>H.J. Lu2-2/+7
* mmix-opc.c (O): Revert the last change. (Z): Likewise.
2005-03-192005-03-19 H.J. Lu <hongjiu.lu@intel.com>H.J. Lu2-2/+7
* mmix-opc.c (O): Use 24UL instead of 24 for unsigned long. (Z): Likewise.
2005-03-19 * mmix-opc.c (O, Z): Force expression as unsigned long.Hans-Peter Nilsson2-2/+6
2005-03-18Change wording of error message to "percent-operand" from "%operand" as theNick Clifton3-54/+47
latter confuses xgettext into thinking that it is a C printf formating directive, which prevents proper translation.
2005-03-16Rename switch to enable/disable -Werror to --enable-werror/--disable-werrorNick Clifton3-14/+14
for compatibility with gcc.
2005-03-16Enable -Werror by defaultNick Clifton3-1/+46
2005-03-16 * ppc-dis.c (powerpc_dialect): Don't set PPC_OPCODE_ALTIVEC whenAlan Modra2-17/+14
BOOKE.
2005-03-15Commit new Spanish translation.Alan Modra2-156/+179
2005-03-14Commit new French translation.Alan Modra2-149/+174
2005-03-14Use ".word 0x0012 # Entry mask: r1 r2 >" instead of just "Entry mask: < r1 ↵Nick Clifton2-13/+19
... >"
2005-03-12gas:Zack Weinberg2-0/+8
* config/tc-arm.c (tinsns): Add ARMv6K instructions sev, wfe, wfi, yield. opcodes: * arm-dis.c (thumb_opcodes): Add ARMv6K instructions nop, sev, wfe, wfi, yield. gas/testsuite: * gas/arm/thumbv6k.d, gas/arm/thumbv6k.s: New dump test. * gas/arm/arm.exp: Run it.
2005-03-12Revert accidental commit of V6K opsZack Weinberg1-7/+0
2005-03-12include:Zack Weinberg2-2/+61
* opcode/arm.h: Adjust comments for ARM_EXT_V4T and ARM_EXT_V5T. Add ARM_EXT_V6T2, ARM_ARCH_V6T2, ARM_ARCH_V6KT2, ARM_ARCH_V6ZT2, and ARM_ARCH_V6ZKT2. opcodes: * arm-dis.c (arm_opcodes): Document %E and %V. Add entries for v6T2 ARM instructions: bfc bfi mls strht ldrht ldrsht ldrsbt movw movt rbit ubfx sbfx. (print_insn_arm): Add support for %E and %V.
2005-03-10opcodes/Alan Modra2-13/+61
* ppc-opc.c (insert_sprg, extract_sprg): New Functions. (powerpc_operands <SPRG>): Call the above. Bit field is 5 bits. (SPRG_MASK): Delete. (XSPRG_MASK): Mask off extra bits now part of sprg field. (powerpc_opcodes): Asjust mfsprg and mtsprg to suit new mask. Move mfsprg4..7 after msprg and consolidate. gas/testsuite * gas/ppc/booke.s: Add new m[t,f]sprg testcases. * gas/ppc/booke.d: Likewise.
2005-03-09 * vax-dis.c (entry_mask_bit): New array.Alan Modra2-2/+44
(print_insn_vax): Decode function entry mask.
2005-03-07 * ppc-opc.c (powerpc_opcodes): Fix encoding of efscfd.Aldy Hernandez2-1/+5
2005-03-05Regenerate .pot filesAlan Modra2-111/+115
2005-03-032005-03-03 Ramana Radhakrishnan <ramana.radhakrishnan@codito.com>Ramana Radhakrishnan2-29/+54
* opcodes/arc-dis.c:Add enum a4_decoding_class. (dsmOneArcInst): Use the enum values for the decoding class Remove redundant case in the switch for decodingClass value 11
2005-03-03update copyright datesAlan Modra43-47/+55
2005-03-02gas/Jan Beulich2-4/+19
2005-03-02 Jan Beulich <jbeulich@novell.com> * config/tc-i386.c (build_modrm_byte): Add lock prefix for cr8...15 accesses. (parse_register): Allow cr8...15 in all modes. gas/testsuite/ 2005-03-02 Jan Beulich <jbeulich@novell.com> * gas/i386/cr-err.[ls]: New. * gas/i386/crx.[ds]: New. * gas/i386/i386.exp: Run new tests. opcodes/ 2005-03-02 Jan Beulich <jbeulich@novell.com> * i386-dis.c (print_insn): Suppress lock prefix printing for cr8...15 accesses. (OP_C): Consider lock prefix in non-64-bit modes.
2005-02-24 * cris-dis.c (format_hex): Remove ineffective warning fix.Alan Modra4-7/+12
* crx-dis.c (make_instruction): Warning fix. * frv-asm.c: Regenerate.
2005-02-23Fix compile time warnings generated by gcc 4.0Nick Clifton17-312/+307
generated by cgit v1.1 at 2024-11-30 16:01:06 +0000